1 |
/* |
/* |
2 |
* Copyright (C) 2005 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
3 |
* |
* |
4 |
* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
5 |
* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: cpu_sparc.c,v 1.11 2005/12/11 21:34:43 debug Exp $ |
* $Id: cpu_sparc.c,v 1.44 2007/03/26 02:18:44 debug Exp $ |
29 |
* |
* |
30 |
* SPARC CPU emulation. |
* SPARC CPU emulation. |
31 |
*/ |
*/ |
39 |
#include "machine.h" |
#include "machine.h" |
40 |
#include "memory.h" |
#include "memory.h" |
41 |
#include "misc.h" |
#include "misc.h" |
42 |
|
#include "settings.h" |
43 |
#include "symbol.h" |
#include "symbol.h" |
44 |
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|
45 |
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|
46 |
#define DYNTRANS_DUALMODE_32 |
#define DYNTRANS_DUALMODE_32 |
47 |
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#define DYNTRANS_DELAYSLOT |
48 |
#include "tmp_sparc_head.c" |
#include "tmp_sparc_head.c" |
49 |
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|
50 |
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|
51 |
static char *sparc_regnames[N_SPARC_REG] = SPARC_REG_NAMES; |
static char *sparc_regnames[N_SPARC_REG] = SPARC_REG_NAMES; |
52 |
|
static char *sparc_pregnames[N_SPARC_PREG] = SPARC_PREG_NAMES; |
53 |
static char *sparc_regbranch_names[N_SPARC_REGBRANCH_TYPES] = |
static char *sparc_regbranch_names[N_SPARC_REGBRANCH_TYPES] = |
54 |
SPARC_REGBRANCH_NAMES; |
SPARC_REGBRANCH_NAMES; |
55 |
static char *sparc_branch_names[N_SPARC_BRANCH_TYPES] = SPARC_BRANCH_NAMES; |
static char *sparc_branch_names[N_SPARC_BRANCH_TYPES] = SPARC_BRANCH_NAMES; |
89 |
cpu->byte_order = EMUL_BIG_ENDIAN; |
cpu->byte_order = EMUL_BIG_ENDIAN; |
90 |
cpu->is_32bit = (cpu->cd.sparc.cpu_type.bits == 32)? 1 : 0; |
cpu->is_32bit = (cpu->cd.sparc.cpu_type.bits == 32)? 1 : 0; |
91 |
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|
92 |
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cpu->instruction_has_delayslot = sparc_cpu_instruction_has_delayslot; |
93 |
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|
94 |
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/* TODO: Separate this into 64-bit vs 32-bit? */ |
95 |
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cpu->translate_v2p = sparc_translate_v2p; |
96 |
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|
97 |
if (cpu->is_32bit) { |
if (cpu->is_32bit) { |
98 |
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cpu->run_instr = sparc32_run_instr; |
99 |
cpu->update_translation_table = |
cpu->update_translation_table = |
100 |
sparc32_update_translation_table; |
sparc32_update_translation_table; |
101 |
cpu->invalidate_translation_caches = |
cpu->invalidate_translation_caches = |
103 |
cpu->invalidate_code_translation = |
cpu->invalidate_code_translation = |
104 |
sparc32_invalidate_code_translation; |
sparc32_invalidate_code_translation; |
105 |
} else { |
} else { |
106 |
|
cpu->run_instr = sparc_run_instr; |
107 |
cpu->update_translation_table = sparc_update_translation_table; |
cpu->update_translation_table = sparc_update_translation_table; |
108 |
cpu->invalidate_translation_caches = |
cpu->invalidate_translation_caches = |
109 |
sparc_invalidate_translation_caches; |
sparc_invalidate_translation_caches; |
135 |
} |
} |
136 |
} |
} |
137 |
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|
138 |
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/* After a reset, the Tick register is not readable by user code: */ |
139 |
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cpu->cd.sparc.tick |= SPARC_TICK_NPT; |
140 |
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|
141 |
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/* Insert number of Windows and Trap levels into the version reg.: */ |
142 |
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cpu->cd.sparc.ver |= N_REG_WINDOWS | (MAXTL << SPARC_VER_MAXTL_SHIFT); |
143 |
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|
144 |
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/* Misc. initial settings suitable for userland emulation: */ |
145 |
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cpu->cd.sparc.cansave = cpu->cd.sparc.cpu_type.nwindows - 2; |
146 |
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cpu->cd.sparc.canrestore = 0; |
147 |
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cpu->cd.sparc.cleanwin = 1; |
148 |
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cpu->cd.sparc.otherwin = 0; |
149 |
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|
150 |
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if (cpu->cd.sparc.cansave + cpu->cd.sparc.canrestore |
151 |
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+ cpu->cd.sparc.otherwin != cpu->cd.sparc.cpu_type.nwindows - 2) { |
152 |
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fatal("Fatal internal error: inconsistent windowing " |
153 |
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"parameters!\n"); |
154 |
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exit(1); |
155 |
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} |
156 |
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|
157 |
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if (cpu->cd.sparc.cpu_type.nwindows > N_REG_WINDOWS) { |
158 |
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fatal("Fatal internal error: nwindows = %1 is more than %i\n", |
159 |
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cpu->cd.sparc.cpu_type.nwindows, N_REG_WINDOWS); |
160 |
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exit(1); |
161 |
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} |
162 |
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|
163 |
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CPU_SETTINGS_ADD_REGISTER64("pc", cpu->pc); |
164 |
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CPU_SETTINGS_ADD_REGISTER64("y", cpu->cd.sparc.y); |
165 |
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CPU_SETTINGS_ADD_REGISTER64("pstate", cpu->cd.sparc.pstate); |
166 |
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for (i=0; i<N_SPARC_REG; i++) |
167 |
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CPU_SETTINGS_ADD_REGISTER64(sparc_regnames[i], |
168 |
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cpu->cd.sparc.r[i]); |
169 |
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/* TODO: Handler for writes to the zero register! */ |
170 |
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|
171 |
return 1; |
return 1; |
172 |
} |
} |
173 |
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|
185 |
i = 0; |
i = 0; |
186 |
while (tdefs[i].name != NULL) { |
while (tdefs[i].name != NULL) { |
187 |
debug("%s", tdefs[i].name); |
debug("%s", tdefs[i].name); |
188 |
for (j=10 - strlen(tdefs[i].name); j>0; j--) |
for (j=16 - strlen(tdefs[i].name); j>0; j--) |
189 |
debug(" "); |
debug(" "); |
190 |
i++; |
i++; |
191 |
if ((i % 6) == 0 || tdefs[i].name == NULL) |
if ((i % 4) == 0 || tdefs[i].name == NULL) |
192 |
debug("\n"); |
debug("\n"); |
193 |
} |
} |
194 |
} |
} |
225 |
|
|
226 |
debug("cpu%i: pc = 0x", x); |
debug("cpu%i: pc = 0x", x); |
227 |
if (bits32) |
if (bits32) |
228 |
debug("%08x", (int)cpu->pc); |
debug("%08"PRIx32, (uint32_t) cpu->pc); |
229 |
else |
else |
230 |
debug("%016llx", (long long)cpu->pc); |
debug("%016"PRIx64, (uint64_t) cpu->pc); |
231 |
debug(" <%s>\n", symbol != NULL? symbol : " no symbol "); |
debug(" <%s>\n", symbol != NULL? symbol : " no symbol "); |
232 |
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|
233 |
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debug("cpu%i: y = 0x%08"PRIx32" ", |
234 |
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x, (uint32_t)cpu->cd.sparc.y); |
235 |
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debug("icc = "); |
236 |
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debug(cpu->cd.sparc.ccr & SPARC_CCR_N? "N" : "n"); |
237 |
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debug(cpu->cd.sparc.ccr & SPARC_CCR_Z? "Z" : "z"); |
238 |
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debug(cpu->cd.sparc.ccr & SPARC_CCR_V? "V" : "v"); |
239 |
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debug(cpu->cd.sparc.ccr & SPARC_CCR_C? "C" : "c"); |
240 |
|
if (!bits32) { |
241 |
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debug(" xcc = "); |
242 |
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debug((cpu->cd.sparc.ccr >> SPARC_CCR_XCC_SHIFT) |
243 |
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& SPARC_CCR_N? "N" : "n"); |
244 |
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debug((cpu->cd.sparc.ccr >> SPARC_CCR_XCC_SHIFT) |
245 |
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& SPARC_CCR_Z? "Z" : "z"); |
246 |
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debug((cpu->cd.sparc.ccr >> SPARC_CCR_XCC_SHIFT) |
247 |
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& SPARC_CCR_V? "V" : "v"); |
248 |
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debug((cpu->cd.sparc.ccr >> SPARC_CCR_XCC_SHIFT) |
249 |
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& SPARC_CCR_C? "C" : "c"); |
250 |
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} |
251 |
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debug("\n"); |
252 |
|
|
253 |
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if (bits32) |
254 |
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debug("cpu%i: psr = 0x%08"PRIx32"\n", |
255 |
|
x, (uint32_t) cpu->cd.sparc.psr); |
256 |
|
else |
257 |
|
debug("cpu%i: pstate = 0x%016"PRIx64"\n", |
258 |
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x, (uint64_t) cpu->cd.sparc.pstate); |
259 |
|
|
260 |
if (bits32) { |
if (bits32) { |
261 |
for (i=0; i<N_SPARC_REG; i++) { |
for (i=0; i<N_SPARC_REG; i++) { |
262 |
if ((i & 3) == 0) |
if ((i & 3) == 0) |
263 |
debug("cpu%i: ", x); |
debug("cpu%i: ", x); |
264 |
/* Skip the zero register: */ |
/* Skip the zero register: */ |
265 |
if (i==0) { |
if (i == SPARC_ZEROREG) { |
266 |
debug(" "); |
debug(" "); |
267 |
continue; |
continue; |
268 |
} |
} |
278 |
int r = ((i >> 1) & 15) | ((i&1) << 4); |
int r = ((i >> 1) & 15) | ((i&1) << 4); |
279 |
if ((i & 1) == 0) |
if ((i & 1) == 0) |
280 |
debug("cpu%i: ", x); |
debug("cpu%i: ", x); |
281 |
|
|
282 |
/* Skip the zero register: */ |
/* Skip the zero register: */ |
283 |
if (r==0) { |
if (i == SPARC_ZEROREG) { |
284 |
debug(" "); |
debug(" "); |
285 |
continue; |
continue; |
286 |
} |
} |
287 |
|
|
288 |
debug("%s = ", sparc_regnames[r]); |
debug("%s = ", sparc_regnames[r]); |
289 |
debug("0x%016llx", (long long) |
debug("0x%016"PRIx64, (uint64_t) |
290 |
cpu->cd.sparc.r[r]); |
cpu->cd.sparc.r[r]); |
291 |
|
|
292 |
if ((i & 1) < 1) |
if ((i & 1) < 1) |
293 |
debug(" "); |
debug(" "); |
294 |
else |
else |
296 |
} |
} |
297 |
} |
} |
298 |
} |
} |
|
} |
|
299 |
|
|
300 |
|
if (coprocs & 1) { |
301 |
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int sum; |
302 |
|
|
303 |
/* |
debug("cpu%i: cwp = 0x%02x\n", x, cpu->cd.sparc.cwp); |
304 |
* sparc_cpu_register_match(): |
debug("cpu%i: cansave = 0x%02x\n", x, cpu->cd.sparc.cansave); |
305 |
*/ |
debug("cpu%i: canrestore = 0x%02x\n", x, |
306 |
void sparc_cpu_register_match(struct machine *m, char *name, |
cpu->cd.sparc.canrestore); |
307 |
int writeflag, uint64_t *valuep, int *match_register) |
debug("cpu%i: otherwin = 0x%02x\n", x, |
308 |
{ |
cpu->cd.sparc.otherwin); |
309 |
int cpunr = 0; |
debug("cpu%i: cleanwin = 0x%02x\n", x, |
310 |
|
cpu->cd.sparc.cleanwin); |
311 |
|
|
312 |
|
sum = cpu->cd.sparc.cansave + cpu->cd.sparc.canrestore + |
313 |
|
cpu->cd.sparc.otherwin; |
314 |
|
debug("cpu%i: cansave + canrestore + otherwin = %i + %i + %i" |
315 |
|
" = %i", x, cpu->cd.sparc.cansave, cpu->cd.sparc.canrestore, |
316 |
|
cpu->cd.sparc.otherwin, sum); |
317 |
|
if (sum == cpu->cd.sparc.cpu_type.nwindows - 2) |
318 |
|
debug(" (consistent)\n"); |
319 |
|
else |
320 |
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debug(" (INCONSISTENT!)\n"); |
321 |
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|
322 |
|
debug("cpu%i: wstate: other = %i, normal = %i\n", |
323 |
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x, (cpu->cd.sparc.wstate & SPARC_WSTATE_OTHER_MASK) |
324 |
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>> SPARC_WSTATE_OTHER_SHIFT, cpu->cd.sparc.wstate & |
325 |
|
SPARC_WSTATE_NORMAL_MASK); |
326 |
|
|
327 |
|
debug("cpu%i: asi = 0x%02x\n", x, cpu->cd.sparc.asi); |
328 |
|
debug("cpu%i: tl = 0x%02x\n", x, cpu->cd.sparc.tl); |
329 |
|
debug("cpu%i: pil = 0x%02x\n", x, cpu->cd.sparc.pil); |
330 |
|
|
331 |
|
for (i=0; i<MAXTL; i++) { |
332 |
|
debug("cpu%i: tpc[%i] = 0x", x, i); |
333 |
|
if (bits32) |
334 |
|
debug("%08"PRIx32"\n", |
335 |
|
(uint32_t) cpu->cd.sparc.tpc[i]); |
336 |
|
else |
337 |
|
debug("%016"PRIx64"\n", |
338 |
|
(uint64_t) cpu->cd.sparc.tpc[i]); |
339 |
|
|
340 |
|
debug("cpu%i: tnpc[%i] = 0x", x, i); |
341 |
|
if (bits32) |
342 |
|
debug("%08"PRIx32"\n", |
343 |
|
(uint32_t) cpu->cd.sparc.tnpc[i]); |
344 |
|
else |
345 |
|
debug("%016"PRIx64"\n", |
346 |
|
(uint64_t) cpu->cd.sparc.tnpc[i]); |
347 |
|
|
348 |
/* CPU number: */ |
debug("cpu%i: tstate[%i] = 0x", x, i); |
349 |
|
if (bits32) |
350 |
|
debug("%08"PRIx32"\n", |
351 |
|
(uint32_t) cpu->cd.sparc.tstate[i]); |
352 |
|
else |
353 |
|
debug("%016"PRIx64"\n", |
354 |
|
(uint64_t) cpu->cd.sparc.tstate[i]); |
355 |
|
|
356 |
/* TODO */ |
debug("cpu%i: ttype[%i] = 0x"PRIx32"\n", |
357 |
|
x, i, cpu->cd.sparc.ttype[i]); |
358 |
|
} |
359 |
|
|
360 |
/* Register name: */ |
debug("cpu%i: tba = 0x", x); |
361 |
if (strcasecmp(name, "pc") == 0) { |
if (bits32) |
362 |
if (writeflag) { |
debug("%08"PRIx32"\n", (uint32_t) cpu->cd.sparc.tba); |
363 |
m->cpus[cpunr]->pc = *valuep; |
else |
364 |
} else |
debug("%016"PRIx64"\n", (uint64_t) cpu->cd.sparc.tba); |
|
*valuep = m->cpus[cpunr]->pc; |
|
|
*match_register = 1; |
|
365 |
} |
} |
366 |
} |
} |
367 |
|
|
368 |
|
|
369 |
/* |
/* |
370 |
* sparc_cpu_interrupt(): |
* sparc_cpu_tlbdump(): |
371 |
|
* |
372 |
|
* Called from the debugger to dump the TLB in a readable format. |
373 |
|
* x is the cpu number to dump, or -1 to dump all CPUs. |
374 |
|
* |
375 |
|
* If rawflag is nonzero, then the TLB contents isn't formated nicely, |
376 |
|
* just dumped. |
377 |
*/ |
*/ |
378 |
int sparc_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr) |
void sparc_cpu_tlbdump(struct machine *m, int x, int rawflag) |
379 |
{ |
{ |
|
fatal("sparc_cpu_interrupt(): TODO\n"); |
|
|
return 0; |
|
380 |
} |
} |
381 |
|
|
382 |
|
|
383 |
/* |
/* |
384 |
* sparc_cpu_interrupt_ack(): |
* sparc_cpu_instruction_has_delayslot(): |
385 |
|
* |
386 |
|
* Return 1 if an opcode is a branch, 0 otherwise. |
387 |
*/ |
*/ |
388 |
int sparc_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr) |
int sparc_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib) |
389 |
{ |
{ |
390 |
/* fatal("sparc_cpu_interrupt_ack(): TODO\n"); */ |
uint32_t iword = *((uint32_t *)&ib[0]); |
391 |
|
int hi2, op2; |
392 |
|
|
393 |
|
iword = BE32_TO_HOST(iword); |
394 |
|
|
395 |
|
hi2 = iword >> 30; |
396 |
|
op2 = (hi2 == 0)? ((iword >> 22) & 7) : ((iword >> 19) & 0x3f); |
397 |
|
|
398 |
|
switch (hi2) { |
399 |
|
case 0: /* conditional branch */ |
400 |
|
switch (op2) { |
401 |
|
case 1: |
402 |
|
case 2: |
403 |
|
case 3: return 1; |
404 |
|
} |
405 |
|
break; |
406 |
|
case 1: /* call */ |
407 |
|
return 1; |
408 |
|
case 2: /* misc alu instructions */ |
409 |
|
switch (op2) { |
410 |
|
case 56:/* jump and link */ |
411 |
|
return 1; |
412 |
|
case 57:/* return */ |
413 |
|
return 1; |
414 |
|
} |
415 |
|
break; |
416 |
|
} |
417 |
|
|
418 |
return 0; |
return 0; |
419 |
} |
} |
420 |
|
|
432 |
* cpu->pc for relative addresses. |
* cpu->pc for relative addresses. |
433 |
*/ |
*/ |
434 |
int sparc_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr, |
int sparc_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr, |
435 |
int running, uint64_t dumpaddr, int bintrans) |
int running, uint64_t dumpaddr) |
436 |
{ |
{ |
437 |
uint64_t offset, tmp; |
uint64_t offset, tmp; |
438 |
uint32_t iword; |
uint32_t iword; |
439 |
int hi2, op2, rd, rs1, rs2, siconst, btype, tmps, no_rd = 0; |
int hi2, op2, rd, rs1, rs2, siconst, btype, tmps, no_rd = 0; |
440 |
int asi, no_rs1 = 0, no_rs2 = 0, jmpl = 0, shift_x = 0, cc, p; |
int asi, no_rs1 = 0, no_rs2 = 0, jmpl = 0, shift_x = 0, cc, p; |
441 |
char *symbol, *mnem; |
char *symbol, *mnem, *rd_name, *rs_name; |
442 |
|
|
443 |
if (running) |
if (running) |
444 |
dumpaddr = cpu->pc; |
dumpaddr = cpu->pc; |
452 |
debug("cpu%i: ", cpu->cpu_id); |
debug("cpu%i: ", cpu->cpu_id); |
453 |
|
|
454 |
if (cpu->is_32bit) |
if (cpu->is_32bit) |
455 |
debug("%08x", (int)dumpaddr); |
debug("%08"PRIx32, (uint32_t) dumpaddr); |
456 |
else |
else |
457 |
debug("%016llx", (long long)dumpaddr); |
debug("%016"PRIx64, (uint64_t) dumpaddr); |
458 |
|
|
459 |
iword = *(uint32_t *)&instr[0]; |
iword = *(uint32_t *)&instr[0]; |
460 |
iword = BE32_TO_HOST(iword); |
iword = BE32_TO_HOST(iword); |
461 |
|
|
462 |
debug(": %08x\t", iword); |
debug(": %08x", iword); |
463 |
|
|
464 |
|
if (running && cpu->delay_slot) |
465 |
|
debug(" (d)"); |
466 |
|
|
467 |
|
debug("\t"); |
468 |
|
|
469 |
|
|
470 |
/* |
/* |
471 |
* Decode the instruction: |
* Decode the instruction: |
526 |
} |
} |
527 |
tmp = (int64_t)(int32_t)tmps; |
tmp = (int64_t)(int32_t)tmps; |
528 |
tmp += dumpaddr; |
tmp += dumpaddr; |
529 |
debug("0x%llx", (long long)tmp); |
debug("0x%"PRIx64, (uint64_t) tmp); |
530 |
symbol = get_symbol_name(&cpu->machine-> |
symbol = get_symbol_name(&cpu->machine-> |
531 |
symbol_context, tmp, &offset); |
symbol_context, tmp, &offset); |
532 |
if (symbol != NULL) |
if (symbol != NULL) |
547 |
|
|
548 |
case 1: tmp = (int32_t)iword << 2; |
case 1: tmp = (int32_t)iword << 2; |
549 |
tmp += dumpaddr; |
tmp += dumpaddr; |
550 |
debug("call\t0x%llx", (long long)tmp); |
debug("call\t0x%"PRIx64, (uint64_t) tmp); |
551 |
symbol = get_symbol_name(&cpu->machine->symbol_context, |
symbol = get_symbol_name(&cpu->machine->symbol_context, |
552 |
tmp, &offset); |
tmp, &offset); |
553 |
if (symbol != NULL) |
if (symbol != NULL) |
555 |
break; |
break; |
556 |
|
|
557 |
case 2: mnem = sparc_alu_names[op2]; |
case 2: mnem = sparc_alu_names[op2]; |
558 |
|
rs_name = sparc_regnames[rs1]; |
559 |
|
rd_name = sparc_regnames[rd]; |
560 |
switch (op2) { |
switch (op2) { |
561 |
case 0: /* add */ |
case 0: /* add */ |
562 |
if (rd == rs1 && (iword & 0x3fff) == 0x2001) { |
if (rd == rs1 && (iword & 0x3fff) == 0x2001) { |
591 |
} else |
} else |
592 |
siconst &= 0x1f; |
siconst &= 0x1f; |
593 |
break; |
break; |
594 |
|
case 40:/* rd on pre-sparcv9, membar etc on sparcv9 */ |
595 |
|
no_rs2 = 1; |
596 |
|
rs_name = "UNIMPLEMENTED"; |
597 |
|
switch (rs1) { |
598 |
|
case 0: rs_name = "y"; break; |
599 |
|
case 2: rs_name = "ccr"; break; |
600 |
|
case 3: rs_name = "asi"; break; |
601 |
|
case 4: rs_name = "tick"; break; |
602 |
|
case 5: rs_name = "pc"; break; |
603 |
|
case 6: rs_name = "fprs"; break; |
604 |
|
case 15:/* membar etc. */ |
605 |
|
if ((iword >> 13) & 1) { |
606 |
|
no_rd = 1; |
607 |
|
mnem = "membar"; |
608 |
|
rs_name = "#TODO"; |
609 |
|
} |
610 |
|
break; |
611 |
|
case 23:rs_name = "tick_cmpr"; break; /* v9 ? */ |
612 |
|
} |
613 |
|
break; |
614 |
|
case 41:rs_name = "psr"; |
615 |
|
no_rs2 = 1; |
616 |
|
break; |
617 |
|
case 42:/* TODO: something with wim only, on sparc v8? */ |
618 |
|
rs_name = sparc_pregnames[rs1]; |
619 |
|
no_rs2 = 1; |
620 |
|
break; |
621 |
case 43:/* ? */ |
case 43:/* ? */ |
622 |
|
/* TODO: pre-sparcv9: rd, rs_name = "tbr"; */ |
623 |
if (iword == 0x81580000) { |
if (iword == 0x81580000) { |
624 |
mnem = "flushw"; |
mnem = "flushw"; |
625 |
no_rs1 = no_rs2 = no_rd = 1; |
no_rs1 = no_rs2 = no_rd = 1; |
626 |
} |
} |
627 |
break; |
break; |
628 |
|
case 48:/* wr* (SPARCv8) */ |
629 |
|
mnem = "wr"; |
630 |
|
if (rs1 == SPARC_ZEROREG) |
631 |
|
no_rs1 = 1; |
632 |
|
switch (rd) { |
633 |
|
case 0: rd_name = "y"; break; |
634 |
|
case 2: rd_name = "ccr"; break; |
635 |
|
case 3: rd_name = "asi"; break; |
636 |
|
case 6: rd_name = "fprs"; break; |
637 |
|
case 23:rd_name = "tick_cmpr"; break; /* v9 ? */ |
638 |
|
default:rd_name = "UNIMPLEMENTED"; |
639 |
|
} |
640 |
|
break; |
641 |
case 49:/* ? */ |
case 49:/* ? */ |
642 |
if (iword == 0x83880000) { |
if (iword == 0x83880000) { |
643 |
mnem = "restored"; |
mnem = "restored"; |
644 |
no_rs1 = no_rs2 = no_rd = 1; |
no_rs1 = no_rs2 = no_rd = 1; |
645 |
} |
} |
646 |
break; |
break; |
647 |
|
case 50:/* wrpr */ |
648 |
|
rd_name = sparc_pregnames[rd]; |
649 |
|
if (rs1 == SPARC_ZEROREG) |
650 |
|
no_rs1 = 1; |
651 |
|
break; |
652 |
case 56:/* jmpl */ |
case 56:/* jmpl */ |
653 |
jmpl = 1; |
jmpl = 1; |
654 |
if (iword == 0x81c7e008) { |
if (iword == 0x81c7e008) { |
675 |
debug("x"); |
debug("x"); |
676 |
debug("\t"); |
debug("\t"); |
677 |
if (!no_rs1) |
if (!no_rs1) |
678 |
debug("%%%s", sparc_regnames[rs1]); |
debug("%%%s", rs_name); |
679 |
if (!no_rs1 && !no_rs2) { |
if (!no_rs1 && !no_rs2) { |
680 |
if (jmpl) |
if (jmpl) |
681 |
debug("+"); |
debug("+"); |
686 |
if ((iword >> 13) & 1) { |
if ((iword >> 13) & 1) { |
687 |
if (siconst >= -9 && siconst <= 9) |
if (siconst >= -9 && siconst <= 9) |
688 |
debug("%i", siconst); |
debug("%i", siconst); |
689 |
|
else if (siconst < 0 && (op2 == 0 || |
690 |
|
op2 == 4 || op2 == 20 || op2 == 60)) |
691 |
|
debug("-0x%x", -siconst); |
692 |
else |
else |
693 |
debug("0x%x", siconst); |
debug("0x%x", siconst); |
694 |
} else { |
} else { |
698 |
if ((!no_rs1 || !no_rs2) && !no_rd) |
if ((!no_rs1 || !no_rs2) && !no_rd) |
699 |
debug(","); |
debug(","); |
700 |
if (!no_rd) |
if (!no_rd) |
701 |
debug("%%%s", sparc_regnames[rd]); |
debug("%%%s", rd_name); |
702 |
break; |
break; |
703 |
|
|
704 |
case 3: debug("%s\t", sparc_loadstore_names[op2]); |
case 3: mnem = sparc_loadstore_names[op2]; |
705 |
|
switch (op2) { |
706 |
|
case 0: /* 'lduw' was called only 'ld' in pre-v9 */ |
707 |
|
if (cpu->cd.sparc.cpu_type.v < 9) |
708 |
|
mnem = "ld"; |
709 |
|
break; |
710 |
|
} |
711 |
|
debug("%s\t", mnem); |
712 |
if (op2 & 4) |
if (op2 & 4) |
713 |
debug("%%%s,", sparc_regnames[rd]); |
debug("%%%s,", sparc_regnames[rd]); |
714 |
debug("[%%%s", sparc_regnames[rs1]); |
debug("[%%%s", sparc_regnames[rs1]); |
722 |
debug("+%%%s", sparc_regnames[rs2]); |
debug("+%%%s", sparc_regnames[rs2]); |
723 |
} |
} |
724 |
debug("]"); |
debug("]"); |
725 |
if (asi != 0) |
if ((op2 & 0x30) == 0x10) |
726 |
debug("(%i)", asi); |
debug("(%i)", asi); |
727 |
if (!(op2 & 4)) |
if (!(op2 & 4)) |
728 |
debug(",%%%s", sparc_regnames[rd]); |
debug(",%%%s", sparc_regnames[rd]); |
734 |
} |
} |
735 |
|
|
736 |
|
|
737 |
|
/* |
738 |
|
* sparc_update_pstate(): |
739 |
|
* |
740 |
|
* Update the pstate register (64-bit sparcs). |
741 |
|
*/ |
742 |
|
static void sparc_update_pstate(struct cpu *cpu, uint64_t new_pstate) |
743 |
|
{ |
744 |
|
/* uint64_t old_pstate = cpu->cd.sparc.pstate; */ |
745 |
|
|
746 |
|
/* TODO: Check individual bits. */ |
747 |
|
|
748 |
|
cpu->cd.sparc.pstate = new_pstate; |
749 |
|
} |
750 |
|
|
751 |
|
|
752 |
#include "tmp_sparc_tail.c" |
#include "tmp_sparc_tail.c" |
753 |
|
|