/[gxemul]/trunk/src/cpus/cpu_sh_instr.c
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Contents of /trunk/src/cpus/cpu_sh_instr.c

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Revision 30 - (show annotations)
Mon Oct 8 16:20:40 2007 UTC (13 years, 3 months ago) by dpavlin
File MIME type: text/plain
File size: 8769 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1325 2006/08/15 15:38:37 debug Exp $
20060723	More Transputer instructions (pfix, nfix, opr, mint, ldl, ldlp,
		eqc, rev, ajw, stl, stlf, sthf, sub, ldnl, ldnlp, ldpi, move,
		wcnt, add, bcnt).
		Adding more SPARC instructions (andcc, addcc, bl, rdpr).
		Progress on the igsfb framebuffer used by NetBSD/netwinder.
		Enabling 8-bit fills in dev_fb.
		NetBSD/netwinder 3.0.1 can now run from a disk image :-)
20060724	Cleanup/performance fix for 64-bit virtual translation table
		updates (by removing the "timestamp" stuff). A full NetBSD/pmax
		3.0.1 install for R4400 has dropped from 667 seconds to 584 :)
		Fixing the igsfb "almost vga" color (it is 24-bit, not 18-bit).
		Adding some MIPS instruction combinations (3*lw, and 3*addu).
		The 8048 keyboard now turns off interrupt enable between the
		KBR_ACK and the KBR_RSTDONE, to work better with Linux 2.6.
		Not causing PPC DEC interrupts if PPC_NO_DEC is set for a
		specific CPU; NetBSD/bebox gets slightly further than before.
		Adding some more SPARC instructions: branches, udiv.
20060725	Refreshing dev_pckbc.c a little.
		Cleanups for the SH emulation mode, and adding the first
		"compact" (16-bit) instructions: various simple movs, nop,
		shll, stc, or, ldc.
20060726	Adding dummy "pcn" (AMD PCnet NIC) PCI glue.
20060727	Various cleanups; removing stuff from cpu.h, such as
		running_translated (not really meaningful anymore), and
		page flags (breaking into the debugger clears all translations
		anyway).
		Minor MIPS instruction combination updates.
20060807	Expanding the 3*sw and 3*lw MIPS instruction combinations to
		work with 2* and 4* too, resulting in a minor performance gain.
		Implementing a usleep hack for the RM52xx/MIPS32/MIPS64 "wait"
		instruction (when emulating 1 cpu).
20060808	Experimenting with some more MIPS instruction combinations.
		Implementing support for showing a (hardcoded 12x22) text
		cursor in igsfb.
20060809	Simplifying the NetBSD/evbmips (Malta) install instructions
		somewhat (by using a NetBSD/pmax ramdisk install kernel).
20060812	Experimenting more with the MIPS 'wait' instruction.
		PCI configuration register writes can now be handled, which
		allow PCI IDE controllers to work with NetBSD/Malta 3.0.1 and
		NetBSD/cobalt 3.0.1. (Previously only NetBSD 2.1 worked.)
20060813	Updating dev_gt.c based on numbers from Alec Voropay, to enable
		Linux 2.6 to use PCI on Malta.
		Continuing on Algor interrupt stuff.
20060814	Adding support for routing ISA interrupts to two different
		interrupts, making it possible to run NetBSD/algor :-)
20060814-15	Testing for the release.

==============  RELEASE 0.4.2  ==============


1 /*
2 * Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: cpu_sh_instr.c,v 1.9 2006/07/25 21:29:04 debug Exp $
29 *
30 * SH instructions.
31 *
32 * Individual functions should keep track of cpu->n_translated_instrs.
33 * (If no instruction was executed, then it should be decreased. If, say, 4
34 * instructions were combined into one function and executed, then it should
35 * be increased by 3.)
36 */
37
38
39 /*
40 * nop: Nothing
41 */
42 X(nop)
43 {
44 }
45
46
47 /*
48 * mov_rm_rn: Copy rm into rn
49 *
50 * arg[0] = ptr to rm
51 * arg[1] = ptr to rn
52 */
53 X(mov_rm_rn)
54 {
55 reg(ic->arg[1]) = reg(ic->arg[0]);
56 }
57
58
59 /*
60 * mov_imm_rn: Set rn to an signed 8-bit value
61 *
62 * arg[0] = int8_t imm, extended to at least int32_t
63 * arg[1] = ptr to rn
64 */
65 X(mov_imm_rn)
66 {
67 reg(ic->arg[1]) = (int32_t)ic->arg[0];
68 }
69
70
71 /*
72 * mov_l_disp_pc_rn: Set rn to an immediate value relative to the current pc
73 *
74 * arg[0] = offset from beginning of the current pc's page
75 * arg[1] = ptr to rn
76 */
77 X(mov_l_disp_pc_rn)
78 {
79 reg(ic->arg[1]) = ic->arg[0] + (cpu->pc &
80 ~((SH_IC_ENTRIES_PER_PAGE-1) << SH_INSTR_ALIGNMENT_SHIFT));
81 }
82
83
84 /*
85 * or_rm_rn: rn = rn or rm
86 *
87 * arg[0] = ptr to rm
88 * arg[1] = ptr to rn
89 */
90 X(or_rm_rn)
91 {
92 reg(ic->arg[1]) |= reg(ic->arg[0]);
93 }
94
95
96 /*
97 * shll_rn: Shift rn left by 1
98 *
99 * arg[0] = ptr to rn
100 */
101 X(shll_rn)
102 {
103 uint32_t rn = reg(ic->arg[0]);
104 if (rn >> 31)
105 cpu->cd.sh.sr |= SH_SR_T;
106 else
107 cpu->cd.sh.sr &= ~SH_SR_T;
108 reg(ic->arg[0]) = rn << 1;
109 }
110
111
112 /*
113 * stc_sr_rn: Store SR into Rn
114 *
115 * arg[0] = ptr to rn
116 */
117 X(stc_sr_rn)
118 {
119 if (!(cpu->cd.sh.sr & SH_SR_MD)) {
120 fatal("TODO: Throw RESINST exception, if MD = 0.\n");
121 exit(1);
122 }
123
124 reg(ic->arg[0]) = cpu->cd.sh.sr;
125 }
126
127
128 /*
129 * ldc_rm_sr: Store Rm into SR
130 *
131 * arg[0] = ptr to rm
132 */
133 X(ldc_rm_sr)
134 {
135 if (!(cpu->cd.sh.sr & SH_SR_MD)) {
136 fatal("TODO: Throw RESINST exception, if MD = 0.\n");
137 exit(1);
138 }
139
140 sh_update_sr(cpu, reg(ic->arg[0]));
141 }
142
143
144 /*****************************************************************************/
145
146
147 X(end_of_page)
148 {
149 /* Update the PC: (offset 0, but on the next page) */
150 cpu->pc &= ~((SH_IC_ENTRIES_PER_PAGE-1) <<
151 SH_INSTR_ALIGNMENT_SHIFT);
152 cpu->pc += (SH_IC_ENTRIES_PER_PAGE <<
153 SH_INSTR_ALIGNMENT_SHIFT);
154
155 /* Find the new physical page and update the translation pointers: */
156 DYNTRANS_PC_TO_POINTERS(cpu);
157
158 /* end_of_page doesn't count as an executed instruction: */
159 cpu->n_translated_instrs --;
160 }
161
162
163 /*****************************************************************************/
164
165
166 /*
167 * sh_instr_to_be_translated():
168 *
169 * Translate an instruction word into an sh_instr_call. ic is filled in with
170 * valid data for the translated instruction, or a "nothing" instruction if
171 * there was a translation failure. The newly translated instruction is then
172 * executed.
173 */
174 X(to_be_translated)
175 {
176 uint64_t addr, low_pc;
177 uint32_t iword;
178 unsigned char *page;
179 unsigned char ib[4];
180 int main_opcode, isize = cpu->cd.sh.compact? 2 : sizeof(ib);
181 int in_crosspage_delayslot = 0, r8, r4, lo4, lo8;
182 /* void (*samepage_function)(struct cpu *, struct sh_instr_call *); */
183
184 /* Figure out the (virtual) address of the instruction: */
185 low_pc = ((size_t)ic - (size_t)cpu->cd.sh.cur_ic_page)
186 / sizeof(struct sh_instr_call);
187
188 /* Special case for branch with delayslot on the next page: */
189 if (cpu->delay_slot == TO_BE_DELAYED && low_pc == 0) {
190 /* fatal("[ delay-slot translation across page "
191 "boundary ]\n"); */
192 in_crosspage_delayslot = 1;
193 }
194
195 addr = cpu->pc & ~((SH_IC_ENTRIES_PER_PAGE-1)
196 << SH_INSTR_ALIGNMENT_SHIFT);
197 addr += (low_pc << SH_INSTR_ALIGNMENT_SHIFT);
198 cpu->pc = (MODE_int_t)addr;
199 addr &= ~((1 << SH_INSTR_ALIGNMENT_SHIFT) - 1);
200
201 /* Read the instruction word from memory: */
202 #ifdef MODE32
203 page = cpu->cd.sh.host_load[(uint32_t)addr >> 12];
204 #else
205 {
206 const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
207 const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
208 const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
209 uint32_t x1 = (addr >> (64-DYNTRANS_L1N)) & mask1;
210 uint32_t x2 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
211 uint32_t x3 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N-
212 DYNTRANS_L3N)) & mask3;
213 struct DYNTRANS_L2_64_TABLE *l2 = cpu->cd.sh.l1_64[x1];
214 struct DYNTRANS_L3_64_TABLE *l3 = l2->l3[x2];
215 page = l3->host_load[x3];
216 }
217 #endif
218
219 if (page != NULL) {
220 /* fatal("TRANSLATION HIT!\n"); */
221 memcpy(ib, page + (addr & 0xfff), isize);
222 } else {
223 /* fatal("TRANSLATION MISS!\n"); */
224 if (!cpu->memory_rw(cpu, cpu->mem, addr, ib,
225 isize, MEM_READ, CACHE_INSTRUCTION)) {
226 fatal("to_be_translated(): read failed: TODO\n");
227 goto bad;
228 }
229 }
230
231 iword = *((uint32_t *)&ib[0]);
232
233 if (cpu->cd.sh.compact) {
234 if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
235 iword = LE16_TO_HOST(iword);
236 else
237 iword = BE16_TO_HOST(iword);
238 main_opcode = iword >> 12;
239 r8 = (iword >> 8) & 0xf;
240 r4 = (iword >> 4) & 0xf;
241 lo8 = iword & 0xff;
242 lo4 = iword & 0xf;
243 } else {
244 if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
245 iword = LE32_TO_HOST(iword);
246 else
247 iword = BE32_TO_HOST(iword);
248 main_opcode = -1; /* TODO */
249 fatal("SH5/SH64 isn't implemented yet. Sorry.\n");
250 goto bad;
251 }
252
253
254 #define DYNTRANS_TO_BE_TRANSLATED_HEAD
255 #include "cpu_dyntrans.c"
256 #undef DYNTRANS_TO_BE_TRANSLATED_HEAD
257
258
259 /*
260 * Translate the instruction:
261 */
262
263 switch (main_opcode) {
264
265 case 0x0:
266 switch (lo8) {
267 case 0x02: /* STC SR,Rn */
268 ic->f = instr(stc_sr_rn);
269 ic->arg[0] = (size_t)&cpu->cd.sh.r[r8]; /* n */
270 break;
271 case 0x09: /* NOP */
272 ic->f = instr(nop);
273 if (iword & 0x0f00) {
274 fatal("Unimplemented NOP variant?\n");
275 goto bad;
276 }
277 break;
278 default:fatal("Unimplemented opcode 0x%x,0x03%x\n",
279 main_opcode, iword & 0xfff);
280 goto bad;
281 }
282 break;
283
284 case 0x2:
285 switch (lo4) {
286 case 0xb: /* OR Rm,Rn */
287 ic->f = instr(or_rm_rn);
288 ic->arg[0] = (size_t)&cpu->cd.sh.r[r4]; /* m */
289 ic->arg[1] = (size_t)&cpu->cd.sh.r[r8]; /* n */
290 break;
291 default:fatal("Unimplemented opcode 0x%x,0x%x\n",
292 main_opcode, lo4);
293 goto bad;
294 }
295 break;
296
297 case 0x4:
298 switch (lo8) {
299 case 0x00: /* SHLL Rn */
300 ic->f = instr(shll_rn);
301 ic->arg[0] = (size_t)&cpu->cd.sh.r[r8]; /* n */
302 break;
303 case 0x0e: /* LDC Rm,SR */
304 ic->f = instr(ldc_rm_sr);
305 ic->arg[0] = (size_t)&cpu->cd.sh.r[r8]; /* m */
306 break;
307 default:fatal("Unimplemented opcode 0x%x,0x02%x\n",
308 main_opcode, lo8);
309 goto bad;
310 }
311 break;
312
313 case 0x6:
314 switch (lo4) {
315 case 0x3: /* MOV Rm,Rn */
316 ic->f = instr(mov_rm_rn);
317 ic->arg[0] = (size_t)&cpu->cd.sh.r[r4]; /* m */
318 ic->arg[1] = (size_t)&cpu->cd.sh.r[r8]; /* n */
319 break;
320 default:fatal("Unimplemented opcode 0x%x,0x%x\n",
321 main_opcode, lo4);
322 goto bad;
323 }
324 break;
325
326 case 0xd: /* MOV.L @(disp,PC),Rn */
327 ic->f = instr(mov_l_disp_pc_rn);
328 ic->arg[0] = lo8 * 4 + (addr & ((SH_IC_ENTRIES_PER_PAGE-1)
329 << SH_INSTR_ALIGNMENT_SHIFT) & ~3) + 4;
330 ic->arg[1] = (size_t)&cpu->cd.sh.r[r8]; /* n */
331 break;
332
333 case 0xe: /* MOV #imm,Rn */
334 ic->f = instr(mov_imm_rn);
335 ic->arg[0] = (int8_t)lo8;
336 ic->arg[1] = (size_t)&cpu->cd.sh.r[r8]; /* n */
337 break;
338
339 default:fatal("Unimplemented main opcode 0x%x\n", main_opcode);
340 goto bad;
341 }
342
343
344 #define DYNTRANS_TO_BE_TRANSLATED_TAIL
345 #include "cpu_dyntrans.c"
346 #undef DYNTRANS_TO_BE_TRANSLATED_TAIL
347 }
348

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