src/cpus/cpu_sh_instr.c

/*
 *  Copyright (C) 2005-2006  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *
 *
 *  $Id: cpu_sh_instr.c,v 1.9 2006/07/25 21:29:04 debug Exp $
 *
 *  SH instructions.
 *
 *  Individual functions should keep track of cpu->n_translated_instrs.
 *  (If no instruction was executed, then it should be decreased. If, say, 4
 *  instructions were combined into one function and executed, then it should
 *  be increased by 3.)
 */


/*
 *  nop: Nothing
 */
X(nop)
{
}


/*
 *  mov_rm_rn:  Copy rm into rn
 *
 *  arg[0] = ptr to rm
 *  arg[1] = ptr to rn
 */
X(mov_rm_rn)
{
        reg(ic->arg[1]) = reg(ic->arg[0]);
}


/*
 *  mov_imm_rn:  Set rn to an signed 8-bit value
 *
 *  arg[0] = int8_t imm, extended to at least int32_t
 *  arg[1] = ptr to rn
 */
X(mov_imm_rn)
{
        reg(ic->arg[1]) = (int32_t)ic->arg[0];
}


/*
 *  mov_l_disp_pc_rn:  Set rn to an immediate value relative to the current pc
 *
 *  arg[0] = offset from beginning of the current pc's page
 *  arg[1] = ptr to rn
 */
X(mov_l_disp_pc_rn)
{
        reg(ic->arg[1]) = ic->arg[0] + (cpu->pc &
            ~((SH_IC_ENTRIES_PER_PAGE-1) << SH_INSTR_ALIGNMENT_SHIFT));
}


/*
 *  or_rm_rn:  rn = rn or rm
 *
 *  arg[0] = ptr to rm
 *  arg[1] = ptr to rn
 */
X(or_rm_rn)
{
        reg(ic->arg[1]) |= reg(ic->arg[0]);
}


/*
 *  shll_rn: Shift rn left by 1
 *
 *  arg[0] = ptr to rn
 */
X(shll_rn)
{
        uint32_t rn = reg(ic->arg[0]);
        if (rn >> 31)
                cpu->cd.sh.sr |= SH_SR_T;
        else
                cpu->cd.sh.sr &= ~SH_SR_T;
        reg(ic->arg[0]) = rn << 1;
}


/*
 *  stc_sr_rn: Store SR into Rn
 *
 *  arg[0] = ptr to rn
 */
X(stc_sr_rn)
{
        if (!(cpu->cd.sh.sr & SH_SR_MD)) {
                fatal("TODO: Throw RESINST exception, if MD = 0.\n");
                exit(1);
        }

        reg(ic->arg[0]) = cpu->cd.sh.sr;
}


/*
 *  ldc_rm_sr: Store Rm into SR
 *
 *  arg[0] = ptr to rm
 */
X(ldc_rm_sr)
{
        if (!(cpu->cd.sh.sr & SH_SR_MD)) {
                fatal("TODO: Throw RESINST exception, if MD = 0.\n");
                exit(1);
        }

        sh_update_sr(cpu, reg(ic->arg[0]));
}


/*****************************************************************************/


X(end_of_page)
{
        /*  Update the PC:  (offset 0, but on the next page)  */
        cpu->pc &= ~((SH_IC_ENTRIES_PER_PAGE-1) <<
            SH_INSTR_ALIGNMENT_SHIFT);
        cpu->pc += (SH_IC_ENTRIES_PER_PAGE <<
            SH_INSTR_ALIGNMENT_SHIFT);

        /*  Find the new physical page and update the translation pointers:  */
        DYNTRANS_PC_TO_POINTERS(cpu);

        /*  end_of_page doesn't count as an executed instruction:  */
        cpu->n_translated_instrs --;
}


/*****************************************************************************/


/*
 *  sh_instr_to_be_translated():
 *
 *  Translate an instruction word into an sh_instr_call. ic is filled in with
 *  valid data for the translated instruction, or a "nothing" instruction if
 *  there was a translation failure. The newly translated instruction is then
 *  executed.
 */
X(to_be_translated)
{
        uint64_t addr, low_pc;
        uint32_t iword;
        unsigned char *page;
        unsigned char ib[4];
        int main_opcode, isize = cpu->cd.sh.compact? 2 : sizeof(ib);
        int in_crosspage_delayslot = 0, r8, r4, lo4, lo8;
        /*  void (*samepage_function)(struct cpu *, struct sh_instr_call *);  */

        /*  Figure out the (virtual) address of the instruction:  */
        low_pc = ((size_t)ic - (size_t)cpu->cd.sh.cur_ic_page)
            / sizeof(struct sh_instr_call);

        /*  Special case for branch with delayslot on the next page:  */
        if (cpu->delay_slot == TO_BE_DELAYED && low_pc == 0) {
                /*  fatal("[ delay-slot translation across page "
                    "boundary ]\n");  */
                in_crosspage_delayslot = 1;
        }

        addr = cpu->pc & ~((SH_IC_ENTRIES_PER_PAGE-1)
            << SH_INSTR_ALIGNMENT_SHIFT);
        addr += (low_pc << SH_INSTR_ALIGNMENT_SHIFT);
        cpu->pc = (MODE_int_t)addr;
        addr &= ~((1 << SH_INSTR_ALIGNMENT_SHIFT) - 1);

        /*  Read the instruction word from memory:  */
#ifdef MODE32
        page = cpu->cd.sh.host_load[(uint32_t)addr >> 12];
#else
        {
                const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
                const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
                const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
                uint32_t x1 = (addr >> (64-DYNTRANS_L1N)) & mask1;
                uint32_t x2 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
                uint32_t x3 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N-
                    DYNTRANS_L3N)) & mask3;
                struct DYNTRANS_L2_64_TABLE *l2 = cpu->cd.sh.l1_64[x1];
                struct DYNTRANS_L3_64_TABLE *l3 = l2->l3[x2];
                page = l3->host_load[x3];
        }
#endif

        if (page != NULL) {
                /*  fatal("TRANSLATION HIT!\n");  */
                memcpy(ib, page + (addr & 0xfff), isize);
        } else {
                /*  fatal("TRANSLATION MISS!\n");  */
                if (!cpu->memory_rw(cpu, cpu->mem, addr, ib,
                    isize, MEM_READ, CACHE_INSTRUCTION)) {
                        fatal("to_be_translated(): read failed: TODO\n");
                        goto bad;
                }
        }

        iword = *((uint32_t *)&ib[0]);

        if (cpu->cd.sh.compact) {
                if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
                        iword = LE16_TO_HOST(iword);
                else
                        iword = BE16_TO_HOST(iword);
                main_opcode = iword >> 12;
                r8 = (iword >> 8) & 0xf;
                r4 = (iword >> 4) & 0xf;
                lo8 = iword & 0xff;
                lo4 = iword & 0xf;
        } else {
                if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
                        iword = LE32_TO_HOST(iword);
                else
                        iword = BE32_TO_HOST(iword);
                main_opcode = -1;       /*  TODO  */
                fatal("SH5/SH64 isn't implemented yet. Sorry.\n");
                goto bad;
        }


#define DYNTRANS_TO_BE_TRANSLATED_HEAD
#include "cpu_dyntrans.c"
#undef  DYNTRANS_TO_BE_TRANSLATED_HEAD


        /*
         *  Translate the instruction:
         */

        switch (main_opcode) {

        case 0x0:
                switch (lo8) {
                case 0x02:      /*  STC SR,Rn  */
                        ic->f = instr(stc_sr_rn);
                        ic->arg[0] = (size_t)&cpu->cd.sh.r[r8]; /* n */
                        break;
                case 0x09:      /*  NOP  */
                        ic->f = instr(nop);
                        if (iword & 0x0f00) {
                                fatal("Unimplemented NOP variant?\n");
                                goto bad;
                        }
                        break;
                default:fatal("Unimplemented opcode 0x%x,0x03%x\n",
                            main_opcode, iword & 0xfff);
                        goto bad;
                }
                break;

        case 0x2:
                switch (lo4) {
                case 0xb:       /*  OR Rm,Rn  */
                        ic->f = instr(or_rm_rn);
                        ic->arg[0] = (size_t)&cpu->cd.sh.r[r4]; /* m */
                        ic->arg[1] = (size_t)&cpu->cd.sh.r[r8]; /* n */
                        break;
                default:fatal("Unimplemented opcode 0x%x,0x%x\n",
                            main_opcode, lo4);
                        goto bad;
                }
                break;

        case 0x4:
                switch (lo8) {
                case 0x00:      /*  SHLL Rn  */
                        ic->f = instr(shll_rn);
                        ic->arg[0] = (size_t)&cpu->cd.sh.r[r8]; /* n */
                        break;
                case 0x0e:      /*  LDC Rm,SR  */
                        ic->f = instr(ldc_rm_sr);
                        ic->arg[0] = (size_t)&cpu->cd.sh.r[r8]; /* m */
                        break;
                default:fatal("Unimplemented opcode 0x%x,0x02%x\n",
                            main_opcode, lo8);
                        goto bad;
                }
                break;

        case 0x6:
                switch (lo4) {
                case 0x3:       /*  MOV Rm,Rn  */
                        ic->f = instr(mov_rm_rn);
                        ic->arg[0] = (size_t)&cpu->cd.sh.r[r4]; /* m */
                        ic->arg[1] = (size_t)&cpu->cd.sh.r[r8]; /* n */
                        break;
                default:fatal("Unimplemented opcode 0x%x,0x%x\n",
                            main_opcode, lo4);
                        goto bad;
                }
                break;

        case 0xd:       /*  MOV.L @(disp,PC),Rn  */
                ic->f = instr(mov_l_disp_pc_rn);
                ic->arg[0] = lo8 * 4 + (addr & ((SH_IC_ENTRIES_PER_PAGE-1)
                    << SH_INSTR_ALIGNMENT_SHIFT) & ~3) + 4;
                ic->arg[1] = (size_t)&cpu->cd.sh.r[r8]; /* n */
                break;

        case 0xe:       /*  MOV #imm,Rn  */
                ic->f = instr(mov_imm_rn);
                ic->arg[0] = (int8_t)lo8;
                ic->arg[1] = (size_t)&cpu->cd.sh.r[r8]; /* n */
                break;

        default:fatal("Unimplemented main opcode 0x%x\n", main_opcode);
                goto bad;
        }


#define DYNTRANS_TO_BE_TRANSLATED_TAIL
#include "cpu_dyntrans.c" 
#undef  DYNTRANS_TO_BE_TRANSLATED_TAIL
}

1	dpavlin	14	/*
2	dpavlin	22	* Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
3	dpavlin	14	*
4			* Redistribution and use in source and binary forms, with or without
5			* modification, are permitted provided that the following conditions are met:
6			*
7			* 1. Redistributions of source code must retain the above copyright
8			* notice, this list of conditions and the following disclaimer.
9			* 2. Redistributions in binary form must reproduce the above copyright
10			* notice, this list of conditions and the following disclaimer in the
11			* documentation and/or other materials provided with the distribution.
12			* 3. The name of the author may not be used to endorse or promote products
13			* derived from this software without specific prior written permission.
14			*
15			* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16			* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17			* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18			* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19			* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20			* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21			* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22			* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23			* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24			* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25			* SUCH DAMAGE.
26			*
27			*
28	dpavlin	30	* $Id: cpu_sh_instr.c,v 1.9 2006/07/25 21:29:04 debug Exp $
29	dpavlin	14	*
30			* SH instructions.
31			*
32			* Individual functions should keep track of cpu->n_translated_instrs.
33			* (If no instruction was executed, then it should be decreased. If, say, 4
34			* instructions were combined into one function and executed, then it should
35			* be increased by 3.)
36			*/
37
38
39			/*
40	dpavlin	30	* nop: Nothing
41	dpavlin	14	*/
42			X(nop)
43			{
44			}
45
46
47	dpavlin	30	/*
48			* mov_rm_rn: Copy rm into rn
49			*
50			* arg[0] = ptr to rm
51			* arg[1] = ptr to rn
52			*/
53			X(mov_rm_rn)
54			{
55			reg(ic->arg[1]) = reg(ic->arg[0]);
56			}
57
58
59			/*
60			* mov_imm_rn: Set rn to an signed 8-bit value
61			*
62			* arg[0] = int8_t imm, extended to at least int32_t
63			* arg[1] = ptr to rn
64			*/
65			X(mov_imm_rn)
66			{
67			reg(ic->arg[1]) = (int32_t)ic->arg[0];
68			}
69
70
71			/*
72			* mov_l_disp_pc_rn: Set rn to an immediate value relative to the current pc
73			*
74			* arg[0] = offset from beginning of the current pc's page
75			* arg[1] = ptr to rn
76			*/
77			X(mov_l_disp_pc_rn)
78			{
79			reg(ic->arg[1]) = ic->arg[0] + (cpu->pc &
80			~((SH_IC_ENTRIES_PER_PAGE-1) << SH_INSTR_ALIGNMENT_SHIFT));
81			}
82
83
84			/*
85			* or_rm_rn: rn = rn or rm
86			*
87			* arg[0] = ptr to rm
88			* arg[1] = ptr to rn
89			*/
90			X(or_rm_rn)
91			{
92			reg(ic->arg[1]) \|= reg(ic->arg[0]);
93			}
94
95
96			/*
97			* shll_rn: Shift rn left by 1
98			*
99			* arg[0] = ptr to rn
100			*/
101			X(shll_rn)
102			{
103			uint32_t rn = reg(ic->arg[0]);
104			if (rn >> 31)
105			cpu->cd.sh.sr \|= SH_SR_T;
106			else
107			cpu->cd.sh.sr &= ~SH_SR_T;
108			reg(ic->arg[0]) = rn << 1;
109			}
110
111
112			/*
113			* stc_sr_rn: Store SR into Rn
114			*
115			* arg[0] = ptr to rn
116			*/
117			X(stc_sr_rn)
118			{
119			if (!(cpu->cd.sh.sr & SH_SR_MD)) {
120			fatal("TODO: Throw RESINST exception, if MD = 0.\n");
121			exit(1);
122			}
123
124			reg(ic->arg[0]) = cpu->cd.sh.sr;
125			}
126
127
128			/*
129			* ldc_rm_sr: Store Rm into SR
130			*
131			* arg[0] = ptr to rm
132			*/
133			X(ldc_rm_sr)
134			{
135			if (!(cpu->cd.sh.sr & SH_SR_MD)) {
136			fatal("TODO: Throw RESINST exception, if MD = 0.\n");
137			exit(1);
138			}
139
140			sh_update_sr(cpu, reg(ic->arg[0]));
141			}
142
143
144	dpavlin	14	/*****************************************************************************/
145
146
147			X(end_of_page)
148			{
149			/* Update the PC: (offset 0, but on the next page) */
150			cpu->pc &= ~((SH_IC_ENTRIES_PER_PAGE-1) <<
151			SH_INSTR_ALIGNMENT_SHIFT);
152			cpu->pc += (SH_IC_ENTRIES_PER_PAGE <<
153			SH_INSTR_ALIGNMENT_SHIFT);
154
155			/* Find the new physical page and update the translation pointers: */
156			DYNTRANS_PC_TO_POINTERS(cpu);
157
158			/* end_of_page doesn't count as an executed instruction: */
159			cpu->n_translated_instrs --;
160			}
161
162
163			/*****************************************************************************/
164
165
166			/*
167			* sh_instr_to_be_translated():
168			*
169			* Translate an instruction word into an sh_instr_call. ic is filled in with
170			* valid data for the translated instruction, or a "nothing" instruction if
171			* there was a translation failure. The newly translated instruction is then
172			* executed.
173			*/
174			X(to_be_translated)
175			{
176	dpavlin	20	uint64_t addr, low_pc;
177	dpavlin	14	uint32_t iword;
178			unsigned char *page;
179			unsigned char ib[4];
180	dpavlin	30	int main_opcode, isize = cpu->cd.sh.compact? 2 : sizeof(ib);
181			int in_crosspage_delayslot = 0, r8, r4, lo4, lo8;
182			/* void (samepage_function)(struct cpu , struct sh_instr_call ); /
183	dpavlin	14
184			/* Figure out the (virtual) address of the instruction: */
185	dpavlin	30	low_pc = ((size_t)ic - (size_t)cpu->cd.sh.cur_ic_page)
186			/ sizeof(struct sh_instr_call);
187
188			/* Special case for branch with delayslot on the next page: */
189			if (cpu->delay_slot == TO_BE_DELAYED && low_pc == 0) {
190			/* fatal("[ delay-slot translation across page "
191			"boundary ]\n"); */
192			in_crosspage_delayslot = 1;
193	dpavlin	14	}
194
195	dpavlin	30	addr = cpu->pc & ~((SH_IC_ENTRIES_PER_PAGE-1)
196			<< SH_INSTR_ALIGNMENT_SHIFT);
197			addr += (low_pc << SH_INSTR_ALIGNMENT_SHIFT);
198			cpu->pc = (MODE_int_t)addr;
199			addr &= ~((1 << SH_INSTR_ALIGNMENT_SHIFT) - 1);
200
201	dpavlin	14	/* Read the instruction word from memory: */
202	dpavlin	30	#ifdef MODE32
203			page = cpu->cd.sh.host_load[(uint32_t)addr >> 12];
204			#else
205			{
206			const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
207			const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
208			const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
209			uint32_t x1 = (addr >> (64-DYNTRANS_L1N)) & mask1;
210			uint32_t x2 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
211			uint32_t x3 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N-
212			DYNTRANS_L3N)) & mask3;
213			struct DYNTRANS_L2_64_TABLE *l2 = cpu->cd.sh.l1_64[x1];
214			struct DYNTRANS_L3_64_TABLE *l3 = l2->l3[x2];
215			page = l3->host_load[x3];
216			}
217			#endif
218	dpavlin	14
219			if (page != NULL) {
220			/* fatal("TRANSLATION HIT!\n"); */
221	dpavlin	30	memcpy(ib, page + (addr & 0xfff), isize);
222	dpavlin	14	} else {
223			/* fatal("TRANSLATION MISS!\n"); */
224			if (!cpu->memory_rw(cpu, cpu->mem, addr, ib,
225	dpavlin	30	isize, MEM_READ, CACHE_INSTRUCTION)) {
226			fatal("to_be_translated(): read failed: TODO\n");
227	dpavlin	14	goto bad;
228			}
229			}
230
231			iword = ((uint32_t )&ib[0]);
232
233	dpavlin	30	if (cpu->cd.sh.compact) {
234			if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
235			iword = LE16_TO_HOST(iword);
236			else
237			iword = BE16_TO_HOST(iword);
238			main_opcode = iword >> 12;
239			r8 = (iword >> 8) & 0xf;
240			r4 = (iword >> 4) & 0xf;
241			lo8 = iword & 0xff;
242			lo4 = iword & 0xf;
243			} else {
244			if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
245			iword = LE32_TO_HOST(iword);
246			else
247			iword = BE32_TO_HOST(iword);
248			main_opcode = -1; /* TODO */
249			fatal("SH5/SH64 isn't implemented yet. Sorry.\n");
250			goto bad;
251			}
252	dpavlin	14
253
254			#define DYNTRANS_TO_BE_TRANSLATED_HEAD
255			#include "cpu_dyntrans.c"
256			#undef DYNTRANS_TO_BE_TRANSLATED_HEAD
257
258
259			/*
260			* Translate the instruction:
261			*/
262
263			switch (main_opcode) {
264
265	dpavlin	30	case 0x0:
266			switch (lo8) {
267			case 0x02: /* STC SR,Rn */
268			ic->f = instr(stc_sr_rn);
269			ic->arg[0] = (size_t)&cpu->cd.sh.r[r8]; /* n */
270			break;
271			case 0x09: /* NOP */
272			ic->f = instr(nop);
273			if (iword & 0x0f00) {
274			fatal("Unimplemented NOP variant?\n");
275			goto bad;
276			}
277			break;
278			default:fatal("Unimplemented opcode 0x%x,0x03%x\n",
279			main_opcode, iword & 0xfff);
280			goto bad;
281			}
282			break;
283
284			case 0x2:
285			switch (lo4) {
286			case 0xb: /* OR Rm,Rn */
287			ic->f = instr(or_rm_rn);
288			ic->arg[0] = (size_t)&cpu->cd.sh.r[r4]; /* m */
289			ic->arg[1] = (size_t)&cpu->cd.sh.r[r8]; /* n */
290			break;
291			default:fatal("Unimplemented opcode 0x%x,0x%x\n",
292			main_opcode, lo4);
293			goto bad;
294			}
295			break;
296
297			case 0x4:
298			switch (lo8) {
299			case 0x00: /* SHLL Rn */
300			ic->f = instr(shll_rn);
301			ic->arg[0] = (size_t)&cpu->cd.sh.r[r8]; /* n */
302			break;
303			case 0x0e: /* LDC Rm,SR */
304			ic->f = instr(ldc_rm_sr);
305			ic->arg[0] = (size_t)&cpu->cd.sh.r[r8]; /* m */
306			break;
307			default:fatal("Unimplemented opcode 0x%x,0x02%x\n",
308			main_opcode, lo8);
309			goto bad;
310			}
311			break;
312
313			case 0x6:
314			switch (lo4) {
315			case 0x3: /* MOV Rm,Rn */
316			ic->f = instr(mov_rm_rn);
317			ic->arg[0] = (size_t)&cpu->cd.sh.r[r4]; /* m */
318			ic->arg[1] = (size_t)&cpu->cd.sh.r[r8]; /* n */
319			break;
320			default:fatal("Unimplemented opcode 0x%x,0x%x\n",
321			main_opcode, lo4);
322			goto bad;
323			}
324			break;
325
326			case 0xd: /* MOV.L @(disp,PC),Rn */
327			ic->f = instr(mov_l_disp_pc_rn);
328			ic->arg[0] = lo8 * 4 + (addr & ((SH_IC_ENTRIES_PER_PAGE-1)
329			<< SH_INSTR_ALIGNMENT_SHIFT) & ~3) + 4;
330			ic->arg[1] = (size_t)&cpu->cd.sh.r[r8]; /* n */
331			break;
332
333			case 0xe: /* MOV #imm,Rn */
334			ic->f = instr(mov_imm_rn);
335			ic->arg[0] = (int8_t)lo8;
336			ic->arg[1] = (size_t)&cpu->cd.sh.r[r8]; /* n */
337			break;
338
339			default:fatal("Unimplemented main opcode 0x%x\n", main_opcode);
340			goto bad;
341	dpavlin	14	}
342
343	dpavlin	30
344	dpavlin	14	#define DYNTRANS_TO_BE_TRANSLATED_TAIL
345			#include "cpu_dyntrans.c"
346			#undef DYNTRANS_TO_BE_TRANSLATED_TAIL
347			}
348