/[gxemul]/trunk/src/cpus/cpu_sh.c
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Contents of /trunk/src/cpus/cpu_sh.c

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Revision 22 - (show annotations)
Mon Oct 8 16:19:37 2007 UTC (13 years, 1 month ago) by dpavlin
File MIME type: text/plain
File size: 15460 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1121 2006/02/18 21:03:08 debug Exp $
20051126	Cobalt and PReP now work with the 21143 NIC.
		Continuing on Alpha dyntrans things.
		Fixing some more left-shift-by-24 to unsigned.
20051127	Working on OpenFirmware emulation; major cleanup/redesign.
		Progress on MacPPC emulation: NetBSD detects two CPUs (when
		running with -n 2), framebuffer output (for text) works.
		Adding quick-hack Bandit PCI controller and "gc" interrupt
		controller for MacPPC.
20051128	Changing from a Bandit to a Uni-North controller for macppc.
		Continuing on OpenFirmware and MacPPC emulation in general
		(obio controller, and wdc attached to the obio seems to work).
20051129	More work on MacPPC emulation (adding a dummy ADB controller).
		Continuing the PCI bus cleanup (endianness and tag composition)
		and rewriting all PCI controllers' access functions.
20051130	Various minor PPC dyntrans optimizations.
		Manually inlining some parts of the framebuffer redraw routine.
		Slowly beginning the conversion of the old MIPS emulation into
		dyntrans (but this will take quite some time to get right).
		Generalizing quick_pc_to_pointers.
20051201	Documentation update (David Muse has made available a kernel
		which simplifies Debian/DECstation installation).
		Continuing on the ADB bus controller.
20051202	Beginning a rewrite of the Zilog serial controller (dev_zs).
20051203	Continuing on the zs rewrite (now called dev_z8530); conversion
		to devinit style.
		Reworking some of the input-only vs output-only vs input-output
		details of src/console.c, better warning messages, and adding
		a debug dump.
		Removing the concept of "device state"; it wasn't really used.
		Changing some debug output (-vv should now be used to show all
		details about devices and busses; not shown during normal
		startup anymore).
		Beginning on some SPARC instruction disassembly support.
20051204	Minor PPC updates (WALNUT skeleton stuff).
		Continuing on the MIPS dyntrans rewrite.
		More progress on the ADB controller (a keyboard is "detected"
		by NetBSD and OpenBSD).
		Downgrading OpenBSD/arc as a guest OS from "working" to
		"almost working" in the documentation.
		Progress on Algor emulation ("v3" PCI controller).
20051205	Minor updates.
20051207	Sorting devices according to address; this reduces complexity
		of device lookups from O(n) to O(log n) in memory_rw (but no
		real performance increase (yet) in experiments).
20051210	Beginning the work on native dyntrans backends (by making a
		simple skeleton; so far only for Alpha hosts).
20051211	Some very minor SPARC updates.
20051215	Fixing a bug in the MIPS mul (note: not mult) instruction,
		so it also works with non-64-bit emulation. (Thanks to Alec
		Voropay for noticing the problem.)
20051216	More work on the fake/empty/simple/skeleton/whatever backend;
		performance doesn't increase, so this isn't really worth it,
		but it was probably worth it to prepare for a real backend
		later.
20051219	More instr call statistics gathering and analysis stuff.
20051220	Another fix for MIPS 'mul'. Also converting mul and {d,}cl{o,z}
		to dyntrans.
		memory_ppc.c syntax error fix (noticed by Peter Valchev).
		Beginning to move out machines from src/machine.c into
		individual files in src/machines (in a way similar to the
		autodev system for devices).
20051222	Updating the documentation regarding NetBSD/pmax 3.0.
20051223	- " - NetBSD/cats 3.0.
20051225	- " - NetBSD/hpcmips 3.0.
20051226	Continuing on the machine registry redesign.
		Adding support for ARM rrx (33-bit rotate).
		Fixing some signed/unsigned issues (exposed by gcc -W).
20051227	Fixing the bug which prevented a NetBSD/prep 3.0 install kernel
		from starting (triggered when an mtmsr was the last instruction
		on a page). Unfortunately not enough to get the kernel to run
		as well as the 2.1 kernels did.
20051230	Some dyntrans refactoring.
20051231	Continuing on the machine registry redesign.
20060101-10	Continuing... moving more machines. Moving MD interrupt stuff
		from machine.c into a new src/machines/interrupts.c.
20060114	Adding various mvmeppc machine skeletons.
20060115	Continuing on mvme* stuff. NetBSD/mvmeppc prints boot messages
		(for MVME1600) and reaches the root device prompt, but no
		specific hardware devices are emulated yet.
20060116	Minor updates to the mvme1600 emulation mode; the Eagle PCI bus
		seems to work without much modification, and a 21143 can be
		detected, interrupts might work (but untested so far).
		Adding a fake MK48Txx (mkclock) device, for NetBSD/mvmeppc.
20060121	Adding an aux control register for ARM. (A BIG thank you to
		Olivier Houchard for tracking down this bug.)
20060122	Adding more ARM instructions (smulXY), and dev_iq80321_7seg.
20060124	Adding disassembly of more ARM instructions (mia*, mra/mar),
		and some semi-bogus XScale and i80321 registers.
20060201-02	Various minor updates. Moving the last machines out of
		machine.c.
20060204	Adding a -c command line option, for running debugger commands
		before the simulation starts, but after all files have been
		loaded.
		Minor iq80321-related updates.
20060209	Minor hacks (DEVINIT macro, etc).
		Preparing for the generalization of the 64-bit dyntrans address
		translation subsystem.
20060216	Adding ARM ldrd (double-register load).
20060217	Continuing on various ARM-related stuff.
20060218	More progress on the ATA/wdc emulation for NetBSD/iq80321.
		NetBSD/evbarm can now be installed :-)  Updating the docs, etc.
		Continuing on Algor emulation.

==============  RELEASE 0.3.8  ==============


1 /*
2 * Copyright (C) 2005 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: cpu_sh.c,v 1.9 2006/02/17 18:38:30 debug Exp $
29 *
30 * Hitachi SuperH ("SH") CPU emulation.
31 *
32 * TODO
33 */
34
35 #include <stdio.h>
36 #include <stdlib.h>
37 #include <string.h>
38 #include <ctype.h>
39
40 #include "cpu.h"
41 #include "machine.h"
42 #include "memory.h"
43 #include "misc.h"
44 #include "symbol.h"
45
46
47 #define DYNTRANS_DUALMODE_32
48 #include "tmp_sh_head.c"
49
50
51 /*
52 * sh_cpu_new():
53 *
54 * Create a new SH cpu object.
55 *
56 * Returns 1 on success, 0 if there was no matching SH processor with
57 * this cpu_type_name.
58 */
59 int sh_cpu_new(struct cpu *cpu, struct memory *mem, struct machine *machine,
60 int cpu_id, char *cpu_type_name)
61 {
62 if (strcasecmp(cpu_type_name, "SH") != 0)
63 return 0;
64
65 cpu->memory_rw = sh_memory_rw;
66
67 /* TODO: per CPU type? */
68 cpu->byte_order = EMUL_LITTLE_ENDIAN;
69 cpu->is_32bit = 1;
70 cpu->cd.sh.bits = 32;
71 cpu->cd.sh.compact = 1;
72
73 if (cpu->is_32bit) {
74 cpu->update_translation_table = sh32_update_translation_table;
75 cpu->invalidate_translation_caches =
76 sh32_invalidate_translation_caches;
77 cpu->invalidate_code_translation =
78 sh32_invalidate_code_translation;
79 } else {
80 cpu->update_translation_table = sh_update_translation_table;
81 cpu->invalidate_translation_caches =
82 sh_invalidate_translation_caches;
83 cpu->invalidate_code_translation =
84 sh_invalidate_code_translation;
85 }
86
87 /* Only show name and caches etc for CPU nr 0 (in SMP machines): */
88 if (cpu_id == 0) {
89 debug("%s", cpu->name);
90 }
91
92 return 1;
93 }
94
95
96 /*
97 * sh_cpu_list_available_types():
98 *
99 * Print a list of available SH CPU types.
100 */
101 void sh_cpu_list_available_types(void)
102 {
103 debug("SH\n");
104 /* TODO */
105 }
106
107
108 /*
109 * sh_cpu_dumpinfo():
110 */
111 void sh_cpu_dumpinfo(struct cpu *cpu)
112 {
113 debug("\n");
114 /* TODO */
115 }
116
117
118 /*
119 * sh_cpu_register_dump():
120 *
121 * Dump cpu registers in a relatively readable format.
122 *
123 * gprs: set to non-zero to dump GPRs and some special-purpose registers.
124 * coprocs: set bit 0..3 to dump registers in coproc 0..3.
125 */
126 void sh_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs)
127 {
128 char *symbol;
129 uint64_t offset;
130 int i, x = cpu->cpu_id, nregs = cpu->cd.sh.compact? 16 : 64;
131 int bits32 = cpu->cd.sh.bits == 32;
132
133 if (gprs) {
134 /* Special registers (pc, ...) first: */
135 symbol = get_symbol_name(&cpu->machine->symbol_context,
136 cpu->pc, &offset);
137
138 debug("cpu%i: pc = 0x", x);
139 if (bits32)
140 debug("%08x", (int)cpu->pc);
141 else
142 debug("%016llx", (long long)cpu->pc);
143 debug(" <%s>\n", symbol != NULL? symbol : " no symbol ");
144
145 if (bits32) {
146 /* 32-bit: */
147 for (i=0; i<nregs; i++) {
148 if ((i % 4) == 0)
149 debug("cpu%i:", x);
150 debug(" r%02i = 0x%08x ", i,
151 (int)cpu->cd.sh.r[i]);
152 if ((i % 4) == 3)
153 debug("\n");
154 }
155 } else {
156 /* 64-bit: */
157 for (i=0; i<nregs; i++) {
158 int r = (i >> 1) + ((i & 1) << 4);
159 if ((i % 2) == 0)
160 debug("cpu%i:", x);
161 debug(" r%02i = 0x%016llx ", r,
162 (long long)cpu->cd.sh.r[r]);
163 if ((i % 2) == 1)
164 debug("\n");
165 }
166 }
167 }
168 }
169
170
171 /*
172 * sh_cpu_register_match():
173 */
174 void sh_cpu_register_match(struct machine *m, char *name,
175 int writeflag, uint64_t *valuep, int *match_register)
176 {
177 int cpunr = 0;
178
179 /* CPU number: */
180
181 /* TODO */
182
183 /* Register name: */
184 if (strcasecmp(name, "pc") == 0) {
185 if (writeflag) {
186 m->cpus[cpunr]->pc = *valuep;
187 } else
188 *valuep = m->cpus[cpunr]->pc;
189 *match_register = 1;
190 }
191 }
192
193
194 /*
195 * sh_cpu_interrupt():
196 */
197 int sh_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr)
198 {
199 fatal("sh_cpu_interrupt(): TODO\n");
200 return 0;
201 }
202
203
204 /*
205 * sh_cpu_interrupt_ack():
206 */
207 int sh_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr)
208 {
209 /* fatal("sh_cpu_interrupt_ack(): TODO\n"); */
210 return 0;
211 }
212
213
214 /*
215 * sh_cpu_disassemble_instr_compact():
216 *
217 * SHcompact instruction disassembly. The top 4 bits of each 16-bit
218 * instruction word is used as the main opcode. For most instructions, the
219 * lowest 4 or 8 bits then select sub-opcode.
220 */
221 int sh_cpu_disassemble_instr_compact(struct cpu *cpu, unsigned char *instr,
222 int running, uint64_t dumpaddr, int bintrans)
223 {
224 uint64_t addr;
225 uint16_t iword;
226 int hi4, lo4, lo8, r8, r4;
227
228 if (cpu->byte_order == EMUL_BIG_ENDIAN)
229 iword = (instr[0] << 8) + instr[1];
230 else
231 iword = (instr[1] << 8) + instr[0];
232
233 debug(": %04x \t", iword);
234 hi4 = iword >> 12; lo4 = iword & 15; lo8 = iword & 255;
235 r8 = (iword >> 8) & 15; r4 = (iword >> 4) & 15;
236
237 /*
238 * Decode the instruction:
239 */
240
241 switch (hi4) {
242 case 0x0:
243 if (lo8 == 0x02)
244 debug("stc\tsr,r%i\n", r8);
245 else if (lo8 == 0x03)
246 debug("bsrf\tr%i\n", r8);
247 else if (lo4 == 0x4)
248 debug("mov.b\tr%i,@(r0,r%i)\n", r4, r8);
249 else if (lo4 == 0x5)
250 debug("mov.w\tr%i,@(r0,r%i)\n", r4, r8);
251 else if (lo4 == 0x6)
252 debug("mov.l\tr%i,@(r0,r%i)\n", r4, r8);
253 else if (lo4 == 0x7)
254 debug("mul.l\tr%i,r%i\n", r4, r8);
255 else if (iword == 0x0008)
256 debug("clrt\n");
257 else if (iword == 0x0009)
258 debug("nop\n");
259 else if (lo8 == 0x0a)
260 debug("sts\tmach,r%i\n", r8);
261 else if (iword == 0x000b)
262 debug("rts\n");
263 else if (lo4 == 0xc)
264 debug("mov.b\t@(r0,r%i),r%i\n", r4, r8);
265 else if (lo4 == 0xd)
266 debug("mov.w\t@(r0,r%i),r%i\n", r4, r8);
267 else if (lo4 == 0xe)
268 debug("mov.l\t@(r0,r%i),r%i\n", r4, r8);
269 else if (lo8 == 0x12)
270 debug("stc\tgbr,r%i\n", r8);
271 else if (iword == 0x0018)
272 debug("sett\n");
273 else if (iword == 0x0019)
274 debug("div0u\n");
275 else if (lo8 == 0x1a)
276 debug("sts\tmacl,r%i\n", r8);
277 else if (lo8 == 0x23)
278 debug("braf\tr%i\n", r8);
279 else if (iword == 0x0028)
280 debug("clrmac\n");
281 else if (lo8 == 0x29)
282 debug("movt\tr%i\n", r8);
283 else if (iword == 0x003b)
284 debug("brk\n");
285 else if (iword == 0x0048)
286 debug("clrs\n");
287 else if (iword == 0x0058)
288 debug("sets\n");
289 else if (lo8 == 0x83)
290 debug("pref\t@r%i\n", r8);
291 else
292 debug("UNIMPLEMENTED hi4=0x%x, lo8=0x%02x\n", hi4, lo8);
293 break;
294 case 0x1:
295 debug("mov.l\tr%i,@(%i,r%i)\n", r4, lo4 * 4, r8);
296 break;
297 case 0x2:
298 if (lo4 == 0x0)
299 debug("mov.b\tr%i,@r%i\n", r4, r8);
300 else if (lo4 == 0x1)
301 debug("mov.w\tr%i,@r%i\n", r4, r8);
302 else if (lo4 == 0x2)
303 debug("mov.l\tr%i,@r%i\n", r4, r8);
304 else if (lo4 == 0x4)
305 debug("mov.b\tr%i,@-r%i\n", r4, r8);
306 else if (lo4 == 0x5)
307 debug("mov.w\tr%i,@-r%i\n", r4, r8);
308 else if (lo4 == 0x6)
309 debug("mov.l\tr%i,@-r%i\n", r4, r8);
310 else if (lo4 == 0x7)
311 debug("div0s\tr%i,r%i\n", r4, r8);
312 else if (lo4 == 0x8)
313 debug("tst\tr%i,r%i\n", r4, r8);
314 else if (lo4 == 0x9)
315 debug("and\tr%i,r%i\n", r4, r8);
316 else if (lo4 == 0xa)
317 debug("xor\tr%i,r%i\n", r4, r8);
318 else if (lo4 == 0xb)
319 debug("or\tr%i,r%i\n", r4, r8);
320 else if (lo4 == 0xc)
321 debug("cmp/str\tr%i,r%i\n", r4, r8);
322 else if (lo4 == 0xd)
323 debug("xtrct\tr%i,r%i\n", r4, r8);
324 else if (lo4 == 0xe)
325 debug("mulu.w\tr%i,r%i\n", r4, r8);
326 else if (lo4 == 0xf)
327 debug("muls.w\tr%i,r%i\n", r4, r8);
328 else
329 debug("UNIMPLEMENTED hi4=0x%x, lo8=0x%02x\n", hi4, lo8);
330 break;
331 case 0x3:
332 if (lo4 == 0x0)
333 debug("cmp/eq\tr%i,r%i\n", r4, r8);
334 else if (lo4 == 0x2)
335 debug("cmp/hs\tr%i,r%i\n", r4, r8);
336 else if (lo4 == 0x3)
337 debug("cmp/ge\tr%i,r%i\n", r4, r8);
338 else if (lo4 == 0x4)
339 debug("div1\tr%i,r%i\n", r4, r8);
340 else if (lo4 == 0x5)
341 debug("dmulu.l\tr%i,r%i\n", r4, r8);
342 else if (lo4 == 0x6)
343 debug("cmp/hi\tr%i,r%i\n", r4, r8);
344 else if (lo4 == 0x7)
345 debug("cmp/gt\tr%i,r%i\n", r4, r8);
346 else if (lo4 == 0x8)
347 debug("sub\tr%i,r%i\n", r4, r8);
348 else if (lo4 == 0xa)
349 debug("subc\tr%i,r%i\n", r4, r8);
350 else if (lo4 == 0xb)
351 debug("subv\tr%i,r%i\n", r4, r8);
352 else if (lo4 == 0xc)
353 debug("add\tr%i,r%i\n", r4, r8);
354 else if (lo4 == 0xd)
355 debug("dmuls.l\tr%i,r%i\n", r4, r8);
356 else if (lo4 == 0xe)
357 debug("addc\tr%i,r%i\n", r4, r8);
358 else if (lo4 == 0xf)
359 debug("addv\tr%i,r%i\n", r4, r8);
360 else
361 debug("UNIMPLEMENTED hi4=0x%x, lo8=0x%02x\n", hi4, lo8);
362 break;
363 case 0x4:
364 if (lo8 == 0x00)
365 debug("shll\tr%i\n", r8);
366 else if (lo8 == 0x01)
367 debug("shlr\tr%i\n", r8);
368 else if (lo8 == 0x04)
369 debug("rotl\tr%i\n", r8);
370 else if (lo8 == 0x05)
371 debug("rotr\tr%i\n", r8);
372 else if (lo8 == 0x06)
373 debug("lds.l\t@r%i+,mach\n", r8);
374 else if (lo8 == 0x08)
375 debug("shll2\tr%i\n", r8);
376 else if (lo8 == 0x09)
377 debug("shlr2\tr%i\n", r8);
378 else if (lo8 == 0x0a)
379 debug("lds\tr%i,mach\n", r8);
380 else if (lo8 == 0x0b)
381 debug("jsr\t@r%i\n", r8);
382 else if (lo4 == 0xc)
383 debug("shad\tr%i,r%i\n", r4, r8);
384 else if (lo4 == 0xd)
385 debug("shld\tr%i,r%i\n", r4, r8);
386 else if (lo8 == 0x0e)
387 debug("ldc\tr%i,sr\n", r8);
388 else if (lo8 == 0x10)
389 debug("dt\tr%i\n", r8);
390 else if (lo8 == 0x11)
391 debug("cmp/pz\tr%i\n", r8);
392 else if (lo8 == 0x15)
393 debug("cmp/pl\tr%i\n", r8);
394 else if (lo8 == 0x16)
395 debug("lds.l\t@r%i+,macl\n", r8);
396 else if (lo8 == 0x18)
397 debug("shll8\tr%i\n", r8);
398 else if (lo8 == 0x19)
399 debug("shlr8\tr%i\n", r8);
400 else if (lo8 == 0x1a)
401 debug("lds\tr%i,macl\n", r8);
402 else if (lo8 == 0x1b)
403 debug("tas.b\t@r%i\n", r8);
404 else if (lo8 == 0x1e)
405 debug("ldc\tr%i,gbr\n", r8);
406 else if (lo8 == 0x20)
407 debug("shal\tr%i\n", r8);
408 else if (lo8 == 0x21)
409 debug("shar\tr%i\n", r8);
410 else if (lo8 == 0x22)
411 debug("sts.l\tpr,@-r%i\n", r8);
412 else if (lo8 == 0x24)
413 debug("rotcl\tr%i\n", r8);
414 else if (lo8 == 0x25)
415 debug("rotcr\tr%i\n", r8);
416 else if (lo8 == 0x26)
417 debug("lds.l\t@r%i+,pr\n", r8);
418 else if (lo8 == 0x28)
419 debug("shll16\tr%i\n", r8);
420 else if (lo8 == 0x29)
421 debug("shlr16\tr%i\n", r8);
422 else if (lo8 == 0x2a)
423 debug("lds\tr%i,pr\n", r8);
424 else if (lo8 == 0x2b)
425 debug("jmp\t@r%i\n", r8);
426 else if (lo8 == 0x56)
427 debug("lds.l\t@r%i+,fpul\n", r8);
428 else if (lo8 == 0x5a)
429 debug("lds\tr%i,fpul\n", r8);
430 else if (lo8 == 0x6a)
431 debug("lds\tr%i,fpscr\n", r8);
432 else
433 debug("UNIMPLEMENTED hi4=0x%x, lo8=0x%02x\n", hi4, lo8);
434 break;
435 case 0x5:
436 debug("mov.l\t@(%i,r%i),r%i\n", lo4 * 4, r4, r8);
437 break;
438 case 0x6:
439 if (lo4 == 0x0)
440 debug("mov.b\t@r%i,r%i\n", r4, r8);
441 else if (lo4 == 0x1)
442 debug("mov.w\t@r%i,r%i\n", r4, r8);
443 else if (lo4 == 0x2)
444 debug("mov.l\t@r%i,r%i\n", r4, r8);
445 else if (lo4 == 0x3)
446 debug("mov\tr%i,r%i\n", r4, r8);
447 else if (lo4 == 0x4)
448 debug("mov.b\t@r%i+,r%i\n", r4, r8);
449 else if (lo4 == 0x6)
450 debug("mov.l\t@r%i+,r%i\n", r4, r8);
451 else if (lo4 == 0x7)
452 debug("not\tr%i,r%i\n", r4, r8);
453 else if (lo4 == 0x8)
454 debug("swap.b\tr%i,r%i\n", r4, r8);
455 else if (lo4 == 0x9)
456 debug("swap.w\tr%i,r%i\n", r4, r8);
457 else if (lo4 == 0xa)
458 debug("negc\tr%i,r%i\n", r4, r8);
459 else if (lo4 == 0xb)
460 debug("neg\tr%i,r%i\n", r4, r8);
461 else if (lo4 == 0xc)
462 debug("extu.b\tr%i,r%i\n", r4, r8);
463 else if (lo4 == 0xd)
464 debug("extu.w\tr%i,r%i\n", r4, r8);
465 else if (lo4 == 0xe)
466 debug("exts.b\tr%i,r%i\n", r4, r8);
467 else if (lo4 == 0xf)
468 debug("exts.w\tr%i,r%i\n", r4, r8);
469 else
470 debug("UNIMPLEMENTED hi4=0x%x, lo8=0x%02x\n", hi4, lo8);
471 break;
472 case 0x7:
473 debug("add\t#%i,r%i\n", (int8_t)lo8, r8);
474 break;
475 case 0x8:
476 if (r8 == 0x8)
477 debug("cmp/eq\t#%i,r0\n", (int8_t)lo8);
478 else if (r8 == 0x9 || r8 == 0xb || r8 == 0xd || r8 == 0xf) {
479 addr = (int8_t)lo8;
480 addr = dumpaddr + 4 + (addr << 1);
481 debug("b%s%s\t0x%x\n",
482 (r8 == 0x9 || r8 == 0xd)? "t" : "f",
483 (r8 == 0x9 || r8 == 0xb)? "" : "/s", (int)addr);
484 } else
485 debug("UNIMPLEMENTED hi4=0x%x,0x%x\n", hi4, r8);
486 break;
487 case 0x9:
488 case 0xd:
489 addr = ((int8_t)lo8) * (hi4==9? 2 : 4);
490 addr += (dumpaddr & ~(hi4==9? 1 : 3)) + 4;
491 debug("mov.%s\t0x%x,r%i\n", hi4==9? "w":"l", (int)addr, r8);
492 break;
493 case 0xa:
494 case 0xb:
495 addr = (int32_t)(int16_t)((iword & 0xfff) << 4);
496 addr = ((int32_t)addr >> 3);
497 addr += dumpaddr + 4;
498 debug("%s\t0x%x\n", hi4==0xa? "bra":"bsr", (int)addr);
499 break;
500 case 0xc:
501 if (r8 == 0x3)
502 debug("trapa\t#%i\n", (uint8_t)lo8);
503 else if (r8 == 0x8)
504 debug("tst\t#%i,r0\n", (uint8_t)lo8);
505 else if (r8 == 0x9)
506 debug("and\t#%i,r0\n", (uint8_t)lo8);
507 else if (r8 == 0xa)
508 debug("xor\t#%i,r0\n", (uint8_t)lo8);
509 else if (r8 == 0xb)
510 debug("or\t#%i,r0\n", (uint8_t)lo8);
511 else if (r8 == 0xc)
512 debug("tst.b\t#%i,@(r0,gbr)\n", (uint8_t)lo8);
513 else if (r8 == 0xd)
514 debug("and.b\t#%i,@(r0,gbr)\n", (uint8_t)lo8);
515 else if (r8 == 0xe)
516 debug("xor.b\t#%i,@(r0,gbr)\n", (uint8_t)lo8);
517 else if (r8 == 0xf)
518 debug("or.b\t#%i,@(r0,gbr)\n", (uint8_t)lo8);
519 else
520 debug("UNIMPLEMENTED hi4=0x%x,0x%x\n", hi4, r8);
521 break;
522 case 0xe:
523 debug("mov\t#%i,r%i\n", (int8_t)lo8, r8);
524 break;
525 default:debug("UNIMPLEMENTED hi4=0x%x\n", hi4);
526 }
527
528 return sizeof(iword);
529 }
530
531
532 /*
533 * sh_cpu_disassemble_instr():
534 *
535 * Convert an instruction word into human readable format, for instruction
536 * tracing.
537 *
538 * If running is 1, cpu->pc should be the address of the instruction.
539 *
540 * If running is 0, things that depend on the runtime environment (eg.
541 * register contents) will not be shown, and addr will be used instead of
542 * cpu->pc for relative addresses.
543 */
544 int sh_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr,
545 int running, uint64_t dumpaddr, int bintrans)
546 {
547 uint64_t offset;
548 uint32_t iword;
549 char *symbol;
550
551 if (running)
552 dumpaddr = cpu->pc;
553
554 symbol = get_symbol_name(&cpu->machine->symbol_context,
555 dumpaddr, &offset);
556 if (symbol != NULL && offset==0)
557 debug("<%s>\n", symbol);
558
559 if (cpu->machine->ncpus > 1 && running)
560 debug("cpu%i: ", cpu->cpu_id);
561
562 if (cpu->cd.sh.bits == 32)
563 debug("%08x", (int)dumpaddr);
564 else
565 debug("%016llx", (long long)dumpaddr);
566
567 if (cpu->cd.sh.compact)
568 return sh_cpu_disassemble_instr_compact(cpu, instr,
569 running, dumpaddr, bintrans);
570
571 if (cpu->byte_order == EMUL_BIG_ENDIAN)
572 iword = (instr[0] << 24) + (instr[1] << 16) + (instr[2] << 8)
573 + instr[3];
574 else
575 iword = (instr[3] << 24) + (instr[2] << 16) + (instr[1] << 8)
576 + instr[0];
577
578 debug(": %08x\t", iword);
579
580 /*
581 * Decode the instruction:
582 */
583
584 debug("TODO\n");
585
586 return sizeof(iword);
587 }
588
589
590 #include "tmp_sh_tail.c"
591

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