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dpavlin |
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/* |
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dpavlin |
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* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
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dpavlin |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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dpavlin |
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* $Id: cpu_sh.c,v 1.16 2006/06/24 21:47:23 debug Exp $ |
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dpavlin |
14 |
* |
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* Hitachi SuperH ("SH") CPU emulation. |
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* |
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* TODO |
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*/ |
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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#include <ctype.h> |
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#include "cpu.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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#include "symbol.h" |
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#define DYNTRANS_DUALMODE_32 |
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#include "tmp_sh_head.c" |
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/* |
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* sh_cpu_new(): |
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* |
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* Create a new SH cpu object. |
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* |
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* Returns 1 on success, 0 if there was no matching SH processor with |
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* this cpu_type_name. |
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*/ |
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int sh_cpu_new(struct cpu *cpu, struct memory *mem, struct machine *machine, |
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int cpu_id, char *cpu_type_name) |
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{ |
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if (strcasecmp(cpu_type_name, "SH") != 0) |
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return 0; |
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cpu->memory_rw = sh_memory_rw; |
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/* TODO: per CPU type? */ |
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cpu->byte_order = EMUL_LITTLE_ENDIAN; |
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cpu->is_32bit = 1; |
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cpu->cd.sh.bits = 32; |
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cpu->cd.sh.compact = 1; |
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if (cpu->is_32bit) { |
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cpu->update_translation_table = sh32_update_translation_table; |
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dpavlin |
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cpu->invalidate_translation_caches = |
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sh32_invalidate_translation_caches; |
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dpavlin |
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cpu->invalidate_code_translation = |
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sh32_invalidate_code_translation; |
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} else { |
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cpu->update_translation_table = sh_update_translation_table; |
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dpavlin |
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cpu->invalidate_translation_caches = |
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sh_invalidate_translation_caches; |
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dpavlin |
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cpu->invalidate_code_translation = |
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sh_invalidate_code_translation; |
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} |
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/* Only show name and caches etc for CPU nr 0 (in SMP machines): */ |
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if (cpu_id == 0) { |
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debug("%s", cpu->name); |
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} |
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return 1; |
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} |
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/* |
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* sh_cpu_list_available_types(): |
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* |
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* Print a list of available SH CPU types. |
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*/ |
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void sh_cpu_list_available_types(void) |
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{ |
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debug("SH\n"); |
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/* TODO */ |
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} |
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/* |
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* sh_cpu_dumpinfo(): |
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*/ |
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void sh_cpu_dumpinfo(struct cpu *cpu) |
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{ |
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debug("\n"); |
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/* TODO */ |
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} |
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/* |
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* sh_cpu_register_dump(): |
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* |
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* Dump cpu registers in a relatively readable format. |
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* |
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* gprs: set to non-zero to dump GPRs and some special-purpose registers. |
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* coprocs: set bit 0..3 to dump registers in coproc 0..3. |
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*/ |
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void sh_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs) |
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{ |
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char *symbol; |
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dpavlin |
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uint64_t offset; |
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dpavlin |
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int i, x = cpu->cpu_id, nregs = cpu->cd.sh.compact? 16 : 64; |
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int bits32 = cpu->cd.sh.bits == 32; |
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if (gprs) { |
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/* Special registers (pc, ...) first: */ |
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symbol = get_symbol_name(&cpu->machine->symbol_context, |
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cpu->pc, &offset); |
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debug("cpu%i: pc = 0x", x); |
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if (bits32) |
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debug("%08x", (int)cpu->pc); |
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else |
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debug("%016llx", (long long)cpu->pc); |
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debug(" <%s>\n", symbol != NULL? symbol : " no symbol "); |
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if (bits32) { |
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/* 32-bit: */ |
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for (i=0; i<nregs; i++) { |
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if ((i % 4) == 0) |
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debug("cpu%i:", x); |
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debug(" r%02i = 0x%08x ", i, |
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(int)cpu->cd.sh.r[i]); |
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if ((i % 4) == 3) |
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debug("\n"); |
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} |
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} else { |
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/* 64-bit: */ |
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for (i=0; i<nregs; i++) { |
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int r = (i >> 1) + ((i & 1) << 4); |
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if ((i % 2) == 0) |
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debug("cpu%i:", x); |
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debug(" r%02i = 0x%016llx ", r, |
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(long long)cpu->cd.sh.r[r]); |
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if ((i % 2) == 1) |
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debug("\n"); |
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} |
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} |
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} |
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} |
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/* |
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* sh_cpu_register_match(): |
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*/ |
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void sh_cpu_register_match(struct machine *m, char *name, |
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int writeflag, uint64_t *valuep, int *match_register) |
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{ |
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int cpunr = 0; |
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/* CPU number: */ |
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/* TODO */ |
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/* Register name: */ |
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if (strcasecmp(name, "pc") == 0) { |
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if (writeflag) { |
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m->cpus[cpunr]->pc = *valuep; |
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} else |
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*valuep = m->cpus[cpunr]->pc; |
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*match_register = 1; |
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} |
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} |
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/* |
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dpavlin |
24 |
* sh_cpu_tlbdump(): |
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* |
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* Called from the debugger to dump the TLB in a readable format. |
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* x is the cpu number to dump, or -1 to dump all CPUs. |
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* |
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* If rawflag is nonzero, then the TLB contents isn't formated nicely, |
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* just dumped. |
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*/ |
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void sh_cpu_tlbdump(struct machine *m, int x, int rawflag) |
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{ |
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} |
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/* |
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* sh_cpu_gdb_stub(): |
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* |
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* Execute a "remote GDB" command. Returns a newly allocated response string |
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* on success, NULL on failure. |
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*/ |
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char *sh_cpu_gdb_stub(struct cpu *cpu, char *cmd) |
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{ |
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fatal("sh_cpu_gdb_stub(): TODO\n"); |
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return NULL; |
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} |
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/* |
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dpavlin |
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* sh_cpu_interrupt(): |
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*/ |
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int sh_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr) |
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{ |
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fatal("sh_cpu_interrupt(): TODO\n"); |
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return 0; |
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} |
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/* |
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* sh_cpu_interrupt_ack(): |
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*/ |
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int sh_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr) |
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{ |
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/* fatal("sh_cpu_interrupt_ack(): TODO\n"); */ |
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return 0; |
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} |
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/* |
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* sh_cpu_disassemble_instr_compact(): |
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* |
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* SHcompact instruction disassembly. The top 4 bits of each 16-bit |
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* instruction word is used as the main opcode. For most instructions, the |
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* lowest 4 or 8 bits then select sub-opcode. |
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*/ |
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int sh_cpu_disassemble_instr_compact(struct cpu *cpu, unsigned char *instr, |
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dpavlin |
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int running, uint64_t dumpaddr) |
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dpavlin |
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{ |
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dpavlin |
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uint64_t addr; |
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dpavlin |
14 |
uint16_t iword; |
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int hi4, lo4, lo8, r8, r4; |
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if (cpu->byte_order == EMUL_BIG_ENDIAN) |
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iword = (instr[0] << 8) + instr[1]; |
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else |
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iword = (instr[1] << 8) + instr[0]; |
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debug(": %04x \t", iword); |
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hi4 = iword >> 12; lo4 = iword & 15; lo8 = iword & 255; |
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r8 = (iword >> 8) & 15; r4 = (iword >> 4) & 15; |
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/* |
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* Decode the instruction: |
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*/ |
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switch (hi4) { |
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case 0x0: |
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if (lo8 == 0x02) |
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debug("stc\tsr,r%i\n", r8); |
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else if (lo8 == 0x03) |
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debug("bsrf\tr%i\n", r8); |
| 274 |
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else if (lo4 == 0x4) |
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debug("mov.b\tr%i,@(r0,r%i)\n", r4, r8); |
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else if (lo4 == 0x5) |
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debug("mov.w\tr%i,@(r0,r%i)\n", r4, r8); |
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else if (lo4 == 0x6) |
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debug("mov.l\tr%i,@(r0,r%i)\n", r4, r8); |
| 280 |
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else if (lo4 == 0x7) |
| 281 |
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debug("mul.l\tr%i,r%i\n", r4, r8); |
| 282 |
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else if (iword == 0x0008) |
| 283 |
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debug("clrt\n"); |
| 284 |
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else if (iword == 0x0009) |
| 285 |
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debug("nop\n"); |
| 286 |
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else if (lo8 == 0x0a) |
| 287 |
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debug("sts\tmach,r%i\n", r8); |
| 288 |
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else if (iword == 0x000b) |
| 289 |
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debug("rts\n"); |
| 290 |
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else if (lo4 == 0xc) |
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debug("mov.b\t@(r0,r%i),r%i\n", r4, r8); |
| 292 |
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else if (lo4 == 0xd) |
| 293 |
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debug("mov.w\t@(r0,r%i),r%i\n", r4, r8); |
| 294 |
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else if (lo4 == 0xe) |
| 295 |
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debug("mov.l\t@(r0,r%i),r%i\n", r4, r8); |
| 296 |
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else if (lo8 == 0x12) |
| 297 |
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debug("stc\tgbr,r%i\n", r8); |
| 298 |
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else if (iword == 0x0018) |
| 299 |
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debug("sett\n"); |
| 300 |
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else if (iword == 0x0019) |
| 301 |
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debug("div0u\n"); |
| 302 |
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else if (lo8 == 0x1a) |
| 303 |
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debug("sts\tmacl,r%i\n", r8); |
| 304 |
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else if (lo8 == 0x23) |
| 305 |
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debug("braf\tr%i\n", r8); |
| 306 |
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else if (iword == 0x0028) |
| 307 |
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debug("clrmac\n"); |
| 308 |
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else if (lo8 == 0x29) |
| 309 |
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debug("movt\tr%i\n", r8); |
| 310 |
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else if (iword == 0x003b) |
| 311 |
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debug("brk\n"); |
| 312 |
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else if (iword == 0x0048) |
| 313 |
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debug("clrs\n"); |
| 314 |
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else if (iword == 0x0058) |
| 315 |
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debug("sets\n"); |
| 316 |
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else if (lo8 == 0x83) |
| 317 |
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debug("pref\t@r%i\n", r8); |
| 318 |
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else |
| 319 |
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debug("UNIMPLEMENTED hi4=0x%x, lo8=0x%02x\n", hi4, lo8); |
| 320 |
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break; |
| 321 |
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case 0x1: |
| 322 |
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debug("mov.l\tr%i,@(%i,r%i)\n", r4, lo4 * 4, r8); |
| 323 |
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break; |
| 324 |
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case 0x2: |
| 325 |
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if (lo4 == 0x0) |
| 326 |
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debug("mov.b\tr%i,@r%i\n", r4, r8); |
| 327 |
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else if (lo4 == 0x1) |
| 328 |
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debug("mov.w\tr%i,@r%i\n", r4, r8); |
| 329 |
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else if (lo4 == 0x2) |
| 330 |
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debug("mov.l\tr%i,@r%i\n", r4, r8); |
| 331 |
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else if (lo4 == 0x4) |
| 332 |
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debug("mov.b\tr%i,@-r%i\n", r4, r8); |
| 333 |
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else if (lo4 == 0x5) |
| 334 |
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debug("mov.w\tr%i,@-r%i\n", r4, r8); |
| 335 |
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else if (lo4 == 0x6) |
| 336 |
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debug("mov.l\tr%i,@-r%i\n", r4, r8); |
| 337 |
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else if (lo4 == 0x7) |
| 338 |
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debug("div0s\tr%i,r%i\n", r4, r8); |
| 339 |
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else if (lo4 == 0x8) |
| 340 |
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debug("tst\tr%i,r%i\n", r4, r8); |
| 341 |
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else if (lo4 == 0x9) |
| 342 |
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debug("and\tr%i,r%i\n", r4, r8); |
| 343 |
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else if (lo4 == 0xa) |
| 344 |
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debug("xor\tr%i,r%i\n", r4, r8); |
| 345 |
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else if (lo4 == 0xb) |
| 346 |
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debug("or\tr%i,r%i\n", r4, r8); |
| 347 |
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else if (lo4 == 0xc) |
| 348 |
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debug("cmp/str\tr%i,r%i\n", r4, r8); |
| 349 |
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else if (lo4 == 0xd) |
| 350 |
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debug("xtrct\tr%i,r%i\n", r4, r8); |
| 351 |
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else if (lo4 == 0xe) |
| 352 |
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debug("mulu.w\tr%i,r%i\n", r4, r8); |
| 353 |
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else if (lo4 == 0xf) |
| 354 |
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debug("muls.w\tr%i,r%i\n", r4, r8); |
| 355 |
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else |
| 356 |
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|
debug("UNIMPLEMENTED hi4=0x%x, lo8=0x%02x\n", hi4, lo8); |
| 357 |
|
|
break; |
| 358 |
|
|
case 0x3: |
| 359 |
|
|
if (lo4 == 0x0) |
| 360 |
|
|
debug("cmp/eq\tr%i,r%i\n", r4, r8); |
| 361 |
|
|
else if (lo4 == 0x2) |
| 362 |
|
|
debug("cmp/hs\tr%i,r%i\n", r4, r8); |
| 363 |
|
|
else if (lo4 == 0x3) |
| 364 |
|
|
debug("cmp/ge\tr%i,r%i\n", r4, r8); |
| 365 |
|
|
else if (lo4 == 0x4) |
| 366 |
|
|
debug("div1\tr%i,r%i\n", r4, r8); |
| 367 |
|
|
else if (lo4 == 0x5) |
| 368 |
|
|
debug("dmulu.l\tr%i,r%i\n", r4, r8); |
| 369 |
|
|
else if (lo4 == 0x6) |
| 370 |
|
|
debug("cmp/hi\tr%i,r%i\n", r4, r8); |
| 371 |
|
|
else if (lo4 == 0x7) |
| 372 |
|
|
debug("cmp/gt\tr%i,r%i\n", r4, r8); |
| 373 |
|
|
else if (lo4 == 0x8) |
| 374 |
|
|
debug("sub\tr%i,r%i\n", r4, r8); |
| 375 |
|
|
else if (lo4 == 0xa) |
| 376 |
|
|
debug("subc\tr%i,r%i\n", r4, r8); |
| 377 |
|
|
else if (lo4 == 0xb) |
| 378 |
|
|
debug("subv\tr%i,r%i\n", r4, r8); |
| 379 |
|
|
else if (lo4 == 0xc) |
| 380 |
|
|
debug("add\tr%i,r%i\n", r4, r8); |
| 381 |
|
|
else if (lo4 == 0xd) |
| 382 |
|
|
debug("dmuls.l\tr%i,r%i\n", r4, r8); |
| 383 |
|
|
else if (lo4 == 0xe) |
| 384 |
|
|
debug("addc\tr%i,r%i\n", r4, r8); |
| 385 |
|
|
else if (lo4 == 0xf) |
| 386 |
|
|
debug("addv\tr%i,r%i\n", r4, r8); |
| 387 |
|
|
else |
| 388 |
|
|
debug("UNIMPLEMENTED hi4=0x%x, lo8=0x%02x\n", hi4, lo8); |
| 389 |
|
|
break; |
| 390 |
|
|
case 0x4: |
| 391 |
|
|
if (lo8 == 0x00) |
| 392 |
|
|
debug("shll\tr%i\n", r8); |
| 393 |
|
|
else if (lo8 == 0x01) |
| 394 |
|
|
debug("shlr\tr%i\n", r8); |
| 395 |
|
|
else if (lo8 == 0x04) |
| 396 |
|
|
debug("rotl\tr%i\n", r8); |
| 397 |
|
|
else if (lo8 == 0x05) |
| 398 |
|
|
debug("rotr\tr%i\n", r8); |
| 399 |
|
|
else if (lo8 == 0x06) |
| 400 |
|
|
debug("lds.l\t@r%i+,mach\n", r8); |
| 401 |
|
|
else if (lo8 == 0x08) |
| 402 |
|
|
debug("shll2\tr%i\n", r8); |
| 403 |
|
|
else if (lo8 == 0x09) |
| 404 |
|
|
debug("shlr2\tr%i\n", r8); |
| 405 |
|
|
else if (lo8 == 0x0a) |
| 406 |
|
|
debug("lds\tr%i,mach\n", r8); |
| 407 |
|
|
else if (lo8 == 0x0b) |
| 408 |
|
|
debug("jsr\t@r%i\n", r8); |
| 409 |
|
|
else if (lo4 == 0xc) |
| 410 |
|
|
debug("shad\tr%i,r%i\n", r4, r8); |
| 411 |
|
|
else if (lo4 == 0xd) |
| 412 |
|
|
debug("shld\tr%i,r%i\n", r4, r8); |
| 413 |
|
|
else if (lo8 == 0x0e) |
| 414 |
|
|
debug("ldc\tr%i,sr\n", r8); |
| 415 |
|
|
else if (lo8 == 0x10) |
| 416 |
|
|
debug("dt\tr%i\n", r8); |
| 417 |
|
|
else if (lo8 == 0x11) |
| 418 |
|
|
debug("cmp/pz\tr%i\n", r8); |
| 419 |
|
|
else if (lo8 == 0x15) |
| 420 |
|
|
debug("cmp/pl\tr%i\n", r8); |
| 421 |
|
|
else if (lo8 == 0x16) |
| 422 |
|
|
debug("lds.l\t@r%i+,macl\n", r8); |
| 423 |
|
|
else if (lo8 == 0x18) |
| 424 |
|
|
debug("shll8\tr%i\n", r8); |
| 425 |
|
|
else if (lo8 == 0x19) |
| 426 |
|
|
debug("shlr8\tr%i\n", r8); |
| 427 |
|
|
else if (lo8 == 0x1a) |
| 428 |
|
|
debug("lds\tr%i,macl\n", r8); |
| 429 |
|
|
else if (lo8 == 0x1b) |
| 430 |
|
|
debug("tas.b\t@r%i\n", r8); |
| 431 |
|
|
else if (lo8 == 0x1e) |
| 432 |
|
|
debug("ldc\tr%i,gbr\n", r8); |
| 433 |
|
|
else if (lo8 == 0x20) |
| 434 |
|
|
debug("shal\tr%i\n", r8); |
| 435 |
|
|
else if (lo8 == 0x21) |
| 436 |
|
|
debug("shar\tr%i\n", r8); |
| 437 |
|
|
else if (lo8 == 0x22) |
| 438 |
|
|
debug("sts.l\tpr,@-r%i\n", r8); |
| 439 |
|
|
else if (lo8 == 0x24) |
| 440 |
|
|
debug("rotcl\tr%i\n", r8); |
| 441 |
|
|
else if (lo8 == 0x25) |
| 442 |
|
|
debug("rotcr\tr%i\n", r8); |
| 443 |
|
|
else if (lo8 == 0x26) |
| 444 |
|
|
debug("lds.l\t@r%i+,pr\n", r8); |
| 445 |
|
|
else if (lo8 == 0x28) |
| 446 |
|
|
debug("shll16\tr%i\n", r8); |
| 447 |
|
|
else if (lo8 == 0x29) |
| 448 |
|
|
debug("shlr16\tr%i\n", r8); |
| 449 |
|
|
else if (lo8 == 0x2a) |
| 450 |
|
|
debug("lds\tr%i,pr\n", r8); |
| 451 |
|
|
else if (lo8 == 0x2b) |
| 452 |
|
|
debug("jmp\t@r%i\n", r8); |
| 453 |
|
|
else if (lo8 == 0x56) |
| 454 |
|
|
debug("lds.l\t@r%i+,fpul\n", r8); |
| 455 |
|
|
else if (lo8 == 0x5a) |
| 456 |
|
|
debug("lds\tr%i,fpul\n", r8); |
| 457 |
|
|
else if (lo8 == 0x6a) |
| 458 |
|
|
debug("lds\tr%i,fpscr\n", r8); |
| 459 |
|
|
else |
| 460 |
|
|
debug("UNIMPLEMENTED hi4=0x%x, lo8=0x%02x\n", hi4, lo8); |
| 461 |
|
|
break; |
| 462 |
|
|
case 0x5: |
| 463 |
|
|
debug("mov.l\t@(%i,r%i),r%i\n", lo4 * 4, r4, r8); |
| 464 |
|
|
break; |
| 465 |
|
|
case 0x6: |
| 466 |
|
|
if (lo4 == 0x0) |
| 467 |
|
|
debug("mov.b\t@r%i,r%i\n", r4, r8); |
| 468 |
|
|
else if (lo4 == 0x1) |
| 469 |
|
|
debug("mov.w\t@r%i,r%i\n", r4, r8); |
| 470 |
|
|
else if (lo4 == 0x2) |
| 471 |
|
|
debug("mov.l\t@r%i,r%i\n", r4, r8); |
| 472 |
|
|
else if (lo4 == 0x3) |
| 473 |
|
|
debug("mov\tr%i,r%i\n", r4, r8); |
| 474 |
|
|
else if (lo4 == 0x4) |
| 475 |
|
|
debug("mov.b\t@r%i+,r%i\n", r4, r8); |
| 476 |
|
|
else if (lo4 == 0x6) |
| 477 |
|
|
debug("mov.l\t@r%i+,r%i\n", r4, r8); |
| 478 |
|
|
else if (lo4 == 0x7) |
| 479 |
|
|
debug("not\tr%i,r%i\n", r4, r8); |
| 480 |
|
|
else if (lo4 == 0x8) |
| 481 |
|
|
debug("swap.b\tr%i,r%i\n", r4, r8); |
| 482 |
|
|
else if (lo4 == 0x9) |
| 483 |
|
|
debug("swap.w\tr%i,r%i\n", r4, r8); |
| 484 |
|
|
else if (lo4 == 0xa) |
| 485 |
|
|
debug("negc\tr%i,r%i\n", r4, r8); |
| 486 |
|
|
else if (lo4 == 0xb) |
| 487 |
|
|
debug("neg\tr%i,r%i\n", r4, r8); |
| 488 |
|
|
else if (lo4 == 0xc) |
| 489 |
|
|
debug("extu.b\tr%i,r%i\n", r4, r8); |
| 490 |
|
|
else if (lo4 == 0xd) |
| 491 |
|
|
debug("extu.w\tr%i,r%i\n", r4, r8); |
| 492 |
|
|
else if (lo4 == 0xe) |
| 493 |
|
|
debug("exts.b\tr%i,r%i\n", r4, r8); |
| 494 |
|
|
else if (lo4 == 0xf) |
| 495 |
|
|
debug("exts.w\tr%i,r%i\n", r4, r8); |
| 496 |
|
|
else |
| 497 |
|
|
debug("UNIMPLEMENTED hi4=0x%x, lo8=0x%02x\n", hi4, lo8); |
| 498 |
|
|
break; |
| 499 |
|
|
case 0x7: |
| 500 |
|
|
debug("add\t#%i,r%i\n", (int8_t)lo8, r8); |
| 501 |
|
|
break; |
| 502 |
|
|
case 0x8: |
| 503 |
|
|
if (r8 == 0x8) |
| 504 |
|
|
debug("cmp/eq\t#%i,r0\n", (int8_t)lo8); |
| 505 |
|
|
else if (r8 == 0x9 || r8 == 0xb || r8 == 0xd || r8 == 0xf) { |
| 506 |
|
|
addr = (int8_t)lo8; |
| 507 |
|
|
addr = dumpaddr + 4 + (addr << 1); |
| 508 |
|
|
debug("b%s%s\t0x%x\n", |
| 509 |
|
|
(r8 == 0x9 || r8 == 0xd)? "t" : "f", |
| 510 |
|
|
(r8 == 0x9 || r8 == 0xb)? "" : "/s", (int)addr); |
| 511 |
|
|
} else |
| 512 |
|
|
debug("UNIMPLEMENTED hi4=0x%x,0x%x\n", hi4, r8); |
| 513 |
|
|
break; |
| 514 |
|
|
case 0x9: |
| 515 |
|
|
case 0xd: |
| 516 |
|
|
addr = ((int8_t)lo8) * (hi4==9? 2 : 4); |
| 517 |
|
|
addr += (dumpaddr & ~(hi4==9? 1 : 3)) + 4; |
| 518 |
|
|
debug("mov.%s\t0x%x,r%i\n", hi4==9? "w":"l", (int)addr, r8); |
| 519 |
|
|
break; |
| 520 |
|
|
case 0xa: |
| 521 |
|
|
case 0xb: |
| 522 |
|
|
addr = (int32_t)(int16_t)((iword & 0xfff) << 4); |
| 523 |
|
|
addr = ((int32_t)addr >> 3); |
| 524 |
|
|
addr += dumpaddr + 4; |
| 525 |
|
|
debug("%s\t0x%x\n", hi4==0xa? "bra":"bsr", (int)addr); |
| 526 |
|
|
break; |
| 527 |
|
|
case 0xc: |
| 528 |
|
|
if (r8 == 0x3) |
| 529 |
|
|
debug("trapa\t#%i\n", (uint8_t)lo8); |
| 530 |
|
|
else if (r8 == 0x8) |
| 531 |
|
|
debug("tst\t#%i,r0\n", (uint8_t)lo8); |
| 532 |
|
|
else if (r8 == 0x9) |
| 533 |
|
|
debug("and\t#%i,r0\n", (uint8_t)lo8); |
| 534 |
|
|
else if (r8 == 0xa) |
| 535 |
|
|
debug("xor\t#%i,r0\n", (uint8_t)lo8); |
| 536 |
|
|
else if (r8 == 0xb) |
| 537 |
|
|
debug("or\t#%i,r0\n", (uint8_t)lo8); |
| 538 |
|
|
else if (r8 == 0xc) |
| 539 |
|
|
debug("tst.b\t#%i,@(r0,gbr)\n", (uint8_t)lo8); |
| 540 |
|
|
else if (r8 == 0xd) |
| 541 |
|
|
debug("and.b\t#%i,@(r0,gbr)\n", (uint8_t)lo8); |
| 542 |
|
|
else if (r8 == 0xe) |
| 543 |
|
|
debug("xor.b\t#%i,@(r0,gbr)\n", (uint8_t)lo8); |
| 544 |
|
|
else if (r8 == 0xf) |
| 545 |
|
|
debug("or.b\t#%i,@(r0,gbr)\n", (uint8_t)lo8); |
| 546 |
|
|
else |
| 547 |
|
|
debug("UNIMPLEMENTED hi4=0x%x,0x%x\n", hi4, r8); |
| 548 |
|
|
break; |
| 549 |
|
|
case 0xe: |
| 550 |
|
|
debug("mov\t#%i,r%i\n", (int8_t)lo8, r8); |
| 551 |
|
|
break; |
| 552 |
|
|
default:debug("UNIMPLEMENTED hi4=0x%x\n", hi4); |
| 553 |
|
|
} |
| 554 |
|
|
|
| 555 |
|
|
return sizeof(iword); |
| 556 |
|
|
} |
| 557 |
|
|
|
| 558 |
|
|
|
| 559 |
|
|
/* |
| 560 |
|
|
* sh_cpu_disassemble_instr(): |
| 561 |
|
|
* |
| 562 |
|
|
* Convert an instruction word into human readable format, for instruction |
| 563 |
|
|
* tracing. |
| 564 |
|
|
* |
| 565 |
|
|
* If running is 1, cpu->pc should be the address of the instruction. |
| 566 |
|
|
* |
| 567 |
|
|
* If running is 0, things that depend on the runtime environment (eg. |
| 568 |
|
|
* register contents) will not be shown, and addr will be used instead of |
| 569 |
|
|
* cpu->pc for relative addresses. |
| 570 |
|
|
*/ |
| 571 |
|
|
int sh_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr, |
| 572 |
dpavlin |
24 |
int running, uint64_t dumpaddr) |
| 573 |
dpavlin |
14 |
{ |
| 574 |
dpavlin |
22 |
uint64_t offset; |
| 575 |
dpavlin |
14 |
uint32_t iword; |
| 576 |
dpavlin |
22 |
char *symbol; |
| 577 |
dpavlin |
14 |
|
| 578 |
|
|
if (running) |
| 579 |
|
|
dumpaddr = cpu->pc; |
| 580 |
|
|
|
| 581 |
|
|
symbol = get_symbol_name(&cpu->machine->symbol_context, |
| 582 |
|
|
dumpaddr, &offset); |
| 583 |
|
|
if (symbol != NULL && offset==0) |
| 584 |
|
|
debug("<%s>\n", symbol); |
| 585 |
|
|
|
| 586 |
|
|
if (cpu->machine->ncpus > 1 && running) |
| 587 |
|
|
debug("cpu%i: ", cpu->cpu_id); |
| 588 |
|
|
|
| 589 |
|
|
if (cpu->cd.sh.bits == 32) |
| 590 |
|
|
debug("%08x", (int)dumpaddr); |
| 591 |
|
|
else |
| 592 |
|
|
debug("%016llx", (long long)dumpaddr); |
| 593 |
|
|
|
| 594 |
|
|
if (cpu->cd.sh.compact) |
| 595 |
|
|
return sh_cpu_disassemble_instr_compact(cpu, instr, |
| 596 |
dpavlin |
24 |
running, dumpaddr); |
| 597 |
dpavlin |
14 |
|
| 598 |
|
|
if (cpu->byte_order == EMUL_BIG_ENDIAN) |
| 599 |
|
|
iword = (instr[0] << 24) + (instr[1] << 16) + (instr[2] << 8) |
| 600 |
|
|
+ instr[3]; |
| 601 |
|
|
else |
| 602 |
|
|
iword = (instr[3] << 24) + (instr[2] << 16) + (instr[1] << 8) |
| 603 |
|
|
+ instr[0]; |
| 604 |
|
|
|
| 605 |
|
|
debug(": %08x\t", iword); |
| 606 |
|
|
|
| 607 |
|
|
/* |
| 608 |
|
|
* Decode the instruction: |
| 609 |
|
|
*/ |
| 610 |
|
|
|
| 611 |
|
|
debug("TODO\n"); |
| 612 |
|
|
|
| 613 |
|
|
return sizeof(iword); |
| 614 |
|
|
} |
| 615 |
|
|
|
| 616 |
|
|
|
| 617 |
|
|
#include "tmp_sh_tail.c" |
| 618 |
|
|
|
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| 
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