/[gxemul]/trunk/src/cpus/cpu_run.c
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Annotation of /trunk/src/cpus/cpu_run.c

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Mon Oct 8 16:19:37 2007 UTC (16 years, 6 months ago) by dpavlin
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++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1121 2006/02/18 21:03:08 debug Exp $
20051126	Cobalt and PReP now work with the 21143 NIC.
		Continuing on Alpha dyntrans things.
		Fixing some more left-shift-by-24 to unsigned.
20051127	Working on OpenFirmware emulation; major cleanup/redesign.
		Progress on MacPPC emulation: NetBSD detects two CPUs (when
		running with -n 2), framebuffer output (for text) works.
		Adding quick-hack Bandit PCI controller and "gc" interrupt
		controller for MacPPC.
20051128	Changing from a Bandit to a Uni-North controller for macppc.
		Continuing on OpenFirmware and MacPPC emulation in general
		(obio controller, and wdc attached to the obio seems to work).
20051129	More work on MacPPC emulation (adding a dummy ADB controller).
		Continuing the PCI bus cleanup (endianness and tag composition)
		and rewriting all PCI controllers' access functions.
20051130	Various minor PPC dyntrans optimizations.
		Manually inlining some parts of the framebuffer redraw routine.
		Slowly beginning the conversion of the old MIPS emulation into
		dyntrans (but this will take quite some time to get right).
		Generalizing quick_pc_to_pointers.
20051201	Documentation update (David Muse has made available a kernel
		which simplifies Debian/DECstation installation).
		Continuing on the ADB bus controller.
20051202	Beginning a rewrite of the Zilog serial controller (dev_zs).
20051203	Continuing on the zs rewrite (now called dev_z8530); conversion
		to devinit style.
		Reworking some of the input-only vs output-only vs input-output
		details of src/console.c, better warning messages, and adding
		a debug dump.
		Removing the concept of "device state"; it wasn't really used.
		Changing some debug output (-vv should now be used to show all
		details about devices and busses; not shown during normal
		startup anymore).
		Beginning on some SPARC instruction disassembly support.
20051204	Minor PPC updates (WALNUT skeleton stuff).
		Continuing on the MIPS dyntrans rewrite.
		More progress on the ADB controller (a keyboard is "detected"
		by NetBSD and OpenBSD).
		Downgrading OpenBSD/arc as a guest OS from "working" to
		"almost working" in the documentation.
		Progress on Algor emulation ("v3" PCI controller).
20051205	Minor updates.
20051207	Sorting devices according to address; this reduces complexity
		of device lookups from O(n) to O(log n) in memory_rw (but no
		real performance increase (yet) in experiments).
20051210	Beginning the work on native dyntrans backends (by making a
		simple skeleton; so far only for Alpha hosts).
20051211	Some very minor SPARC updates.
20051215	Fixing a bug in the MIPS mul (note: not mult) instruction,
		so it also works with non-64-bit emulation. (Thanks to Alec
		Voropay for noticing the problem.)
20051216	More work on the fake/empty/simple/skeleton/whatever backend;
		performance doesn't increase, so this isn't really worth it,
		but it was probably worth it to prepare for a real backend
		later.
20051219	More instr call statistics gathering and analysis stuff.
20051220	Another fix for MIPS 'mul'. Also converting mul and {d,}cl{o,z}
		to dyntrans.
		memory_ppc.c syntax error fix (noticed by Peter Valchev).
		Beginning to move out machines from src/machine.c into
		individual files in src/machines (in a way similar to the
		autodev system for devices).
20051222	Updating the documentation regarding NetBSD/pmax 3.0.
20051223	- " - NetBSD/cats 3.0.
20051225	- " - NetBSD/hpcmips 3.0.
20051226	Continuing on the machine registry redesign.
		Adding support for ARM rrx (33-bit rotate).
		Fixing some signed/unsigned issues (exposed by gcc -W).
20051227	Fixing the bug which prevented a NetBSD/prep 3.0 install kernel
		from starting (triggered when an mtmsr was the last instruction
		on a page). Unfortunately not enough to get the kernel to run
		as well as the 2.1 kernels did.
20051230	Some dyntrans refactoring.
20051231	Continuing on the machine registry redesign.
20060101-10	Continuing... moving more machines. Moving MD interrupt stuff
		from machine.c into a new src/machines/interrupts.c.
20060114	Adding various mvmeppc machine skeletons.
20060115	Continuing on mvme* stuff. NetBSD/mvmeppc prints boot messages
		(for MVME1600) and reaches the root device prompt, but no
		specific hardware devices are emulated yet.
20060116	Minor updates to the mvme1600 emulation mode; the Eagle PCI bus
		seems to work without much modification, and a 21143 can be
		detected, interrupts might work (but untested so far).
		Adding a fake MK48Txx (mkclock) device, for NetBSD/mvmeppc.
20060121	Adding an aux control register for ARM. (A BIG thank you to
		Olivier Houchard for tracking down this bug.)
20060122	Adding more ARM instructions (smulXY), and dev_iq80321_7seg.
20060124	Adding disassembly of more ARM instructions (mia*, mra/mar),
		and some semi-bogus XScale and i80321 registers.
20060201-02	Various minor updates. Moving the last machines out of
		machine.c.
20060204	Adding a -c command line option, for running debugger commands
		before the simulation starts, but after all files have been
		loaded.
		Minor iq80321-related updates.
20060209	Minor hacks (DEVINIT macro, etc).
		Preparing for the generalization of the 64-bit dyntrans address
		translation subsystem.
20060216	Adding ARM ldrd (double-register load).
20060217	Continuing on various ARM-related stuff.
20060218	More progress on the ATA/wdc emulation for NetBSD/iq80321.
		NetBSD/evbarm can now be installed :-)  Updating the docs, etc.
		Continuing on Algor emulation.

==============  RELEASE 0.3.8  ==============
1 dpavlin 14 /*
2     * Copyright (C) 2005 Anders Gavare. All rights reserved.
3     *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 22 * $Id: cpu_run.c,v 1.6 2005/12/26 12:32:10 debug Exp $
29 dpavlin 14 *
30     * Included from cpu_mips.c, cpu_ppc.c etc. (The reason for this is that
31     * the call to a specific cpu's routine that runs one instruction will
32     * be inlined from here.)
33     *
34 dpavlin 22 * TODO: Rewrite/cleanup. This is too ugly and inefficient! Also, the
35     * dyntrans stuff doesn't require this kind of complexity, it can be a
36     * lot simpler.
37 dpavlin 14 */
38    
39     #include "console.h"
40     #include "debugger.h"
41    
42    
43     static int instrs_per_cycle(struct cpu *cpu) {
44     #ifdef CPU_RUN_MIPS
45     return cpu->cd.mips.cpu_type.instrs_per_cycle;
46     #else
47     return 1;
48     #endif
49     }
50    
51    
52     /*
53     * CPU_RUN():
54     *
55     * Run instructions on all CPUs in this machine, for a "medium duration"
56     * (or until all CPUs have halted).
57     *
58     * Return value is 1 if anything happened, 0 if all CPUs are stopped.
59     */
60     int CPU_RUN(struct emul *emul, struct machine *machine)
61     {
62     struct cpu **cpus = machine->cpus;
63     int ncpus = machine->ncpus;
64     int64_t max_instructions_cached = machine->max_instructions;
65     int64_t max_random_cycles_per_chunk_cached =
66     machine->max_random_cycles_per_chunk;
67     int64_t ncycles_chunk_end;
68     int running, rounds;
69    
70     /* The main loop: */
71     running = 1;
72     rounds = 0;
73     while (running || single_step) {
74     ncycles_chunk_end = machine->ncycles + (1 << 17);
75    
76     machine->a_few_instrs = machine->a_few_cycles *
77     instrs_per_cycle(cpus[0]);
78    
79     /* Do a chunk of cycles: */
80     do {
81     int i, j, te, cpu0instrs, a_few_instrs2;
82    
83     running = 0;
84     cpu0instrs = 0;
85    
86     /*
87     * Run instructions from each CPU:
88     */
89    
90     /* Is any cpu alive? */
91     for (i=0; i<ncpus; i++)
92     if (cpus[i]->running)
93     running = 1;
94    
95     if (single_step) {
96     if (single_step == 1) {
97     /*
98     * TODO: (Important!)
99     *
100     * If these are enabled, and focus is
101     * shifted to another machine in the
102     * debugger, then the wrong machine
103     * gets its variables restored!
104     */
105     old_instruction_trace =
106     machine->instruction_trace;
107     old_quiet_mode = quiet_mode;
108     old_show_trace_tree =
109     machine->show_trace_tree;
110     machine->instruction_trace = 1;
111     machine->show_trace_tree = 1;
112     quiet_mode = 0;
113     single_step = 2;
114     }
115    
116     for (j=0; j<instrs_per_cycle(cpus[0]); j++) {
117     if (single_step)
118     debugger();
119     for (i=0; i<ncpus; i++)
120     if (cpus[i]->running) {
121     int instrs_run =
122     CPU_RINSTR(emul,
123     cpus[i]);
124     if (i == 0)
125     cpu0instrs +=
126     instrs_run;
127     }
128     }
129     } else if (max_random_cycles_per_chunk_cached > 0) {
130     for (i=0; i<ncpus; i++)
131     if (cpus[i]->running && !single_step) {
132     a_few_instrs2 = machine->
133     a_few_cycles;
134     if (a_few_instrs2 >=
135     max_random_cycles_per_chunk_cached)
136     a_few_instrs2 = max_random_cycles_per_chunk_cached;
137     j = (random() % a_few_instrs2) + 1;
138     j *= instrs_per_cycle(cpus[i]);
139     while (j-- >= 1 && cpus[i]->running) {
140     int instrs_run = CPU_RINSTR(emul, cpus[i]);
141     if (i == 0)
142     cpu0instrs += instrs_run;
143     if (single_step)
144     break;
145     }
146     }
147     } else {
148     /* CPU 0 is special, cpu0instr must be updated. */
149     for (j=0; j<machine->a_few_instrs; ) {
150     int instrs_run;
151     if (!cpus[0]->running || single_step)
152     break;
153     do {
154     instrs_run =
155     CPU_RINSTR(emul, cpus[0]);
156     if (instrs_run == 0 ||
157     single_step) {
158     j = machine->a_few_instrs;
159     break;
160     }
161     } while (instrs_run == 0);
162     j += instrs_run;
163     cpu0instrs += instrs_run;
164     }
165    
166     /* CPU 1 and up: */
167     for (i=1; i<ncpus; i++) {
168     a_few_instrs2 = machine->a_few_cycles *
169     instrs_per_cycle(cpus[i]);
170     for (j=0; j<a_few_instrs2; )
171     if (cpus[i]->running) {
172     int instrs_run = 0;
173     while (!instrs_run) {
174     instrs_run = CPU_RINSTR(emul, cpus[i]);
175     if (instrs_run == 0 ||
176     single_step) {
177     j = a_few_instrs2;
178     break;
179     }
180     }
181     j += instrs_run;
182     } else
183     break;
184     }
185     }
186    
187     /*
188     * Hardware 'ticks': (clocks, interrupt sources...)
189     *
190     * Here, cpu0instrs is the number of instructions
191     * executed on cpu0. (TODO: don't use cpu 0 for this,
192     * use some kind of "mainbus" instead.) Hardware
193     * ticks are not per instruction, but per cycle,
194     * so we divide by the number of
195     * instructions_per_cycle for cpu0.
196     *
197     * TODO: This doesn't work in a machine with, say,
198     * a mixture of R3000, R4000, and R10000 CPUs, if
199     * there ever was such a thing.
200     *
201     * TODO 2: A small bug occurs if cpu0instrs isn't
202     * evenly divisible by instrs_per_cycle. We then
203     * cause hardware ticks a fraction of a cycle too
204     * often.
205     */
206     i = instrs_per_cycle(cpus[0]);
207     switch (i) {
208     case 1: break;
209     case 2: cpu0instrs >>= 1; break;
210     case 4: cpu0instrs >>= 2; break;
211     default:
212     cpu0instrs /= i;
213     }
214    
215     for (te=0; te<machine->n_tick_entries; te++) {
216     machine->ticks_till_next[te] -= cpu0instrs;
217    
218     if (machine->ticks_till_next[te] <= 0) {
219     while (machine->ticks_till_next[te]
220     <= 0)
221     machine->ticks_till_next[te] +=
222     machine->
223     ticks_reset_value[te];
224     machine->tick_func[te](cpus[0],
225     machine->tick_extra[te]);
226     }
227     }
228    
229     /* Any CPU dead? */
230     for (i=0; i<ncpus; i++) {
231     if (cpus[i]->dead && machine->
232     exit_without_entering_debugger == 0)
233     single_step = 1;
234     }
235    
236     machine->ncycles += cpu0instrs;
237     } while (running && (machine->ncycles < ncycles_chunk_end));
238    
239     /* If we've done buffered console output,
240     the flush stdout every now and then: */
241     if (machine->ncycles > machine->ncycles_flush + (1<<17)) {
242     console_flush();
243     machine->ncycles_flush = machine->ncycles;
244     }
245    
246     if (machine->ncycles > machine->ncycles_show + (1<<25)) {
247     machine->ncycles_since_gettimeofday +=
248     (machine->ncycles - machine->ncycles_show);
249     cpu_show_cycles(machine, 0);
250     machine->ncycles_show = machine->ncycles;
251     }
252    
253     if (max_instructions_cached != 0 &&
254     machine->ncycles >= max_instructions_cached)
255     running = 0;
256    
257     /* Let's allow other machines to run. */
258     rounds ++;
259     if (rounds > 2)
260     break;
261     }
262    
263     return running;
264     }
265    
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