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dpavlin |
32 |
/* |
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dpavlin |
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* Copyright (C) 2006-2007 Anders Gavare. All rights reserved. |
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dpavlin |
32 |
* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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dpavlin |
34 |
* $Id: cpu_rca180x.c,v 1.4 2006/12/30 13:30:55 debug Exp $ |
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dpavlin |
32 |
* |
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* RCA180X CPU emulation. |
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* |
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* See http://www.elf-emulation.com/1802.html for a good list of 1802/1805 |
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* opcodes. |
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*/ |
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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#include <ctype.h> |
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#include "cpu.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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#include "settings.h" |
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#include "symbol.h" |
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#include "timer.h" |
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#define DYNTRANS_32 |
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#include "tmp_rca180x_head.c" |
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static void rca180x_timer_tick(struct timer *timer, void *extra) |
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{ |
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struct cpu *cpu = (struct cpu *) extra; |
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int dec = 3; |
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if (cpu->cd.rca180x.timer_mode_new) |
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dec = 1; |
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if (cpu->cd.rca180x.delay_timer_value > 0) |
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cpu->cd.rca180x.delay_timer_value -= dec; |
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if (cpu->cd.rca180x.sound_timer_value > 0) |
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cpu->cd.rca180x.sound_timer_value -= dec; |
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if (cpu->cd.rca180x.delay_timer_value < 0) |
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cpu->cd.rca180x.delay_timer_value = 0; |
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if (cpu->cd.rca180x.sound_timer_value < 0) |
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cpu->cd.rca180x.sound_timer_value = 0; |
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} |
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/* |
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* rca180x_cpu_new(): |
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* |
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* Create a new RCA180X cpu object. |
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* |
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* Returns 1 on success, 0 if there was no matching RCA180X processor with |
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* this cpu_type_name. |
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*/ |
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dpavlin |
34 |
int rca180x_cpu_new(struct cpu *cpu, struct memory *mem, |
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struct machine *machine, int cpu_id, char *cpu_type_name) |
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dpavlin |
32 |
{ |
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int i; |
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if (strcasecmp(cpu_type_name, "RCA1802") != 0) |
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return 0; |
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/* TODO: RCA1805 etc */ |
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cpu->run_instr = rca180x_run_instr; |
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cpu->memory_rw = rca180x_memory_rw; |
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cpu->update_translation_table = rca180x_update_translation_table; |
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cpu->invalidate_translation_caches = |
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rca180x_invalidate_translation_caches; |
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cpu->invalidate_code_translation = rca180x_invalidate_code_translation; |
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cpu->is_32bit = 1; |
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cpu->byte_order = EMUL_BIG_ENDIAN; |
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/* |
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* CHIP8 emulation: |
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*/ |
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cpu->cd.rca180x.sp = 0xff0; |
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cpu->cd.rca180x.xres = 64; |
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cpu->cd.rca180x.yres = 32; |
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cpu->cd.rca180x.framebuffer_cache = malloc(cpu->cd.rca180x.xres * |
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cpu->cd.rca180x.yres); |
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if (cpu->cd.rca180x.framebuffer_cache == NULL) { |
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fprintf(stderr, "Out of memory.\n"); |
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exit(1); |
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} |
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memset(cpu->cd.rca180x.framebuffer_cache, 0, cpu->cd.rca180x.xres * |
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cpu->cd.rca180x.yres); |
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/* 18.2 Hz for original CHIP8, 60 Hz for new. */ |
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cpu->cd.rca180x.timer_mode_new = 1; |
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cpu->cd.rca180x.timer = timer_add( |
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cpu->cd.rca180x.timer_mode_new? 60.0 : 18.2, |
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rca180x_timer_tick, cpu); |
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/* Only show name and caches etc for CPU nr 0 (in SMP machines): */ |
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if (cpu_id == 0) { |
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debug("%s", cpu->name); |
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} |
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/* Add all register names to the settings: */ |
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CPU_SETTINGS_ADD_REGISTER64("pc", cpu->pc); |
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CPU_SETTINGS_ADD_REGISTER16("index", cpu->cd.rca180x.index); |
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CPU_SETTINGS_ADD_REGISTER16("sp", cpu->cd.rca180x.sp); |
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CPU_SETTINGS_ADD_REGISTER8("d", cpu->cd.rca180x.d); |
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CPU_SETTINGS_ADD_REGISTER8("df", cpu->cd.rca180x.df); |
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CPU_SETTINGS_ADD_REGISTER8("ie", cpu->cd.rca180x.ie); |
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CPU_SETTINGS_ADD_REGISTER8("p", cpu->cd.rca180x.p); |
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CPU_SETTINGS_ADD_REGISTER8("q", cpu->cd.rca180x.q); |
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CPU_SETTINGS_ADD_REGISTER8("x", cpu->cd.rca180x.x); |
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CPU_SETTINGS_ADD_REGISTER8("t_p", cpu->cd.rca180x.t_p); |
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CPU_SETTINGS_ADD_REGISTER8("t_x", cpu->cd.rca180x.t_x); |
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CPU_SETTINGS_ADD_REGISTER8("chip8_mode", cpu->cd.rca180x.chip8_mode); |
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for (i=0; i<N_RCA180X_REGS; i++) { |
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char tmpstr[5]; |
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snprintf(tmpstr, sizeof(tmpstr), "r%x", i); |
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CPU_SETTINGS_ADD_REGISTER16(tmpstr, cpu->cd.rca180x.r[i]); |
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} |
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for (i=0; i<N_CHIP8_REGS; i++) { |
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char tmpstr[5]; |
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snprintf(tmpstr, sizeof(tmpstr), "v%x", i); |
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CPU_SETTINGS_ADD_REGISTER8(tmpstr, cpu->cd.rca180x.v[i]); |
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} |
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return 1; |
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} |
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/* |
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* rca180x_cpu_list_available_types(): |
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* |
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* Print a list of available RCA180X CPU types. |
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*/ |
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void rca180x_cpu_list_available_types(void) |
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{ |
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/* TODO: RCA1805... */ |
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debug("RCA1802\n"); |
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} |
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/* |
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* rca180x_cpu_dumpinfo(): |
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*/ |
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void rca180x_cpu_dumpinfo(struct cpu *cpu) |
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{ |
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debug("\n"); |
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} |
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| 180 |
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/* |
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* rca180x_cpu_register_dump(): |
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* |
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* Dump cpu registers in a relatively readable format. |
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* |
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* gprs: set to non-zero to dump GPRs and some special-purpose registers. |
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* coprocs: set bit 0..3 to dump registers in coproc 0..3. |
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*/ |
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void rca180x_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs) |
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{ |
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char *symbol; |
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uint64_t offset; |
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int i, x = cpu->cpu_id; |
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if (gprs) { |
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/* Special registers (pc, ...) first: */ |
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symbol = get_symbol_name(&cpu->machine->symbol_context, |
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cpu->pc, &offset); |
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debug("cpu%i: pc=0x%x", x, (int)cpu->pc); |
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debug(" <%s>\n", symbol != NULL? symbol : " no symbol "); |
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for (i=0; i<N_RCA180X_REGS; i++) { |
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if ((i % 4) == 0) |
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debug("cpu%i:", x); |
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debug(" r%x = 0x%04x", i, cpu->cd.rca180x.r[i]); |
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if ((i % 4) == 3) |
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debug("\n"); |
| 208 |
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} |
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debug("cpu%i: d=0x%02x df=%i ie=%i q=%i p=0x%x x=0x%x t_p=0x%x " |
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"t_x=0x%x chip8_mode=%i\n", x, |
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cpu->cd.rca180x.d, cpu->cd.rca180x.df, |
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cpu->cd.rca180x.ie, cpu->cd.rca180x.q, cpu->cd.rca180x.p, |
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cpu->cd.rca180x.x, cpu->cd.rca180x.t_p, cpu->cd.rca180x.t_x, |
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cpu->cd.rca180x.chip8_mode); |
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if (cpu->cd.rca180x.chip8_mode) { |
| 218 |
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for (i=0; i<N_CHIP8_REGS; i++) { |
| 219 |
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if ((i % 8) == 0) |
| 220 |
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debug("cpu%i:", x); |
| 221 |
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debug(" v%x=0x%02x", i, cpu->cd.rca180x.v[i]); |
| 222 |
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if ((i % 8) == 7) |
| 223 |
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debug("\n"); |
| 224 |
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} |
| 225 |
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| 226 |
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debug("cpu%i: i=0x%04x sp=0x%03x delay=%i sound=%i\n", |
| 227 |
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x, cpu->cd.rca180x.index, cpu->cd.rca180x.sp, |
| 228 |
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cpu->cd.rca180x.delay_timer_value, |
| 229 |
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cpu->cd.rca180x.sound_timer_value); |
| 230 |
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} |
| 231 |
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} |
| 232 |
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} |
| 233 |
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| 234 |
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| 235 |
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/* |
| 236 |
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* rca180x_cpu_tlbdump(): |
| 237 |
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* |
| 238 |
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* Called from the debugger to dump the TLB in a readable format. |
| 239 |
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* x is the cpu number to dump, or -1 to dump all CPUs. |
| 240 |
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* |
| 241 |
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* If rawflag is nonzero, then the TLB contents isn't formated nicely, |
| 242 |
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* just dumped. |
| 243 |
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*/ |
| 244 |
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void rca180x_cpu_tlbdump(struct machine *m, int x, int rawflag) |
| 245 |
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{ |
| 246 |
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} |
| 247 |
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| 248 |
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| 249 |
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/* |
| 250 |
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* rca180x_cpu_gdb_stub(): |
| 251 |
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* |
| 252 |
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* Execute a "remote GDB" command. Returns a newly allocated response string |
| 253 |
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* on success, NULL on failure. |
| 254 |
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*/ |
| 255 |
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char *rca180x_cpu_gdb_stub(struct cpu *cpu, char *cmd) |
| 256 |
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{ |
| 257 |
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fatal("rca180x_cpu_gdb_stub(): TODO\n"); |
| 258 |
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return NULL; |
| 259 |
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} |
| 260 |
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| 261 |
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| 262 |
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/* |
| 263 |
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* rca180x_cpu_interrupt(): |
| 264 |
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*/ |
| 265 |
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int rca180x_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr) |
| 266 |
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{ |
| 267 |
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fatal("rca180x_cpu_interrupt(): TODO\n"); |
| 268 |
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return 0; |
| 269 |
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} |
| 270 |
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| 271 |
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| 272 |
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/* |
| 273 |
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* rca180x_cpu_interrupt_ack(): |
| 274 |
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*/ |
| 275 |
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int rca180x_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr) |
| 276 |
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{ |
| 277 |
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/* fatal("rca180x_cpu_interrupt_ack(): TODO\n"); */ |
| 278 |
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return 0; |
| 279 |
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} |
| 280 |
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| 281 |
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| 282 |
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/* |
| 283 |
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* chip8_cpu_disassemble_instr(): |
| 284 |
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* |
| 285 |
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* Convert an instruction word into human readable format, for instruction |
| 286 |
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* tracing and disassembly. |
| 287 |
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* |
| 288 |
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* If running is 1, cpu->pc should be the address of the instruction. |
| 289 |
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* |
| 290 |
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* If running is 0, things that depend on the runtime environment (eg. |
| 291 |
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* register contents) will not be shown, and addr will be used instead of |
| 292 |
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* cpu->pc for relative addresses. |
| 293 |
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*/ |
| 294 |
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int chip8_cpu_disassemble_instr(struct cpu *cpu, unsigned char *ib, |
| 295 |
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int running, uint64_t dumpaddr) |
| 296 |
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{ |
| 297 |
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uint64_t offset; |
| 298 |
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char *symbol, *mnem; |
| 299 |
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int no_y; |
| 300 |
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| 301 |
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if (running) |
| 302 |
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dumpaddr = cpu->pc; |
| 303 |
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| 304 |
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symbol = get_symbol_name(&cpu->machine->symbol_context, |
| 305 |
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dumpaddr, &offset); |
| 306 |
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if (symbol != NULL && offset==0) |
| 307 |
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debug("<%s>\n", symbol); |
| 308 |
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| 309 |
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if (cpu->machine->ncpus > 1 && running) |
| 310 |
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debug("cpu%i: ", cpu->cpu_id); |
| 311 |
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| 312 |
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debug("0x%04x: %02x%02x\t", (int)dumpaddr, ib[0], ib[1]); |
| 313 |
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| 314 |
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switch (ib[0] >> 4) { |
| 315 |
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| 316 |
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case 0x0: |
| 317 |
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switch(ib[0] & 0xf) { |
| 318 |
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case 0x0: |
| 319 |
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switch(ib[1] >> 4) { |
| 320 |
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case 0xc: |
| 321 |
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debug("scdown\t%i\n", ib[1] & 0xf); |
| 322 |
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break; |
| 323 |
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case 0xe: |
| 324 |
|
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switch(ib[1] & 0xf) { |
| 325 |
|
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case 0x0: |
| 326 |
|
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debug("cls"); |
| 327 |
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break; |
| 328 |
|
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case 0xe: |
| 329 |
|
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debug("rts"); |
| 330 |
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break; |
| 331 |
|
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default:debug("UNIMPLEMENTED"); |
| 332 |
|
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} |
| 333 |
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break; |
| 334 |
|
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case 0xf: |
| 335 |
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switch(ib[1] & 0xf) { |
| 336 |
|
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case 0xb: |
| 337 |
|
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debug("scright"); |
| 338 |
|
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break; |
| 339 |
|
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case 0xc: |
| 340 |
|
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debug("scleft"); |
| 341 |
|
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break; |
| 342 |
|
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case 0xe: |
| 343 |
|
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debug("low"); |
| 344 |
|
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break; |
| 345 |
|
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case 0xf: |
| 346 |
|
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debug("high"); |
| 347 |
|
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break; |
| 348 |
|
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default:debug("UNIMPLEMENTED"); |
| 349 |
|
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} |
| 350 |
|
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break; |
| 351 |
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|
| 352 |
|
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default:debug("UNIMPLEMENTED"); |
| 353 |
|
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} |
| 354 |
|
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break; |
| 355 |
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|
| 356 |
|
|
default:debug("call\t0x%04x", (ib[0] << 8) + ib[1]); |
| 357 |
|
|
} |
| 358 |
|
|
break; |
| 359 |
|
|
|
| 360 |
|
|
case 0x1: |
| 361 |
|
|
case 0x2: |
| 362 |
|
|
debug("%s\t0x%03x", |
| 363 |
|
|
(ib[0] >> 4) == 0x1? "jmp" : "jsr", |
| 364 |
|
|
((ib[0] & 0xf) << 8) + ib[1]); |
| 365 |
|
|
break; |
| 366 |
|
|
|
| 367 |
|
|
case 0x3: |
| 368 |
|
|
case 0x4: |
| 369 |
|
|
debug("%s\tv%x, 0x%02x", |
| 370 |
|
|
(ib[0] >> 4) == 0x3? "skeq" : "skne", |
| 371 |
|
|
ib[0] & 0xf, ib[1]); |
| 372 |
|
|
break; |
| 373 |
|
|
|
| 374 |
|
|
case 0x5: |
| 375 |
|
|
if ((ib[1] & 0xf) == 0) |
| 376 |
|
|
debug("skeq\tv%x, v%x", ib[0] & 0xf, ib[1] >> 4); |
| 377 |
|
|
else |
| 378 |
|
|
debug("UNIMPLEMENTED (skeq, but low nibble non-zero)"); |
| 379 |
|
|
break; |
| 380 |
|
|
|
| 381 |
|
|
case 0x6: |
| 382 |
|
|
case 0x7: |
| 383 |
|
|
debug("%s\tv%x, 0x%02x", |
| 384 |
|
|
(ib[0] >> 4) == 0x6? "mov" : "add", |
| 385 |
|
|
ib[0] & 0xf, ib[1]); |
| 386 |
|
|
break; |
| 387 |
|
|
|
| 388 |
|
|
case 0x8: |
| 389 |
|
|
mnem = "UNIMPLEMENTED"; |
| 390 |
|
|
no_y = 0; |
| 391 |
|
|
|
| 392 |
|
|
switch (ib[1] & 0xf) { |
| 393 |
|
|
case 0: mnem = "mov"; break; |
| 394 |
|
|
case 1: mnem = "or"; break; |
| 395 |
|
|
case 2: mnem = "and"; break; |
| 396 |
|
|
case 3: mnem = "xor"; break; |
| 397 |
|
|
case 4: mnem = "add"; break; |
| 398 |
|
|
case 5: mnem = "sub"; break; |
| 399 |
|
|
case 6: mnem = "shr"; no_y = 1; break; |
| 400 |
|
|
case 7: mnem = "rsb"; break; |
| 401 |
|
|
case 14: mnem = "shl"; no_y = 1; break; |
| 402 |
|
|
} |
| 403 |
|
|
|
| 404 |
|
|
debug("%s\tv%x", mnem, ib[0] & 0xf); |
| 405 |
|
|
if (!no_y) |
| 406 |
|
|
debug(", v%x", ib[1] >> 4); |
| 407 |
|
|
break; |
| 408 |
|
|
|
| 409 |
|
|
case 0x9: |
| 410 |
|
|
if ((ib[1] & 0xf) == 0) |
| 411 |
|
|
debug("skne\tv%x, v%x", ib[0] & 0xf, ib[1] >> 4); |
| 412 |
|
|
else |
| 413 |
|
|
debug("UNIMPLEMENTED (skne, but low nibble non-zero)"); |
| 414 |
|
|
break; |
| 415 |
|
|
|
| 416 |
|
|
case 0xa: |
| 417 |
|
|
case 0xb: |
| 418 |
|
|
debug("%s\t0x%03x", |
| 419 |
|
|
(ib[0] >> 4) == 0xa? "mvi" : "jmi", |
| 420 |
|
|
((ib[0] & 0xf) << 8) + ib[1]); |
| 421 |
|
|
break; |
| 422 |
|
|
|
| 423 |
|
|
case 0xc: |
| 424 |
|
|
debug("rand\tv%x, 0x%02x", ib[0] & 0xf, ib[1]); |
| 425 |
|
|
break; |
| 426 |
|
|
|
| 427 |
|
|
case 0xd: |
| 428 |
|
|
if ((ib[1] & 0xf) == 0) |
| 429 |
|
|
debug("xsprite\tv%x, v%x", |
| 430 |
|
|
ib[0] & 0xf, ib[1] >> 4); |
| 431 |
|
|
else |
| 432 |
|
|
debug("sprite\tv%x, v%x, %i", |
| 433 |
|
|
ib[0] & 0xf, ib[1] >> 4, ib[1] & 0xf); |
| 434 |
|
|
break; |
| 435 |
|
|
|
| 436 |
|
|
case 0xe: |
| 437 |
|
|
switch (ib[1]) { |
| 438 |
|
|
case 0x9e: |
| 439 |
|
|
case 0xa1: |
| 440 |
|
|
debug("%s\t%x", |
| 441 |
|
|
ib[1] == 0x9e? "skpr" : "skup", ib[0] & 0xf); |
| 442 |
|
|
break; |
| 443 |
|
|
default:debug("UNIMPLEMENTED"); |
| 444 |
|
|
} |
| 445 |
|
|
break; |
| 446 |
|
|
|
| 447 |
|
|
case 0xf: |
| 448 |
|
|
switch (ib[1]) { |
| 449 |
|
|
case 0x07: |
| 450 |
|
|
case 0x0a: |
| 451 |
|
|
case 0x15: |
| 452 |
|
|
case 0x18: |
| 453 |
|
|
case 0x1e: |
| 454 |
|
|
case 0x29: |
| 455 |
|
|
case 0x30: |
| 456 |
|
|
case 0x33: |
| 457 |
|
|
mnem = NULL; |
| 458 |
|
|
switch (ib[1]) { |
| 459 |
|
|
case 0x07: mnem = "gdelay"; break; |
| 460 |
|
|
case 0x0a: mnem = "key"; break; |
| 461 |
|
|
case 0x15: mnem = "sdelay"; break; |
| 462 |
|
|
case 0x18: mnem = "ssound"; break; |
| 463 |
|
|
case 0x1e: mnem = "adi"; break; |
| 464 |
|
|
case 0x29: mnem = "font"; break; |
| 465 |
|
|
case 0x30: mnem = "xfont"; break; |
| 466 |
|
|
case 0x33: mnem = "bcd"; break; |
| 467 |
|
|
} |
| 468 |
|
|
debug("%s\tv%x", mnem, ib[0] & 0xf); |
| 469 |
|
|
break; |
| 470 |
|
|
case 0x55: |
| 471 |
|
|
case 0x65: |
| 472 |
|
|
mnem = NULL; |
| 473 |
|
|
switch (ib[1]) { |
| 474 |
|
|
case 0x55: mnem = "str"; break; |
| 475 |
|
|
case 0x65: mnem = "ldr"; break; |
| 476 |
|
|
} |
| 477 |
|
|
debug("%s\tv0-v%x", mnem, ib[0] & 0xf); |
| 478 |
|
|
break; |
| 479 |
|
|
default:debug("UNIMPLEMENTED"); |
| 480 |
|
|
} |
| 481 |
|
|
break; |
| 482 |
|
|
|
| 483 |
|
|
default:debug("UNIMPLEMENTED"); |
| 484 |
|
|
} |
| 485 |
|
|
|
| 486 |
|
|
debug("\n"); |
| 487 |
|
|
|
| 488 |
|
|
return sizeof(uint16_t); |
| 489 |
|
|
} |
| 490 |
|
|
|
| 491 |
|
|
|
| 492 |
|
|
/* |
| 493 |
|
|
* rca180x_cpu_disassemble_instr(): |
| 494 |
|
|
* |
| 495 |
|
|
* Convert an instruction word into human readable format, for instruction |
| 496 |
|
|
* tracing and disassembly. |
| 497 |
|
|
* |
| 498 |
|
|
* If running is 1, cpu->pc should be the address of the instruction. |
| 499 |
|
|
* |
| 500 |
|
|
* If running is 0, things that depend on the runtime environment (eg. |
| 501 |
|
|
* register contents) will not be shown, and addr will be used instead of |
| 502 |
|
|
* cpu->pc for relative addresses. |
| 503 |
|
|
*/ |
| 504 |
|
|
int rca180x_cpu_disassemble_instr(struct cpu *cpu, unsigned char *ib, |
| 505 |
|
|
int running, uint64_t dumpaddr) |
| 506 |
|
|
{ |
| 507 |
|
|
uint64_t offset; |
| 508 |
|
|
char *symbol, *mnem = NULL; |
| 509 |
|
|
int len, no_reg=0; |
| 510 |
|
|
|
| 511 |
|
|
if (cpu->cd.rca180x.chip8_mode) |
| 512 |
|
|
return chip8_cpu_disassemble_instr(cpu, ib, running, dumpaddr); |
| 513 |
|
|
|
| 514 |
|
|
if (running) |
| 515 |
|
|
dumpaddr = cpu->pc; |
| 516 |
|
|
|
| 517 |
|
|
symbol = get_symbol_name(&cpu->machine->symbol_context, |
| 518 |
|
|
dumpaddr, &offset); |
| 519 |
|
|
if (symbol != NULL && offset==0) |
| 520 |
|
|
debug("<%s>\n", symbol); |
| 521 |
|
|
|
| 522 |
|
|
if (cpu->machine->ncpus > 1 && running) |
| 523 |
|
|
debug("cpu%i: ", cpu->cpu_id); |
| 524 |
|
|
|
| 525 |
|
|
debug("0x%04x:\t%02x", (int)dumpaddr, ib[0]); |
| 526 |
|
|
len = 1; |
| 527 |
|
|
|
| 528 |
|
|
switch (ib[0] >> 4) { |
| 529 |
|
|
|
| 530 |
|
|
case 0x0: |
| 531 |
|
|
case 0x1: |
| 532 |
|
|
case 0x2: |
| 533 |
|
|
case 0x4: |
| 534 |
|
|
case 0x5: |
| 535 |
|
|
case 0x8: |
| 536 |
|
|
case 0x9: |
| 537 |
|
|
case 0xa: |
| 538 |
|
|
case 0xb: |
| 539 |
|
|
case 0xd: |
| 540 |
|
|
case 0xe: |
| 541 |
|
|
switch (ib[0] >> 4) { |
| 542 |
|
|
case 0x0: mnem = "ldn"; |
| 543 |
|
|
if (ib[0] == 0x00) { |
| 544 |
|
|
no_reg = 1; |
| 545 |
|
|
mnem = "idl"; |
| 546 |
|
|
} |
| 547 |
|
|
break; |
| 548 |
|
|
case 0x1: mnem = "inc"; break; |
| 549 |
|
|
case 0x2: mnem = "dec"; break; |
| 550 |
|
|
case 0x4: mnem = "lda"; break; |
| 551 |
|
|
case 0x5: mnem = "str"; break; |
| 552 |
|
|
case 0x8: mnem = "glo"; break; |
| 553 |
|
|
case 0x9: mnem = "ghi"; break; |
| 554 |
|
|
case 0xa: mnem = "plo"; break; |
| 555 |
|
|
case 0xb: mnem = "phi"; break; |
| 556 |
|
|
case 0xd: mnem = "sep"; break; |
| 557 |
|
|
case 0xe: mnem = "sex"; break; |
| 558 |
|
|
} |
| 559 |
|
|
debug("\t%s", mnem); |
| 560 |
|
|
if (!no_reg) |
| 561 |
|
|
debug("\tr%x", ib[0] & 0xf); |
| 562 |
|
|
break; |
| 563 |
|
|
|
| 564 |
|
|
case 0x3: |
| 565 |
|
|
len ++; |
| 566 |
|
|
debug("%02x\t", ib[1]); |
| 567 |
|
|
|
| 568 |
|
|
switch (ib[0] & 0xf) { |
| 569 |
|
|
case 0x0: debug("br"); break; |
| 570 |
|
|
case 0x1: debug("bq"); break; |
| 571 |
|
|
case 0x2: debug("bz"); break; |
| 572 |
|
|
case 0x3: debug("bdf"); break; |
| 573 |
|
|
case 0x4: debug("b1"); break; |
| 574 |
|
|
case 0x5: debug("b2"); break; |
| 575 |
|
|
case 0x6: debug("b3"); break; |
| 576 |
|
|
case 0x7: debug("b4"); break; |
| 577 |
|
|
case 0x8: debug("nbr"); break; |
| 578 |
|
|
case 0x9: debug("bnq"); break; |
| 579 |
|
|
case 0xa: debug("bnz"); break; |
| 580 |
|
|
case 0xb: debug("bnf"); break; |
| 581 |
|
|
case 0xc: debug("bn1"); break; |
| 582 |
|
|
case 0xd: debug("bn2"); break; |
| 583 |
|
|
case 0xe: debug("bn3"); break; |
| 584 |
|
|
case 0xf: debug("bn4"); break; |
| 585 |
|
|
} |
| 586 |
|
|
|
| 587 |
|
|
debug("\t0x%04x", ((dumpaddr + 1) & 0xff00) + ib[1]); |
| 588 |
|
|
break; |
| 589 |
|
|
|
| 590 |
|
|
case 0x6: |
| 591 |
|
|
switch (ib[0] & 0xf) { |
| 592 |
|
|
case 0x0: |
| 593 |
|
|
debug("\tirx"); |
| 594 |
|
|
break; |
| 595 |
|
|
case 0x8: |
| 596 |
|
|
debug("\tTODO: 1805 instruction!"); |
| 597 |
|
|
break; |
| 598 |
|
|
default: |
| 599 |
|
|
debug("\t%s%i", ib[0] & 8? "inp" : "out", ib[0] & 7); |
| 600 |
|
|
} |
| 601 |
|
|
break; |
| 602 |
|
|
|
| 603 |
|
|
case 0x7: |
| 604 |
|
|
switch (ib[0] & 0xf) { |
| 605 |
|
|
|
| 606 |
|
|
case 0x0: debug("\tret"); break; |
| 607 |
|
|
case 0x1: debug("\tdis"); break; |
| 608 |
|
|
case 0x2: debug("\tldxa"); break; |
| 609 |
|
|
case 0x3: debug("\tstxd"); break; |
| 610 |
|
|
case 0x4: debug("\tadc"); break; |
| 611 |
|
|
case 0x5: debug("\tsdb"); break; |
| 612 |
|
|
case 0x6: debug("\tshrc"); break; |
| 613 |
|
|
case 0x7: debug("\tsmb"); break; |
| 614 |
|
|
case 0x8: debug("\tsav"); break; |
| 615 |
|
|
case 0x9: debug("\tmark"); break; |
| 616 |
|
|
case 0xa: debug("\treq"); break; |
| 617 |
|
|
case 0xb: debug("\tseq"); break; |
| 618 |
|
|
case 0xe: debug("\tshlc"); break; |
| 619 |
|
|
|
| 620 |
|
|
default: |
| 621 |
|
|
switch (ib[0] & 0xf) { |
| 622 |
|
|
case 0xc: mnem = "adci"; break; |
| 623 |
|
|
case 0xd: mnem = "sdbi"; break; |
| 624 |
|
|
case 0xf: mnem = "smbi"; break; |
| 625 |
|
|
} |
| 626 |
|
|
len ++; |
| 627 |
|
|
debug("%02x\t%s\t0x%02x", ib[1], mnem, ib[1]); |
| 628 |
|
|
break; |
| 629 |
|
|
} |
| 630 |
|
|
break; |
| 631 |
|
|
|
| 632 |
|
|
case 0xc: |
| 633 |
|
|
len += 2; |
| 634 |
|
|
debug("%02x%02x\t", ib[1], ib[2]); |
| 635 |
|
|
|
| 636 |
|
|
switch (ib[0] & 0xf) { |
| 637 |
|
|
case 0x0: debug("lbr"); break; |
| 638 |
|
|
case 0x1: debug("lbq"); break; |
| 639 |
|
|
case 0x2: debug("lbz"); break; |
| 640 |
|
|
case 0x3: debug("lbdf"); break; |
| 641 |
|
|
case 0x4: debug("nop"); break; |
| 642 |
|
|
case 0x5: debug("lsnq"); break; |
| 643 |
|
|
case 0x6: debug("lsnz"); break; |
| 644 |
|
|
case 0x7: debug("lsnf"); break; |
| 645 |
|
|
case 0x8: debug("nlbr"); break; |
| 646 |
|
|
case 0x9: debug("lbnq"); break; |
| 647 |
|
|
case 0xa: debug("lbnz"); break; |
| 648 |
|
|
case 0xb: debug("lbnf"); break; |
| 649 |
|
|
case 0xc: debug("lsie"); break; |
| 650 |
|
|
case 0xd: debug("lsq"); break; |
| 651 |
|
|
case 0xe: debug("lsz"); break; |
| 652 |
|
|
case 0xf: debug("lsdf"); break; |
| 653 |
|
|
} |
| 654 |
|
|
|
| 655 |
|
|
debug("\t0x%02x%02x", ib[1], ib[2]); |
| 656 |
|
|
break; |
| 657 |
|
|
|
| 658 |
|
|
case 0xf: |
| 659 |
|
|
switch (ib[0] & 0xf) { |
| 660 |
|
|
|
| 661 |
|
|
case 0x0: debug("\tldx"); break; |
| 662 |
|
|
case 0x1: debug("\tor"); break; |
| 663 |
|
|
case 0x2: debug("\tand"); break; |
| 664 |
|
|
case 0x3: debug("\txor"); break; |
| 665 |
|
|
case 0x4: debug("\tadd"); break; |
| 666 |
|
|
case 0x5: debug("\tsb"); break; |
| 667 |
|
|
case 0x6: debug("\tshr"); break; |
| 668 |
|
|
case 0x7: debug("\tsm"); break; |
| 669 |
|
|
case 0xe: debug("\tshl"); break; |
| 670 |
|
|
|
| 671 |
|
|
default: |
| 672 |
|
|
switch (ib[0] & 0xf) { |
| 673 |
|
|
case 0x8: mnem = "ldi"; break; |
| 674 |
|
|
case 0x9: mnem = "ori"; break; |
| 675 |
|
|
case 0xa: mnem = "ani"; break; |
| 676 |
|
|
case 0xb: mnem = "xri"; break; |
| 677 |
|
|
case 0xc: mnem = "adi"; break; |
| 678 |
|
|
case 0xd: mnem = "sdi"; break; |
| 679 |
|
|
case 0xf: mnem = "smi"; break; |
| 680 |
|
|
} |
| 681 |
|
|
len ++; |
| 682 |
|
|
debug("%02x\t%s\t0x%02x", ib[1], mnem, ib[1]); |
| 683 |
|
|
break; |
| 684 |
|
|
} |
| 685 |
|
|
break; |
| 686 |
|
|
|
| 687 |
|
|
default:debug("\tUNIMPLEMENTED"); |
| 688 |
|
|
} |
| 689 |
|
|
|
| 690 |
|
|
debug("\n"); |
| 691 |
|
|
|
| 692 |
|
|
return len; |
| 693 |
|
|
} |
| 694 |
|
|
|
| 695 |
|
|
|
| 696 |
|
|
#include "tmp_rca180x_tail.c" |
| 697 |
|
|
|
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