25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: cpu_ppc_instr_loadstore.c,v 1.1 2005/08/29 14:36:41 debug Exp $ |
* $Id: cpu_ppc_instr_loadstore.c,v 1.6 2005/11/23 06:59:52 debug Exp $ |
29 |
* |
* |
30 |
* POWER/PowerPC load/store instructions. |
* POWER/PowerPC load/store instructions. |
31 |
* |
* |
52 |
#endif |
#endif |
53 |
unsigned char data[LS_SIZE]; |
unsigned char data[LS_SIZE]; |
54 |
|
|
55 |
|
/* Synchronize the PC: */ |
56 |
|
int low_pc = ((size_t)ic - (size_t)cpu->cd.ppc.cur_ic_page) |
57 |
|
/ sizeof(struct ppc_instr_call); |
58 |
|
cpu->pc &= ~((PPC_IC_ENTRIES_PER_PAGE-1) << PPC_INSTR_ALIGNMENT_SHIFT); |
59 |
|
cpu->pc += (low_pc << PPC_INSTR_ALIGNMENT_SHIFT); |
60 |
|
|
61 |
#ifndef LS_B |
#ifndef LS_B |
62 |
if (addr & (LS_SIZE-1)) { |
if ((addr & 0xfff) + LS_SIZE-1 > 0xfff) { |
63 |
fatal("PPC LOAD/STORE misalignment: TODO\n"); |
fatal("PPC LOAD/STORE misalignment across page boundary: TODO" |
64 |
|
" (addr=0x%08x, LS_SIZE=%i)\n", (int)addr, LS_SIZE); |
65 |
exit(1); |
exit(1); |
66 |
} |
} |
67 |
#endif |
#endif |
69 |
#ifdef LS_LOAD |
#ifdef LS_LOAD |
70 |
if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data), |
if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data), |
71 |
MEM_READ, CACHE_DATA)) { |
MEM_READ, CACHE_DATA)) { |
72 |
fatal("load failed: TODO\n"); |
/* Exception. */ |
73 |
exit(1); |
return; |
74 |
} |
} |
75 |
#ifdef LS_B |
#ifdef LS_B |
76 |
reg(ic->arg[0]) = |
reg(ic->arg[0]) = |
81 |
#endif |
#endif |
82 |
#ifdef LS_H |
#ifdef LS_H |
83 |
reg(ic->arg[0]) = |
reg(ic->arg[0]) = |
84 |
|
#ifdef LS_BYTEREVERSE |
85 |
|
((data[1] << 8) + data[0]); |
86 |
|
#else |
87 |
#ifndef LS_ZERO |
#ifndef LS_ZERO |
88 |
(int16_t) |
(int16_t) |
89 |
#endif |
#endif |
90 |
((data[0] << 8) + data[1]); |
((data[0] << 8) + data[1]); |
91 |
|
#endif /* !BYTEREVERSE */ |
92 |
#endif |
#endif |
93 |
#ifdef LS_W |
#ifdef LS_W |
94 |
reg(ic->arg[0]) = |
reg(ic->arg[0]) = |
95 |
|
#ifdef LS_BYTEREVERSE |
96 |
|
((data[3] << 24) + (data[2] << 16) + |
97 |
|
(data[1] << 8) + data[0]); |
98 |
|
#else /* !LS_BYTEREVERSE */ |
99 |
#ifndef LS_ZERO |
#ifndef LS_ZERO |
100 |
(int32_t) |
(int32_t) |
101 |
|
#else |
102 |
|
(uint32_t) |
103 |
#endif |
#endif |
104 |
((data[0] << 24) + (data[1] << 16) + |
((data[0] << 24) + (data[1] << 16) + |
105 |
(data[2] << 8) + data[3]); |
(data[2] << 8) + data[3]); |
106 |
|
#endif /* !LS_BYTEREVERSE */ |
107 |
#endif |
#endif |
108 |
#ifdef LS_D |
#ifdef LS_D |
109 |
reg(ic->arg[0]) = |
(*(uint64_t *)(ic->arg[0])) = |
110 |
((uint64_t)data[0] << 56) + |
((uint64_t)data[0] << 56) + ((uint64_t)data[1] << 48) + |
111 |
((uint64_t)data[1] << 48) + |
((uint64_t)data[2] << 40) + ((uint64_t)data[3] << 32) + |
112 |
((uint64_t)data[2] << 40) + |
((uint64_t)data[4] << 24) + (data[5] << 16) + |
113 |
((uint64_t)data[3] << 32) + |
(data[6] << 8) + data[7]; |
|
(data[4] << 24) + (data[5] << 16) + (data[6] << 8) + data[7]; |
|
114 |
#endif |
#endif |
115 |
|
|
116 |
#else /* store: */ |
#else /* store: */ |
119 |
data[0] = reg(ic->arg[0]); |
data[0] = reg(ic->arg[0]); |
120 |
#endif |
#endif |
121 |
#ifdef LS_H |
#ifdef LS_H |
122 |
|
#ifdef LS_BYTEREVERSE |
123 |
|
data[0] = reg(ic->arg[0]); |
124 |
|
data[1] = reg(ic->arg[0]) >> 8; |
125 |
|
#else |
126 |
data[0] = reg(ic->arg[0]) >> 8; |
data[0] = reg(ic->arg[0]) >> 8; |
127 |
data[1] = reg(ic->arg[0]); |
data[1] = reg(ic->arg[0]); |
128 |
#endif |
#endif |
129 |
|
#endif |
130 |
#ifdef LS_W |
#ifdef LS_W |
131 |
|
#ifdef LS_BYTEREVERSE |
132 |
|
data[0] = reg(ic->arg[0]); |
133 |
|
data[1] = reg(ic->arg[0]) >> 8; |
134 |
|
data[2] = reg(ic->arg[0]) >> 16; |
135 |
|
data[3] = reg(ic->arg[0]) >> 24; |
136 |
|
#else |
137 |
data[0] = reg(ic->arg[0]) >> 24; |
data[0] = reg(ic->arg[0]) >> 24; |
138 |
data[1] = reg(ic->arg[0]) >> 16; |
data[1] = reg(ic->arg[0]) >> 16; |
139 |
data[2] = reg(ic->arg[0]) >> 8; |
data[2] = reg(ic->arg[0]) >> 8; |
140 |
data[3] = reg(ic->arg[0]); |
data[3] = reg(ic->arg[0]); |
141 |
|
#endif /* !LS_BYTEREVERSE */ |
142 |
#endif |
#endif |
143 |
#ifdef LS_D |
#ifdef LS_D |
144 |
data[0] = (uint64_t)reg(ic->arg[0]) >> 56; |
{ uint64_t x = *(uint64_t *)(ic->arg[0]); |
145 |
data[1] = (uint64_t)reg(ic->arg[0]) >> 48; |
data[0] = x >> 56; |
146 |
data[2] = (uint64_t)reg(ic->arg[0]) >> 40; |
data[1] = x >> 48; |
147 |
data[3] = (uint64_t)reg(ic->arg[0]) >> 32; |
data[2] = x >> 40; |
148 |
data[4] = reg(ic->arg[0]) >> 24; |
data[3] = x >> 32; |
149 |
data[5] = reg(ic->arg[0]) >> 16; |
data[4] = x >> 24; |
150 |
data[6] = reg(ic->arg[0]) >> 8; |
data[5] = x >> 16; |
151 |
data[7] = reg(ic->arg[0]); |
data[6] = x >> 8; |
152 |
|
data[7] = x; } |
153 |
#endif |
#endif |
154 |
if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data), |
if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data), |
155 |
MEM_WRITE, CACHE_DATA)) { |
MEM_WRITE, CACHE_DATA)) { |
156 |
fatal("store failed: TODO\n"); |
/* Exception. */ |
157 |
exit(1); |
return; |
158 |
} |
} |
159 |
#endif |
#endif |
160 |
|
|
194 |
|
|
195 |
#ifndef LS_B |
#ifndef LS_B |
196 |
if (addr & (LS_SIZE-1)) { |
if (addr & (LS_SIZE-1)) { |
|
fatal("PPC LOAD/STORE misalignment: TODO\n"); |
|
|
exit(1); |
|
|
|
|
|
/* |
|
|
* TODO: |
|
|
* Removing the fatal() call above causes WEIRD BUGS with compaq's cc! :( |
|
|
*/ |
|
|
|
|
197 |
LS_GENERIC_N(cpu, ic); |
LS_GENERIC_N(cpu, ic); |
198 |
return; |
return; |
199 |
} |
} |
215 |
#endif /* LS_B */ |
#endif /* LS_B */ |
216 |
#ifdef LS_H |
#ifdef LS_H |
217 |
reg(ic->arg[0]) = |
reg(ic->arg[0]) = |
218 |
|
#ifdef LS_BYTEREVERSE |
219 |
|
((page[addr+1] << 8) + page[addr]); |
220 |
|
#else |
221 |
#ifndef LS_ZERO |
#ifndef LS_ZERO |
222 |
(int16_t) |
(int16_t) |
223 |
#endif |
#endif |
224 |
((page[addr] << 8) + page[addr+1]); |
((page[addr] << 8) + page[addr+1]); |
225 |
|
#endif /* !BYTEREVERSE */ |
226 |
#endif /* LS_H */ |
#endif /* LS_H */ |
227 |
#ifdef LS_W |
#ifdef LS_W |
228 |
reg(ic->arg[0]) = |
reg(ic->arg[0]) = |
229 |
|
#ifdef LS_BYTEREVERSE |
230 |
|
((page[addr+3] << 24) + (page[addr+2] << 16) + |
231 |
|
(page[addr+1] << 8) + page[addr]); |
232 |
|
#else /* !LS_BYTEREVERSE */ |
233 |
#ifndef LS_ZERO |
#ifndef LS_ZERO |
234 |
(int32_t) |
(int32_t) |
235 |
|
#else |
236 |
|
(uint32_t) |
237 |
#endif |
#endif |
238 |
((page[addr] << 24) + (page[addr+1] << 16) + |
((page[addr] << 24) + (page[addr+1] << 16) + |
239 |
(page[addr+2] << 8) + page[addr+3]); |
(page[addr+2] << 8) + page[addr+3]); |
240 |
|
#endif /* !LS_BYTEREVERSE */ |
241 |
#endif /* LS_W */ |
#endif /* LS_W */ |
242 |
#ifdef LS_D |
#ifdef LS_D |
243 |
reg(ic->arg[0]) = |
(*(uint64_t *)(ic->arg[0])) = |
244 |
((uint64_t)page[addr+0] << 56) + |
((uint64_t)page[addr+0] << 56) + |
245 |
((uint64_t)page[addr+1] << 48) + |
((uint64_t)page[addr+1] << 48) + |
246 |
((uint64_t)page[addr+2] << 40) + |
((uint64_t)page[addr+2] << 40) + |
247 |
((uint64_t)page[addr+3] << 32) + |
((uint64_t)page[addr+3] << 32) + |
248 |
(page[addr+4] << 24) + (page[addr+5] << 16) + |
((uint64_t)page[addr+4] << 24) + (page[addr+5] << 16) + |
249 |
(page[addr+6] << 8) + page[addr+7]; |
(page[addr+6] << 8) + page[addr+7]; |
250 |
#endif /* LS_D */ |
#endif /* LS_D */ |
251 |
|
|
256 |
page[addr] = reg(ic->arg[0]); |
page[addr] = reg(ic->arg[0]); |
257 |
#endif |
#endif |
258 |
#ifdef LS_H |
#ifdef LS_H |
259 |
|
#ifdef LS_BYTEREVERSE |
260 |
|
page[addr] = reg(ic->arg[0]); |
261 |
|
page[addr+1] = reg(ic->arg[0]) >> 8; |
262 |
|
#else |
263 |
page[addr] = reg(ic->arg[0]) >> 8; |
page[addr] = reg(ic->arg[0]) >> 8; |
264 |
page[addr+1] = reg(ic->arg[0]); |
page[addr+1] = reg(ic->arg[0]); |
265 |
|
#endif /* !BYTEREVERSE */ |
266 |
#endif |
#endif |
267 |
#ifdef LS_W |
#ifdef LS_W |
268 |
|
#ifdef LS_BYTEREVERSE |
269 |
|
page[addr] = reg(ic->arg[0]); |
270 |
|
page[addr+1] = reg(ic->arg[0]) >> 8; |
271 |
|
page[addr+2] = reg(ic->arg[0]) >> 16; |
272 |
|
page[addr+3] = reg(ic->arg[0]) >> 24; |
273 |
|
#else |
274 |
page[addr] = reg(ic->arg[0]) >> 24; |
page[addr] = reg(ic->arg[0]) >> 24; |
275 |
page[addr+1] = reg(ic->arg[0]) >> 16; |
page[addr+1] = reg(ic->arg[0]) >> 16; |
276 |
page[addr+2] = reg(ic->arg[0]) >> 8; |
page[addr+2] = reg(ic->arg[0]) >> 8; |
277 |
page[addr+3] = reg(ic->arg[0]); |
page[addr+3] = reg(ic->arg[0]); |
278 |
|
#endif /* !LS_BYTEREVERSE */ |
279 |
#endif |
#endif |
280 |
#ifdef LS_D |
#ifdef LS_D |
281 |
page[addr] = (uint64_t)reg(ic->arg[0]) >> 56; |
{ uint64_t x = *(uint64_t *)(ic->arg[0]); |
282 |
page[addr+1] = (uint64_t)reg(ic->arg[0]) >> 48; |
page[addr] = x >> 56; |
283 |
page[addr+2] = (uint64_t)reg(ic->arg[0]) >> 40; |
page[addr+1] = x >> 48; |
284 |
page[addr+3] = (uint64_t)reg(ic->arg[0]) >> 32; |
page[addr+2] = x >> 40; |
285 |
page[addr+4] = reg(ic->arg[0]) >> 24; |
page[addr+3] = x >> 32; |
286 |
page[addr+5] = reg(ic->arg[0]) >> 16; |
page[addr+4] = x >> 24; |
287 |
page[addr+6] = reg(ic->arg[0]) >> 8; |
page[addr+5] = x >> 16; |
288 |
page[addr+7] = reg(ic->arg[0]); |
page[addr+6] = x >> 8; |
289 |
|
page[addr+7] = x; } |
290 |
#endif |
#endif |
291 |
#endif /* !LS_LOAD */ |
#endif /* !LS_LOAD */ |
292 |
} |
} |