/[gxemul]/trunk/src/cpus/cpu_ppc_instr_loadstore.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Contents of /trunk/src/cpus/cpu_ppc_instr_loadstore.c

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Revision 14 - (show annotations)
Mon Oct 8 16:18:51 2007 UTC (16 years, 5 months ago) by dpavlin
File MIME type: text/plain
File size: 6282 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.982 2005/10/07 22:45:32 debug Exp $
20050816	Some success in decoding the way the SGI O2 PROM draws graphics
		during bootup; lines/rectangles and bitmaps work, enough to
		show the bootlogo etc. :-)
		Adding more PPC instructions, and (dummy) BAT registers.
20050817	Updating the pckbc to support scancode type 3 keyboards
		(required in order to interact with the SGI O2 PROM).
		Adding more PPC instructions.
20050818	Adding more ARM instructions; general register forms.
		Importing armreg.h from NetBSD (ARM cpu ids). Adding a (dummy)
		CATS machine mode (using SA110 as the default CPU).
		Continuing on general dyntrans related stuff.
20050819	Register forms for ARM load/stores. Gaah! The Compaq C Compiler
		bug is triggered for ARM loads as well, not just PPC :-(
		Adding full support for ARM PC-relative load/stores, and load/
		stores where the PC register is the destination register.
		Adding support for ARM a.out binaries.
20050820	Continuing to add more ARM instructions, and correcting some
		bugs. Continuing on CATS emulation.
		More work on the PPC stuff.
20050821	Minor PPC and ARM updates. Adding more machine types.
20050822	All ARM "data processing instructions" are now generated
		automatically.
20050824	Beginning the work on the ARM system control coprocessor.
		Adding support for ARM halfword load/stores, and signed loads.
20050825	Fixing an important bug related to the ARM condition codes.
		OpenBSD/zaurus and NetBSD/netwinder now print some boot
		messages. :)
		Adding a dummy SH (Hitachi SuperH) cpu family.
		Beginning to add some ARM virtual address translation.
		MIPS bugfixes: unaligned PC now cause an ADEL exception (at
		least for non-bintrans execution), and ADEL/ADES (not
		TLBL/TLBS) are used if userland tries to access kernel space.
		(Thanks to Joshua Wise for making me aware of these bugs.)
20050827	More work on the ARM emulation, and various other updates.
20050828	More ARM updates.
		Finally taking the time to work on translation invalidation
		(i.e. invalidating translated code mappings when memory is
		written to). Hopefully this doesn't break anything.
20050829	Moving CPU related files from src/ to a new subdir, src/cpus/.
		Moving PROM emulation stuff from src/ to src/promemul/.
		Better debug instruction trace for ARM loads and stores.
20050830	Various ARM updates (correcting CMP flag calculation, etc).
20050831	PPC instruction updates. (Flag fixes, etc.)
20050901	Various minor PPC and ARM instruction emulation updates.
		Minor OpenFirmware emulation updates.
20050903	Adding support for adding arbitrary ARM coprocessors (with
		the i80321 I/O coprocessor as a first test).
		Various other ARM and PPC updates.
20050904	Adding some SHcompact disassembly routines.
20050907	(Re)adding a dummy HPPA CPU module, and a dummy i960 module.
20050908	Began hacking on some Apple Partition Table support.
20050909	Adding support for loading Mach-O (Darwin PPC) binaries.
20050910	Fixing an ARM bug (Carry flag was incorrectly updated for some
		data processing instructions); OpenBSD/cats and NetBSD/
		netwinder get quite a bit further now.
		Applying a patch to dev_wdc, and a one-liner to dev_pcic, to
		make them work better when emulating new versions of OpenBSD.
		(Thanks to Alexander Yurchenko for the patches.)
		Also doing some other minor updates to dev_wdc. (Some cleanup,
		and finally converting to devinit, etc.)
20050912	IRIX doesn't have u_int64_t by default (noticed by Andreas
		<avr@gnulinux.nl>); configure updated to reflect this.
		Working on ARM register bank switching, CPSR vs SPSR issues,
		and beginning the work on interrupt/exception support.
20050913	Various minor ARM updates (speeding up load/store multiple,
		and fixing a ROR bug in R(); NetBSD/cats now boots as far as
		OpenBSD/cats).
20050917	Adding a dummy Atmel AVR (8-bit) cpu family skeleton.
20050918	Various minor updates.
20050919	Symbols are now loaded from Mach-O executables.
		Continuing the work on adding ARM exception support.
20050920	More work on ARM stuff: OpenBSD/cats and NetBSD/cats reach
		userland! :-)
20050921	Some more progress on ARM interrupt specifics.
20050923	Fixing linesize for VR4121 (patch by Yurchenko). Also fixing
		linesizes/cachesizes for some other VR4xxx.
		Adding a dummy Acer Labs M1543 PCI-ISA bridge (for CATS) and a
		dummy Symphony Labs 83C553 bridge (for Netwinder), usable by 
		dev_footbridge.
20050924	Some PPC progress.
20050925	More PPC progress.
20050926	PPC progress (fixing some bugs etc); Darwin's kernel gets
		slightly further than before.
20050928	Various updates: footbridge/ISA/pciide stuff, and finally
		fixing the VGA text scroll-by-changing-the-base-offset bug.
20050930	Adding a dummy S3 ViRGE pci card for CATS emulation, which
		both NetBSD and OpenBSD detects as VGA.
		Continuing on Footbridge (timers, ISA interrupt stuff).
20051001	Continuing... there are still bugs, probably interrupt-
		related.
20051002	More work on the Footbridge (interrupt stuff).
20051003	Various minor updates. (Trying to find the bug(s).)
20051004	Continuing on the ARM stuff.
20051005	More ARM-related fixes.
20051007	FINALLY! Found and fixed 2 ARM bugs: 1 memory related, and the
		other was because of an error in the ARM manual (load multiple
		with the S-bit set should _NOT_ load usermode registers, as the
		manual says, but it should load saved registers, which may or
		may not happen to be usermode registers).
		NetBSD/cats and OpenBSD/cats seem to install fine now :-)
		except for a minor bug at the end of the OpenBSD/cats install.
		Updating the documentation, preparing for the next release.
20051008	Continuing with release testing and cleanup.

1 /*
2 * Copyright (C) 2005 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: cpu_ppc_instr_loadstore.c,v 1.1 2005/08/29 14:36:41 debug Exp $
29 *
30 * POWER/PowerPC load/store instructions.
31 *
32 *
33 * Load/store instructions have the following arguments:
34 *
35 * arg[0] = pointer to the register to load to or store from
36 * arg[1] = pointer to the base register
37 *
38 * arg[2] = offset (as an int32_t)
39 * (or, for Indexed load/stores: pointer to index register)
40 */
41
42
43 #ifndef LS_IGNOREOFS
44 void LS_GENERIC_N(struct cpu *cpu, struct ppc_instr_call *ic)
45 {
46 #ifdef MODE32
47 uint32_t addr = reg(ic->arg[1]) +
48 #ifdef LS_INDEXED
49 reg(ic->arg[2]);
50 #else
51 (int32_t)ic->arg[2];
52 #endif
53 unsigned char data[LS_SIZE];
54
55 #ifndef LS_B
56 if (addr & (LS_SIZE-1)) {
57 fatal("PPC LOAD/STORE misalignment: TODO\n");
58 exit(1);
59 }
60 #endif
61
62 #ifdef LS_LOAD
63 if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data),
64 MEM_READ, CACHE_DATA)) {
65 fatal("load failed: TODO\n");
66 exit(1);
67 }
68 #ifdef LS_B
69 reg(ic->arg[0]) =
70 #ifndef LS_ZERO
71 (int8_t)
72 #endif
73 data[0];
74 #endif
75 #ifdef LS_H
76 reg(ic->arg[0]) =
77 #ifndef LS_ZERO
78 (int16_t)
79 #endif
80 ((data[0] << 8) + data[1]);
81 #endif
82 #ifdef LS_W
83 reg(ic->arg[0]) =
84 #ifndef LS_ZERO
85 (int32_t)
86 #endif
87 ((data[0] << 24) + (data[1] << 16) +
88 (data[2] << 8) + data[3]);
89 #endif
90 #ifdef LS_D
91 reg(ic->arg[0]) =
92 ((uint64_t)data[0] << 56) +
93 ((uint64_t)data[1] << 48) +
94 ((uint64_t)data[2] << 40) +
95 ((uint64_t)data[3] << 32) +
96 (data[4] << 24) + (data[5] << 16) + (data[6] << 8) + data[7];
97 #endif
98
99 #else /* store: */
100
101 #ifdef LS_B
102 data[0] = reg(ic->arg[0]);
103 #endif
104 #ifdef LS_H
105 data[0] = reg(ic->arg[0]) >> 8;
106 data[1] = reg(ic->arg[0]);
107 #endif
108 #ifdef LS_W
109 data[0] = reg(ic->arg[0]) >> 24;
110 data[1] = reg(ic->arg[0]) >> 16;
111 data[2] = reg(ic->arg[0]) >> 8;
112 data[3] = reg(ic->arg[0]);
113 #endif
114 #ifdef LS_D
115 data[0] = (uint64_t)reg(ic->arg[0]) >> 56;
116 data[1] = (uint64_t)reg(ic->arg[0]) >> 48;
117 data[2] = (uint64_t)reg(ic->arg[0]) >> 40;
118 data[3] = (uint64_t)reg(ic->arg[0]) >> 32;
119 data[4] = reg(ic->arg[0]) >> 24;
120 data[5] = reg(ic->arg[0]) >> 16;
121 data[6] = reg(ic->arg[0]) >> 8;
122 data[7] = reg(ic->arg[0]);
123 #endif
124 if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data),
125 MEM_WRITE, CACHE_DATA)) {
126 fatal("store failed: TODO\n");
127 exit(1);
128 }
129 #endif
130
131 #ifdef LS_UPDATE
132 reg(ic->arg[1]) = addr;
133 #endif
134 #else /* !MODE32 */
135 fatal("TODO: mode64\n");
136 #endif /* !MODE32 */
137 }
138 #endif
139
140
141 void LS_N(struct cpu *cpu, struct ppc_instr_call *ic)
142 {
143 #ifdef MODE32
144 uint32_t addr = reg(ic->arg[1])
145 #ifdef LS_INDEXED
146 + reg(ic->arg[2])
147 #else
148 #ifndef LS_IGNOREOFS
149 + (int32_t)ic->arg[2]
150 #endif
151 #endif
152 ;
153
154 unsigned char *page = cpu->cd.ppc.
155 #ifdef LS_LOAD
156 host_load
157 #else
158 host_store
159 #endif
160 [addr >> 12];
161 #ifdef LS_UPDATE
162 uint32_t new_addr = addr;
163 #endif
164
165 #ifndef LS_B
166 if (addr & (LS_SIZE-1)) {
167 fatal("PPC LOAD/STORE misalignment: TODO\n");
168 exit(1);
169
170 /*
171 * TODO:
172 * Removing the fatal() call above causes WEIRD BUGS with compaq's cc! :(
173 */
174
175 LS_GENERIC_N(cpu, ic);
176 return;
177 }
178 #endif
179
180 if (page == NULL) {
181 LS_GENERIC_N(cpu, ic);
182 return;
183 } else {
184 addr &= 4095;
185 #ifdef LS_LOAD
186 /* Load: */
187 #ifdef LS_B
188 reg(ic->arg[0]) =
189 #ifndef LS_ZERO
190 (int8_t)
191 #endif
192 page[addr];
193 #endif /* LS_B */
194 #ifdef LS_H
195 reg(ic->arg[0]) =
196 #ifndef LS_ZERO
197 (int16_t)
198 #endif
199 ((page[addr] << 8) + page[addr+1]);
200 #endif /* LS_H */
201 #ifdef LS_W
202 reg(ic->arg[0]) =
203 #ifndef LS_ZERO
204 (int32_t)
205 #endif
206 ((page[addr] << 24) + (page[addr+1] << 16) +
207 (page[addr+2] << 8) + page[addr+3]);
208 #endif /* LS_W */
209 #ifdef LS_D
210 reg(ic->arg[0]) =
211 ((uint64_t)page[addr+0] << 56) +
212 ((uint64_t)page[addr+1] << 48) +
213 ((uint64_t)page[addr+2] << 40) +
214 ((uint64_t)page[addr+3] << 32) +
215 (page[addr+4] << 24) + (page[addr+5] << 16) +
216 (page[addr+6] << 8) + page[addr+7];
217 #endif /* LS_D */
218
219 #else /* !LS_LOAD */
220
221 /* Store: */
222 #ifdef LS_B
223 page[addr] = reg(ic->arg[0]);
224 #endif
225 #ifdef LS_H
226 page[addr] = reg(ic->arg[0]) >> 8;
227 page[addr+1] = reg(ic->arg[0]);
228 #endif
229 #ifdef LS_W
230 page[addr] = reg(ic->arg[0]) >> 24;
231 page[addr+1] = reg(ic->arg[0]) >> 16;
232 page[addr+2] = reg(ic->arg[0]) >> 8;
233 page[addr+3] = reg(ic->arg[0]);
234 #endif
235 #ifdef LS_D
236 page[addr] = (uint64_t)reg(ic->arg[0]) >> 56;
237 page[addr+1] = (uint64_t)reg(ic->arg[0]) >> 48;
238 page[addr+2] = (uint64_t)reg(ic->arg[0]) >> 40;
239 page[addr+3] = (uint64_t)reg(ic->arg[0]) >> 32;
240 page[addr+4] = reg(ic->arg[0]) >> 24;
241 page[addr+5] = reg(ic->arg[0]) >> 16;
242 page[addr+6] = reg(ic->arg[0]) >> 8;
243 page[addr+7] = reg(ic->arg[0]);
244 #endif
245 #endif /* !LS_LOAD */
246 }
247
248 #ifdef LS_UPDATE
249 reg(ic->arg[1]) = new_addr;
250 #endif
251
252 #else /* !MODE32 */
253 fatal("ppc load/store mode64: TODO\n");
254 exit(1);
255 #endif
256 }
257

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