25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: cpu_ppc.c,v 1.45 2006/01/24 21:26:01 debug Exp $ |
* $Id: cpu_ppc.c,v 1.64 2006/09/21 11:53:26 debug Exp $ |
29 |
* |
* |
30 |
* PowerPC/POWER CPU emulation. |
* PowerPC/POWER CPU emulation. |
31 |
*/ |
*/ |
46 |
#include "ppc_pte.h" |
#include "ppc_pte.h" |
47 |
#include "ppc_spr.h" |
#include "ppc_spr.h" |
48 |
#include "ppc_spr_strings.h" |
#include "ppc_spr_strings.h" |
49 |
|
#include "settings.h" |
50 |
#include "symbol.h" |
#include "symbol.h" |
51 |
|
|
52 |
#define DYNTRANS_DUALMODE_32 |
#define DYNTRANS_DUALMODE_32 |
87 |
|
|
88 |
cpu->memory_rw = ppc_memory_rw; |
cpu->memory_rw = ppc_memory_rw; |
89 |
|
|
90 |
cpu->cd.ppc.cpu_type = cpu_type_defs[found]; |
cpu->cd.ppc.cpu_type = cpu_type_defs[found]; |
91 |
cpu->name = cpu->cd.ppc.cpu_type.name; |
cpu->name = cpu->cd.ppc.cpu_type.name; |
92 |
cpu->byte_order = EMUL_BIG_ENDIAN; |
cpu->byte_order = EMUL_BIG_ENDIAN; |
93 |
cpu->cd.ppc.mode = MODE_PPC; /* TODO */ |
cpu->cd.ppc.mode = MODE_PPC; /* TODO */ |
94 |
|
|
95 |
/* Current operating mode: */ |
/* Current operating mode: */ |
96 |
cpu->cd.ppc.bits = cpu->cd.ppc.cpu_type.bits; |
cpu->cd.ppc.bits = cpu->cd.ppc.cpu_type.bits; |
97 |
cpu->cd.ppc.spr[SPR_PVR] = cpu->cd.ppc.cpu_type.pvr; |
cpu->cd.ppc.spr[SPR_PVR] = cpu->cd.ppc.cpu_type.pvr; |
98 |
|
|
99 |
|
/* cpu->cd.ppc.msr = PPC_MSR_IR | PPC_MSR_DR | |
100 |
|
PPC_MSR_SF | PPC_MSR_FP; */ |
101 |
|
|
102 |
cpu->cd.ppc.spr[SPR_IBAT0U] = 0x00001ffc | BAT_Vs; |
cpu->cd.ppc.spr[SPR_IBAT0U] = 0x00001ffc | BAT_Vs; |
103 |
cpu->cd.ppc.spr[SPR_IBAT0L] = 0x00000000 | BAT_PP_RW; |
cpu->cd.ppc.spr[SPR_IBAT0L] = 0x00000000 | BAT_PP_RW; |
104 |
cpu->cd.ppc.spr[SPR_IBAT1U] = 0xc0001ffc | BAT_Vs; |
cpu->cd.ppc.spr[SPR_IBAT1U] = 0xc0001ffc | BAT_Vs; |
117 |
cpu->is_32bit = (cpu->cd.ppc.bits == 32)? 1 : 0; |
cpu->is_32bit = (cpu->cd.ppc.bits == 32)? 1 : 0; |
118 |
|
|
119 |
if (cpu->is_32bit) { |
if (cpu->is_32bit) { |
120 |
|
cpu->run_instr = ppc32_run_instr; |
121 |
cpu->update_translation_table = ppc32_update_translation_table; |
cpu->update_translation_table = ppc32_update_translation_table; |
122 |
cpu->invalidate_translation_caches = |
cpu->invalidate_translation_caches = |
123 |
ppc32_invalidate_translation_caches; |
ppc32_invalidate_translation_caches; |
124 |
cpu->invalidate_code_translation = |
cpu->invalidate_code_translation = |
125 |
ppc32_invalidate_code_translation; |
ppc32_invalidate_code_translation; |
126 |
} else { |
} else { |
127 |
|
cpu->run_instr = ppc_run_instr; |
128 |
cpu->update_translation_table = ppc_update_translation_table; |
cpu->update_translation_table = ppc_update_translation_table; |
129 |
cpu->invalidate_translation_caches = |
cpu->invalidate_translation_caches = |
130 |
ppc_invalidate_translation_caches; |
ppc_invalidate_translation_caches; |
132 |
ppc_invalidate_code_translation; |
ppc_invalidate_code_translation; |
133 |
} |
} |
134 |
|
|
135 |
cpu->translate_address = ppc_translate_address; |
cpu->translate_v2p = ppc_translate_v2p; |
136 |
|
|
137 |
/* Only show name and caches etc for CPU nr 0 (in SMP machines): */ |
/* Only show name and caches etc for CPU nr 0 (in SMP machines): */ |
138 |
if (cpu_id == 0) { |
if (cpu_id == 0) { |
169 |
if (cpu->machine->prom_emulation) |
if (cpu->machine->prom_emulation) |
170 |
cpu->cd.ppc.of_emul_addr = 0xfff00000; |
cpu->cd.ppc.of_emul_addr = 0xfff00000; |
171 |
|
|
172 |
|
/* Add all register names to the settings: */ |
173 |
|
CPU_SETTINGS_ADD_REGISTER64("pc", cpu->pc); |
174 |
|
CPU_SETTINGS_ADD_REGISTER64("msr", cpu->cd.ppc.msr); |
175 |
|
CPU_SETTINGS_ADD_REGISTER64("ctr", cpu->cd.ppc.spr[SPR_CTR]); |
176 |
|
CPU_SETTINGS_ADD_REGISTER64("xer", cpu->cd.ppc.spr[SPR_XER]); |
177 |
|
CPU_SETTINGS_ADD_REGISTER64("dec", cpu->cd.ppc.spr[SPR_DEC]); |
178 |
|
CPU_SETTINGS_ADD_REGISTER64("hdec", cpu->cd.ppc.spr[SPR_HDEC]); |
179 |
|
CPU_SETTINGS_ADD_REGISTER64("srr0", cpu->cd.ppc.spr[SPR_SRR0]); |
180 |
|
CPU_SETTINGS_ADD_REGISTER64("srr1", cpu->cd.ppc.spr[SPR_SRR1]); |
181 |
|
CPU_SETTINGS_ADD_REGISTER64("sdr1", cpu->cd.ppc.spr[SPR_SDR1]); |
182 |
|
CPU_SETTINGS_ADD_REGISTER64("ibat0u", cpu->cd.ppc.spr[SPR_IBAT0U]); |
183 |
|
CPU_SETTINGS_ADD_REGISTER64("ibat0l", cpu->cd.ppc.spr[SPR_IBAT0L]); |
184 |
|
CPU_SETTINGS_ADD_REGISTER64("ibat1u", cpu->cd.ppc.spr[SPR_IBAT1U]); |
185 |
|
CPU_SETTINGS_ADD_REGISTER64("ibat1l", cpu->cd.ppc.spr[SPR_IBAT1L]); |
186 |
|
CPU_SETTINGS_ADD_REGISTER64("ibat2u", cpu->cd.ppc.spr[SPR_IBAT2U]); |
187 |
|
CPU_SETTINGS_ADD_REGISTER64("ibat2l", cpu->cd.ppc.spr[SPR_IBAT2L]); |
188 |
|
CPU_SETTINGS_ADD_REGISTER64("ibat3u", cpu->cd.ppc.spr[SPR_IBAT3U]); |
189 |
|
CPU_SETTINGS_ADD_REGISTER64("ibat3l", cpu->cd.ppc.spr[SPR_IBAT3L]); |
190 |
|
CPU_SETTINGS_ADD_REGISTER64("dbat0u", cpu->cd.ppc.spr[SPR_DBAT0U]); |
191 |
|
CPU_SETTINGS_ADD_REGISTER64("dbat0l", cpu->cd.ppc.spr[SPR_DBAT0L]); |
192 |
|
CPU_SETTINGS_ADD_REGISTER64("dbat1u", cpu->cd.ppc.spr[SPR_DBAT1U]); |
193 |
|
CPU_SETTINGS_ADD_REGISTER64("dbat1l", cpu->cd.ppc.spr[SPR_DBAT1L]); |
194 |
|
CPU_SETTINGS_ADD_REGISTER64("dbat2u", cpu->cd.ppc.spr[SPR_DBAT2U]); |
195 |
|
CPU_SETTINGS_ADD_REGISTER64("dbat2l", cpu->cd.ppc.spr[SPR_DBAT2L]); |
196 |
|
CPU_SETTINGS_ADD_REGISTER64("dbat3u", cpu->cd.ppc.spr[SPR_DBAT3U]); |
197 |
|
CPU_SETTINGS_ADD_REGISTER64("dbat3l", cpu->cd.ppc.spr[SPR_DBAT3L]); |
198 |
|
CPU_SETTINGS_ADD_REGISTER64("lr", cpu->cd.ppc.spr[SPR_LR]); |
199 |
|
CPU_SETTINGS_ADD_REGISTER32("cr", cpu->cd.ppc.cr); |
200 |
|
CPU_SETTINGS_ADD_REGISTER32("fpscr", cpu->cd.ppc.fpscr); |
201 |
|
/* Integer GPRs, floating point registers, and segment registers: */ |
202 |
|
for (i=0; i<PPC_NGPRS; i++) { |
203 |
|
char tmpstr[5]; |
204 |
|
snprintf(tmpstr, sizeof(tmpstr), "r%i", i); |
205 |
|
CPU_SETTINGS_ADD_REGISTER64(tmpstr, cpu->cd.ppc.gpr[i]); |
206 |
|
} |
207 |
|
for (i=0; i<PPC_NFPRS; i++) { |
208 |
|
char tmpstr[5]; |
209 |
|
snprintf(tmpstr, sizeof(tmpstr), "f%i", i); |
210 |
|
CPU_SETTINGS_ADD_REGISTER64(tmpstr, cpu->cd.ppc.fpr[i]); |
211 |
|
} |
212 |
|
for (i=0; i<16; i++) { |
213 |
|
char tmpstr[5]; |
214 |
|
snprintf(tmpstr, sizeof(tmpstr), "sr%i", i); |
215 |
|
CPU_SETTINGS_ADD_REGISTER32(tmpstr, cpu->cd.ppc.sr[i]); |
216 |
|
} |
217 |
|
|
218 |
return 1; |
return 1; |
219 |
} |
} |
220 |
|
|
319 |
*valuep = cpu->cd.ppc.msr; |
*valuep = cpu->cd.ppc.msr; |
320 |
|
|
321 |
if (check_for_interrupts && cpu->cd.ppc.msr & PPC_MSR_EE) { |
if (check_for_interrupts && cpu->cd.ppc.msr & PPC_MSR_EE) { |
322 |
if (cpu->cd.ppc.dec_intr_pending) { |
if (cpu->cd.ppc.dec_intr_pending && |
323 |
|
!(cpu->cd.ppc.cpu_type.flags & PPC_NO_DEC)) { |
324 |
ppc_exception(cpu, PPC_EXCEPTION_DEC); |
ppc_exception(cpu, PPC_EXCEPTION_DEC); |
325 |
cpu->cd.ppc.dec_intr_pending = 0; |
cpu->cd.ppc.dec_intr_pending = 0; |
326 |
} else if (cpu->cd.ppc.irq_asserted) |
} else if (cpu->cd.ppc.irq_asserted) |
344 |
cpu->cd.ppc.spr[SPR_SRR1] = (cpu->cd.ppc.msr & 0x87c0ffff); |
cpu->cd.ppc.spr[SPR_SRR1] = (cpu->cd.ppc.msr & 0x87c0ffff); |
345 |
|
|
346 |
if (!quiet_mode) |
if (!quiet_mode) |
347 |
fatal("[ PPC Exception 0x%x; pc=0x%llx ]\n", exception_nr, |
fatal("[ PPC Exception 0x%x; pc=0x%"PRIx64" ]\n", exception_nr, |
348 |
(long long)cpu->pc); |
(long long)cpu->pc); |
349 |
|
|
350 |
/* Disable External Interrupts, Recoverable Interrupt Mode, |
/* Disable External Interrupts, Recoverable Interrupt Mode, |
384 |
|
|
385 |
debug("cpu%i: pc = 0x", x); |
debug("cpu%i: pc = 0x", x); |
386 |
if (bits32) |
if (bits32) |
387 |
debug("%08x", (int)cpu->pc); |
debug("%08"PRIx32, (uint32_t)cpu->pc); |
388 |
else |
else |
389 |
debug("%016llx", (long long)cpu->pc); |
debug("%016"PRIx64, (uint64_t)cpu->pc); |
390 |
debug(" <%s>\n", symbol != NULL? symbol : " no symbol "); |
debug(" <%s>\n", symbol != NULL? symbol : " no symbol "); |
391 |
|
|
392 |
debug("cpu%i: lr = 0x", x); |
debug("cpu%i: lr = 0x", x); |
393 |
if (bits32) |
if (bits32) |
394 |
debug("%08x", (int)cpu->cd.ppc.spr[SPR_LR]); |
debug("%08"PRIx32, (uint32_t)cpu->cd.ppc.spr[SPR_LR]); |
395 |
else |
else |
396 |
debug("%016llx", (long long)cpu->cd.ppc.spr[SPR_LR]); |
debug("%016"PRIx64, (uint64_t)cpu->cd.ppc.spr[SPR_LR]); |
397 |
debug(" cr = 0x%08x", (int)cpu->cd.ppc.cr); |
debug(" cr = 0x%08"PRIx32, (uint32_t)cpu->cd.ppc.cr); |
398 |
|
|
399 |
if (bits32) |
if (bits32) |
400 |
debug(" "); |
debug(" "); |
402 |
debug("\ncpu%i: ", x); |
debug("\ncpu%i: ", x); |
403 |
debug("ctr = 0x", x); |
debug("ctr = 0x", x); |
404 |
if (bits32) |
if (bits32) |
405 |
debug("%08x", (int)cpu->cd.ppc.spr[SPR_CTR]); |
debug("%08"PRIx32, (uint32_t)cpu->cd.ppc.spr[SPR_CTR]); |
406 |
else |
else |
407 |
debug("%016llx", (long long)cpu->cd.ppc.spr[SPR_CTR]); |
debug("%016"PRIx64, (uint64_t)cpu->cd.ppc.spr[SPR_CTR]); |
408 |
|
|
409 |
debug(" xer = 0x", x); |
debug(" xer = 0x", x); |
410 |
if (bits32) |
if (bits32) |
411 |
debug("%08x\n", (int)cpu->cd.ppc.spr[SPR_XER]); |
debug("%08"PRIx32, (uint32_t)cpu->cd.ppc.spr[SPR_XER]); |
412 |
else |
else |
413 |
debug("%016llx\n", (long long)cpu->cd.ppc.spr[SPR_XER]); |
debug("%016"PRIx64, (uint64_t)cpu->cd.ppc.spr[SPR_XER]); |
414 |
|
|
415 |
|
debug("\n"); |
416 |
|
|
417 |
if (bits32) { |
if (bits32) { |
418 |
/* 32-bit: */ |
/* 32-bit: */ |
527 |
for (i=0; i<16; i++) { |
for (i=0; i<16; i++) { |
528 |
uint32_t s = cpu->cd.ppc.sr[i]; |
uint32_t s = cpu->cd.ppc.sr[i]; |
529 |
debug("cpu%i:", x); |
debug("cpu%i:", x); |
530 |
debug(" sr%2i = 0x%08x", i, (int)s); |
debug(" sr%-2i = 0x%08x", i, (int)s); |
531 |
s &= (SR_TYPE | SR_SUKEY | SR_PRKEY | SR_NOEXEC); |
s &= (SR_TYPE | SR_SUKEY | SR_PRKEY | SR_NOEXEC); |
532 |
if (s != 0) { |
if (s != 0) { |
533 |
debug(" ("); |
debug(" ("); |
560 |
|
|
561 |
|
|
562 |
/* |
/* |
563 |
* ppc_cpu_register_match(): |
* ppc_cpu_tlbdump(): |
564 |
|
* |
565 |
|
* Not currently used for PPC. |
566 |
*/ |
*/ |
567 |
void ppc_cpu_register_match(struct machine *m, char *name, |
void ppc_cpu_tlbdump(struct machine *m, int x, int rawflag) |
|
int writeflag, uint64_t *valuep, int *match_register) |
|
568 |
{ |
{ |
569 |
int cpunr = 0; |
} |
|
|
|
|
/* CPU number: */ |
|
570 |
|
|
|
/* TODO */ |
|
571 |
|
|
572 |
/* Register name: */ |
static void add_response_word(struct cpu *cpu, char *r, uint64_t value, |
573 |
if (strcasecmp(name, "pc") == 0) { |
size_t maxlen, int len) |
574 |
if (writeflag) { |
{ |
575 |
m->cpus[cpunr]->pc = *valuep; |
char *format = (len == 4)? "%08"PRIx64 : "%016"PRIx64; |
576 |
} else |
if (len == 4) |
577 |
*valuep = m->cpus[cpunr]->pc; |
value &= 0xffffffffULL; |
578 |
*match_register = 1; |
if (cpu->byte_order == EMUL_LITTLE_ENDIAN) { |
579 |
} else if (strcasecmp(name, "msr") == 0) { |
if (len == 4) { |
580 |
if (writeflag) |
value = ((value & 0xff) << 24) + |
581 |
m->cpus[cpunr]->cd.ppc.msr = *valuep; |
((value & 0xff00) << 8) + |
582 |
else |
((value & 0xff0000) >> 8) + |
583 |
*valuep = m->cpus[cpunr]->cd.ppc.msr; |
((value & 0xff000000) >> 24); |
584 |
*match_register = 1; |
} else { |
585 |
} else if (strcasecmp(name, "lr") == 0) { |
value = ((value & 0xff) << 56) + |
586 |
if (writeflag) |
((value & 0xff00) << 40) + |
587 |
m->cpus[cpunr]->cd.ppc.spr[SPR_LR] = *valuep; |
((value & 0xff0000) << 24) + |
588 |
else |
((value & 0xff000000ULL) << 8) + |
589 |
*valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_LR]; |
((value & 0xff00000000ULL) >> 8) + |
590 |
*match_register = 1; |
((value & 0xff0000000000ULL) >> 24) + |
591 |
} else if (strcasecmp(name, "cr") == 0) { |
((value & 0xff000000000000ULL) >> 40) + |
592 |
if (writeflag) |
((value & 0xff00000000000000ULL) >> 56); |
|
m->cpus[cpunr]->cd.ppc.cr = *valuep; |
|
|
else |
|
|
*valuep = m->cpus[cpunr]->cd.ppc.cr; |
|
|
*match_register = 1; |
|
|
} else if (strcasecmp(name, "dec") == 0) { |
|
|
if (writeflag) |
|
|
m->cpus[cpunr]->cd.ppc.spr[SPR_DEC] = *valuep; |
|
|
else |
|
|
*valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_DEC]; |
|
|
*match_register = 1; |
|
|
} else if (strcasecmp(name, "hdec") == 0) { |
|
|
if (writeflag) |
|
|
m->cpus[cpunr]->cd.ppc.spr[SPR_HDEC] = *valuep; |
|
|
else |
|
|
*valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_HDEC]; |
|
|
*match_register = 1; |
|
|
} else if (strcasecmp(name, "ctr") == 0) { |
|
|
if (writeflag) |
|
|
m->cpus[cpunr]->cd.ppc.spr[SPR_CTR] = *valuep; |
|
|
else |
|
|
*valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_CTR]; |
|
|
*match_register = 1; |
|
|
} else if (name[0] == 'r' && isdigit((int)name[1])) { |
|
|
int nr = atoi(name + 1); |
|
|
if (nr >= 0 && nr < PPC_NGPRS) { |
|
|
if (writeflag) { |
|
|
m->cpus[cpunr]->cd.ppc.gpr[nr] = *valuep; |
|
|
} else |
|
|
*valuep = m->cpus[cpunr]->cd.ppc.gpr[nr]; |
|
|
*match_register = 1; |
|
593 |
} |
} |
594 |
} else if (strcasecmp(name, "xer") == 0) { |
} |
595 |
if (writeflag) |
snprintf(r + strlen(r), maxlen - strlen(r), format, (uint64_t)value); |
596 |
m->cpus[cpunr]->cd.ppc.spr[SPR_XER] = *valuep; |
} |
597 |
else |
|
598 |
*valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_XER]; |
|
599 |
*match_register = 1; |
/* |
600 |
} else if (strcasecmp(name, "fpscr") == 0) { |
* ppc_cpu_gdb_stub(): |
601 |
if (writeflag) |
* |
602 |
m->cpus[cpunr]->cd.ppc.fpscr = *valuep; |
* Execute a "remote GDB" command. Returns a newly allocated response string |
603 |
else |
* on success, NULL on failure. |
604 |
*valuep = m->cpus[cpunr]->cd.ppc.fpscr; |
*/ |
605 |
*match_register = 1; |
char *ppc_cpu_gdb_stub(struct cpu *cpu, char *cmd) |
606 |
} else if (name[0] == 'f' && isdigit((int)name[1])) { |
{ |
607 |
int nr = atoi(name + 1); |
if (strcmp(cmd, "g") == 0) { |
608 |
if (nr >= 0 && nr < PPC_NFPRS) { |
int i; |
609 |
if (writeflag) { |
char *r; |
610 |
m->cpus[cpunr]->cd.ppc.fpr[nr] = *valuep; |
size_t wlen = cpu->is_32bit? |
611 |
} else |
sizeof(uint32_t) : sizeof(uint64_t); |
612 |
*valuep = m->cpus[cpunr]->cd.ppc.fpr[nr]; |
size_t len = 1 + 76 * wlen; |
613 |
*match_register = 1; |
r = malloc(len); |
614 |
|
if (r == NULL) { |
615 |
|
fprintf(stderr, "out of memory\n"); |
616 |
|
exit(1); |
617 |
|
} |
618 |
|
r[0] = '\0'; |
619 |
|
for (i=0; i<128; i++) |
620 |
|
add_response_word(cpu, r, i, len, wlen); |
621 |
|
return r; |
622 |
|
} |
623 |
|
|
624 |
|
if (cmd[0] == 'p') { |
625 |
|
int regnr = strtol(cmd + 1, NULL, 16); |
626 |
|
size_t wlen = cpu->is_32bit? |
627 |
|
sizeof(uint32_t) : sizeof(uint64_t); |
628 |
|
size_t len = 2 * wlen + 1; |
629 |
|
char *r = malloc(len); |
630 |
|
r[0] = '\0'; |
631 |
|
if (regnr >= 0 && regnr <= 31) { |
632 |
|
add_response_word(cpu, r, |
633 |
|
cpu->cd.ppc.gpr[regnr], len, wlen); |
634 |
|
} else if (regnr == 0x40) { |
635 |
|
add_response_word(cpu, r, cpu->pc, len, wlen); |
636 |
|
} else if (regnr == 0x42) { |
637 |
|
add_response_word(cpu, r, cpu->cd.ppc.cr, len, wlen); |
638 |
|
} else if (regnr == 0x43) { |
639 |
|
add_response_word(cpu, r, cpu->cd.ppc.spr[SPR_LR], |
640 |
|
len, wlen); |
641 |
|
} else if (regnr == 0x44) { |
642 |
|
add_response_word(cpu, r, cpu->cd.ppc.spr[SPR_CTR], |
643 |
|
len, wlen); |
644 |
|
} else if (regnr == 0x45) { |
645 |
|
add_response_word(cpu, r, cpu->cd.ppc.spr[SPR_XER], |
646 |
|
len, wlen); |
647 |
|
} else { |
648 |
|
/* Unimplemented: */ |
649 |
|
add_response_word(cpu, r, 0xcc000 + regnr, len, wlen); |
650 |
} |
} |
651 |
|
return r; |
652 |
} |
} |
653 |
|
|
654 |
|
fatal("ppc_cpu_gdb_stub(): TODO\n"); |
655 |
|
return NULL; |
656 |
} |
} |
657 |
|
|
658 |
|
|
711 |
* cpu->pc for relative addresses. |
* cpu->pc for relative addresses. |
712 |
*/ |
*/ |
713 |
int ppc_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr, |
int ppc_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr, |
714 |
int running, uint64_t dumpaddr, int bintrans) |
int running, uint64_t dumpaddr) |
715 |
{ |
{ |
716 |
int hi6, xo, lev, rt, rs, ra, rb, imm, sh, me, rc, l_bit, oe_bit; |
int hi6, xo, lev, rt, rs, ra, rb, imm, sh, me, rc, l_bit, oe_bit; |
717 |
int spr, aa_bit, lk_bit, bf, bh, bi, bo, mb, nb, bt, ba, bb, fpreg; |
int spr, aa_bit, lk_bit, bf, bh, bi, bo, mb, nb, bt, ba, bb, fpreg; |
1005 |
case PPC_HI6_30: |
case PPC_HI6_30: |
1006 |
xo = (iword >> 2) & 7; |
xo = (iword >> 2) & 7; |
1007 |
switch (xo) { |
switch (xo) { |
1008 |
|
case PPC_30_RLDICL: |
1009 |
case PPC_30_RLDICR: |
case PPC_30_RLDICR: |
1010 |
|
case PPC_30_RLDIMI: /* mb, not me */ |
1011 |
|
mnem = NULL; |
1012 |
|
switch (xo) { |
1013 |
|
case PPC_30_RLDICL: mnem = "rldicl"; break; |
1014 |
|
case PPC_30_RLDICR: mnem = "rldicr"; break; |
1015 |
|
case PPC_30_RLDIMI: mnem = "rldimi"; break; |
1016 |
|
} |
1017 |
rs = (iword >> 21) & 31; |
rs = (iword >> 21) & 31; |
1018 |
ra = (iword >> 16) & 31; |
ra = (iword >> 16) & 31; |
1019 |
sh = ((iword >> 11) & 31) | ((iword & 2) << 4); |
sh = ((iword >> 11) & 31) | ((iword & 2) << 4); |
1020 |
me = ((iword >> 6) & 31) | (iword & 0x20); |
me = ((iword >> 6) & 31) | (iword & 0x20); |
1021 |
rc = iword & 1; |
rc = iword & 1; |
1022 |
debug("rldicr%s\tr%i,r%i,%i,%i", |
debug("%s%s\tr%i,r%i,%i,%i", |
1023 |
rc?".":"", ra, rs, sh, me); |
mnem, rc?".":"", ra, rs, sh, me); |
1024 |
break; |
break; |
1025 |
default: |
default: |
1026 |
debug("unimplemented hi6_30, xo = 0x%x", xo); |
debug("unimplemented hi6_30, xo = 0x%x", xo); |
1187 |
case PPC_31_WRTEEI: |
case PPC_31_WRTEEI: |
1188 |
debug("wrteei\t%i", iword & 0x8000? 1 : 0); |
debug("wrteei\t%i", iword & 0x8000? 1 : 0); |
1189 |
break; |
break; |
1190 |
|
case PPC_31_MTMSRD: |
1191 |
|
/* TODO: Just a guess based on MTMSR */ |
1192 |
|
rs = (iword >> 21) & 31; |
1193 |
|
l_bit = (iword >> 16) & 1; |
1194 |
|
debug("mtmsrd\tr%i", rs); |
1195 |
|
if (l_bit) |
1196 |
|
debug(",%i", l_bit); |
1197 |
|
break; |
1198 |
case PPC_31_ADDZE: |
case PPC_31_ADDZE: |
1199 |
case PPC_31_ADDZEO: |
case PPC_31_ADDZEO: |
1200 |
rt = (iword >> 21) & 31; |
rt = (iword >> 21) & 31; |
1415 |
debug("%s\tr%i,r%i", mnem, ra, rb); |
debug("%s\tr%i,r%i", mnem, ra, rb); |
1416 |
break; |
break; |
1417 |
case PPC_31_SLW: |
case PPC_31_SLW: |
1418 |
|
case PPC_31_SLD: |
1419 |
case PPC_31_SRAW: |
case PPC_31_SRAW: |
1420 |
case PPC_31_SRW: |
case PPC_31_SRW: |
1421 |
case PPC_31_AND: |
case PPC_31_AND: |
1422 |
case PPC_31_ANDC: |
case PPC_31_ANDC: |
1423 |
case PPC_31_NOR: |
case PPC_31_NOR: |
1424 |
|
case PPC_31_EQV: |
1425 |
case PPC_31_OR: |
case PPC_31_OR: |
1426 |
case PPC_31_ORC: |
case PPC_31_ORC: |
1427 |
case PPC_31_XOR: |
case PPC_31_XOR: |
1436 |
switch (xo) { |
switch (xo) { |
1437 |
case PPC_31_SLW: mnem = |
case PPC_31_SLW: mnem = |
1438 |
power? "sl" : "slw"; break; |
power? "sl" : "slw"; break; |
1439 |
|
case PPC_31_SLD: mnem = "sld"; break; |
1440 |
case PPC_31_SRAW: mnem = |
case PPC_31_SRAW: mnem = |
1441 |
power? "sra" : "sraw"; break; |
power? "sra" : "sraw"; break; |
1442 |
case PPC_31_SRW: mnem = |
case PPC_31_SRW: mnem = |
1445 |
case PPC_31_NAND: mnem = "nand"; break; |
case PPC_31_NAND: mnem = "nand"; break; |
1446 |
case PPC_31_ANDC: mnem = "andc"; break; |
case PPC_31_ANDC: mnem = "andc"; break; |
1447 |
case PPC_31_NOR: mnem = "nor"; break; |
case PPC_31_NOR: mnem = "nor"; break; |
1448 |
|
case PPC_31_EQV: mnem = "eqv"; break; |
1449 |
case PPC_31_OR: mnem = "or"; break; |
case PPC_31_OR: mnem = "or"; break; |
1450 |
case PPC_31_ORC: mnem = "orc"; break; |
case PPC_31_ORC: mnem = "orc"; break; |
1451 |
case PPC_31_XOR: mnem = "xor"; break; |
case PPC_31_XOR: mnem = "xor"; break; |
1530 |
debug("%s%s\tr%i,r%i,%i", mnem, |
debug("%s%s\tr%i,r%i,%i", mnem, |
1531 |
rc? "." : "", ra, rs, sh); |
rc? "." : "", ra, rs, sh); |
1532 |
break; |
break; |
1533 |
|
case PPC_31_DSSALL: |
1534 |
|
debug("dssall"); |
1535 |
|
break; |
1536 |
case PPC_31_EIEIO: |
case PPC_31_EIEIO: |
1537 |
debug("%s", power? "eieio?" : "eieio"); |
debug("%s", power? "eieio?" : "eieio"); |
1538 |
break; |
break; |
1555 |
} |
} |
1556 |
debug("%s%s\tr%i,r%i", mnem, rc? "." : "", ra, rs); |
debug("%s%s\tr%i,r%i", mnem, rc? "." : "", ra, rs); |
1557 |
break; |
break; |
|
case 359: |
|
|
debug("TODO: ALTIVEC 359"); |
|
|
break; |
|
1558 |
case PPC_31_LVX: |
case PPC_31_LVX: |
1559 |
debug("lvx\tTODO: ALTIVEC"); |
case PPC_31_LVXL: |
|
break; |
|
1560 |
case PPC_31_STVX: |
case PPC_31_STVX: |
|
debug("stvx\tTODO: ALTIVEC"); |
|
|
break; |
|
1561 |
case PPC_31_STVXL: |
case PPC_31_STVXL: |
1562 |
debug("stvxl\tTODO: ALTIVEC"); |
rs = (iword >> 21) & 31; /* vs for stores, */ |
1563 |
|
ra = (iword >> 16) & 31; /* rs=vl for loads */ |
1564 |
|
rb = (iword >> 11) & 31; |
1565 |
|
rc = iword & 1; |
1566 |
|
switch (xo) { |
1567 |
|
case PPC_31_LVX: mnem = "lvx"; break; |
1568 |
|
case PPC_31_LVXL: mnem = "lvxl"; break; |
1569 |
|
case PPC_31_STVX: mnem = "stvx"; break; |
1570 |
|
case PPC_31_STVXL: mnem = "stvxl"; break; |
1571 |
|
} |
1572 |
|
debug("%s%s\tv%i,r%i,r%i", mnem, rc? "." : "", |
1573 |
|
rs, ra, rb); |
1574 |
break; |
break; |
1575 |
default: |
default: |
1576 |
debug("unimplemented hi6_31, xo = 0x%x", xo); |
debug("unimplemented hi6_31, xo = 0x%x", xo); |
1943 |
|
|
1944 |
#include "tmp_ppc_tail.c" |
#include "tmp_ppc_tail.c" |
1945 |
|
|
1946 |
|
|