25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: cpu_ppc.c,v 1.59 2006/06/24 21:47:23 debug Exp $ |
* $Id: cpu_ppc.c,v 1.64 2006/09/21 11:53:26 debug Exp $ |
29 |
* |
* |
30 |
* PowerPC/POWER CPU emulation. |
* PowerPC/POWER CPU emulation. |
31 |
*/ |
*/ |
46 |
#include "ppc_pte.h" |
#include "ppc_pte.h" |
47 |
#include "ppc_spr.h" |
#include "ppc_spr.h" |
48 |
#include "ppc_spr_strings.h" |
#include "ppc_spr_strings.h" |
49 |
|
#include "settings.h" |
50 |
#include "symbol.h" |
#include "symbol.h" |
51 |
|
|
52 |
#define DYNTRANS_DUALMODE_32 |
#define DYNTRANS_DUALMODE_32 |
87 |
|
|
88 |
cpu->memory_rw = ppc_memory_rw; |
cpu->memory_rw = ppc_memory_rw; |
89 |
|
|
90 |
cpu->cd.ppc.cpu_type = cpu_type_defs[found]; |
cpu->cd.ppc.cpu_type = cpu_type_defs[found]; |
91 |
cpu->name = cpu->cd.ppc.cpu_type.name; |
cpu->name = cpu->cd.ppc.cpu_type.name; |
92 |
cpu->byte_order = EMUL_BIG_ENDIAN; |
cpu->byte_order = EMUL_BIG_ENDIAN; |
93 |
cpu->cd.ppc.mode = MODE_PPC; /* TODO */ |
cpu->cd.ppc.mode = MODE_PPC; /* TODO */ |
94 |
|
|
95 |
/* Current operating mode: */ |
/* Current operating mode: */ |
96 |
cpu->cd.ppc.bits = cpu->cd.ppc.cpu_type.bits; |
cpu->cd.ppc.bits = cpu->cd.ppc.cpu_type.bits; |
117 |
cpu->is_32bit = (cpu->cd.ppc.bits == 32)? 1 : 0; |
cpu->is_32bit = (cpu->cd.ppc.bits == 32)? 1 : 0; |
118 |
|
|
119 |
if (cpu->is_32bit) { |
if (cpu->is_32bit) { |
120 |
|
cpu->run_instr = ppc32_run_instr; |
121 |
cpu->update_translation_table = ppc32_update_translation_table; |
cpu->update_translation_table = ppc32_update_translation_table; |
122 |
cpu->invalidate_translation_caches = |
cpu->invalidate_translation_caches = |
123 |
ppc32_invalidate_translation_caches; |
ppc32_invalidate_translation_caches; |
124 |
cpu->invalidate_code_translation = |
cpu->invalidate_code_translation = |
125 |
ppc32_invalidate_code_translation; |
ppc32_invalidate_code_translation; |
126 |
} else { |
} else { |
127 |
|
cpu->run_instr = ppc_run_instr; |
128 |
cpu->update_translation_table = ppc_update_translation_table; |
cpu->update_translation_table = ppc_update_translation_table; |
129 |
cpu->invalidate_translation_caches = |
cpu->invalidate_translation_caches = |
130 |
ppc_invalidate_translation_caches; |
ppc_invalidate_translation_caches; |
169 |
if (cpu->machine->prom_emulation) |
if (cpu->machine->prom_emulation) |
170 |
cpu->cd.ppc.of_emul_addr = 0xfff00000; |
cpu->cd.ppc.of_emul_addr = 0xfff00000; |
171 |
|
|
172 |
|
/* Add all register names to the settings: */ |
173 |
|
CPU_SETTINGS_ADD_REGISTER64("pc", cpu->pc); |
174 |
|
CPU_SETTINGS_ADD_REGISTER64("msr", cpu->cd.ppc.msr); |
175 |
|
CPU_SETTINGS_ADD_REGISTER64("ctr", cpu->cd.ppc.spr[SPR_CTR]); |
176 |
|
CPU_SETTINGS_ADD_REGISTER64("xer", cpu->cd.ppc.spr[SPR_XER]); |
177 |
|
CPU_SETTINGS_ADD_REGISTER64("dec", cpu->cd.ppc.spr[SPR_DEC]); |
178 |
|
CPU_SETTINGS_ADD_REGISTER64("hdec", cpu->cd.ppc.spr[SPR_HDEC]); |
179 |
|
CPU_SETTINGS_ADD_REGISTER64("srr0", cpu->cd.ppc.spr[SPR_SRR0]); |
180 |
|
CPU_SETTINGS_ADD_REGISTER64("srr1", cpu->cd.ppc.spr[SPR_SRR1]); |
181 |
|
CPU_SETTINGS_ADD_REGISTER64("sdr1", cpu->cd.ppc.spr[SPR_SDR1]); |
182 |
|
CPU_SETTINGS_ADD_REGISTER64("ibat0u", cpu->cd.ppc.spr[SPR_IBAT0U]); |
183 |
|
CPU_SETTINGS_ADD_REGISTER64("ibat0l", cpu->cd.ppc.spr[SPR_IBAT0L]); |
184 |
|
CPU_SETTINGS_ADD_REGISTER64("ibat1u", cpu->cd.ppc.spr[SPR_IBAT1U]); |
185 |
|
CPU_SETTINGS_ADD_REGISTER64("ibat1l", cpu->cd.ppc.spr[SPR_IBAT1L]); |
186 |
|
CPU_SETTINGS_ADD_REGISTER64("ibat2u", cpu->cd.ppc.spr[SPR_IBAT2U]); |
187 |
|
CPU_SETTINGS_ADD_REGISTER64("ibat2l", cpu->cd.ppc.spr[SPR_IBAT2L]); |
188 |
|
CPU_SETTINGS_ADD_REGISTER64("ibat3u", cpu->cd.ppc.spr[SPR_IBAT3U]); |
189 |
|
CPU_SETTINGS_ADD_REGISTER64("ibat3l", cpu->cd.ppc.spr[SPR_IBAT3L]); |
190 |
|
CPU_SETTINGS_ADD_REGISTER64("dbat0u", cpu->cd.ppc.spr[SPR_DBAT0U]); |
191 |
|
CPU_SETTINGS_ADD_REGISTER64("dbat0l", cpu->cd.ppc.spr[SPR_DBAT0L]); |
192 |
|
CPU_SETTINGS_ADD_REGISTER64("dbat1u", cpu->cd.ppc.spr[SPR_DBAT1U]); |
193 |
|
CPU_SETTINGS_ADD_REGISTER64("dbat1l", cpu->cd.ppc.spr[SPR_DBAT1L]); |
194 |
|
CPU_SETTINGS_ADD_REGISTER64("dbat2u", cpu->cd.ppc.spr[SPR_DBAT2U]); |
195 |
|
CPU_SETTINGS_ADD_REGISTER64("dbat2l", cpu->cd.ppc.spr[SPR_DBAT2L]); |
196 |
|
CPU_SETTINGS_ADD_REGISTER64("dbat3u", cpu->cd.ppc.spr[SPR_DBAT3U]); |
197 |
|
CPU_SETTINGS_ADD_REGISTER64("dbat3l", cpu->cd.ppc.spr[SPR_DBAT3L]); |
198 |
|
CPU_SETTINGS_ADD_REGISTER64("lr", cpu->cd.ppc.spr[SPR_LR]); |
199 |
|
CPU_SETTINGS_ADD_REGISTER32("cr", cpu->cd.ppc.cr); |
200 |
|
CPU_SETTINGS_ADD_REGISTER32("fpscr", cpu->cd.ppc.fpscr); |
201 |
|
/* Integer GPRs, floating point registers, and segment registers: */ |
202 |
|
for (i=0; i<PPC_NGPRS; i++) { |
203 |
|
char tmpstr[5]; |
204 |
|
snprintf(tmpstr, sizeof(tmpstr), "r%i", i); |
205 |
|
CPU_SETTINGS_ADD_REGISTER64(tmpstr, cpu->cd.ppc.gpr[i]); |
206 |
|
} |
207 |
|
for (i=0; i<PPC_NFPRS; i++) { |
208 |
|
char tmpstr[5]; |
209 |
|
snprintf(tmpstr, sizeof(tmpstr), "f%i", i); |
210 |
|
CPU_SETTINGS_ADD_REGISTER64(tmpstr, cpu->cd.ppc.fpr[i]); |
211 |
|
} |
212 |
|
for (i=0; i<16; i++) { |
213 |
|
char tmpstr[5]; |
214 |
|
snprintf(tmpstr, sizeof(tmpstr), "sr%i", i); |
215 |
|
CPU_SETTINGS_ADD_REGISTER32(tmpstr, cpu->cd.ppc.sr[i]); |
216 |
|
} |
217 |
|
|
218 |
return 1; |
return 1; |
219 |
} |
} |
220 |
|
|
319 |
*valuep = cpu->cd.ppc.msr; |
*valuep = cpu->cd.ppc.msr; |
320 |
|
|
321 |
if (check_for_interrupts && cpu->cd.ppc.msr & PPC_MSR_EE) { |
if (check_for_interrupts && cpu->cd.ppc.msr & PPC_MSR_EE) { |
322 |
if (cpu->cd.ppc.dec_intr_pending) { |
if (cpu->cd.ppc.dec_intr_pending && |
323 |
|
!(cpu->cd.ppc.cpu_type.flags & PPC_NO_DEC)) { |
324 |
ppc_exception(cpu, PPC_EXCEPTION_DEC); |
ppc_exception(cpu, PPC_EXCEPTION_DEC); |
325 |
cpu->cd.ppc.dec_intr_pending = 0; |
cpu->cd.ppc.dec_intr_pending = 0; |
326 |
} else if (cpu->cd.ppc.irq_asserted) |
} else if (cpu->cd.ppc.irq_asserted) |
527 |
for (i=0; i<16; i++) { |
for (i=0; i<16; i++) { |
528 |
uint32_t s = cpu->cd.ppc.sr[i]; |
uint32_t s = cpu->cd.ppc.sr[i]; |
529 |
debug("cpu%i:", x); |
debug("cpu%i:", x); |
530 |
debug(" sr%2i = 0x%08x", i, (int)s); |
debug(" sr%-2i = 0x%08x", i, (int)s); |
531 |
s &= (SR_TYPE | SR_SUKEY | SR_PRKEY | SR_NOEXEC); |
s &= (SR_TYPE | SR_SUKEY | SR_PRKEY | SR_NOEXEC); |
532 |
if (s != 0) { |
if (s != 0) { |
533 |
debug(" ("); |
debug(" ("); |
557 |
} |
} |
558 |
} |
} |
559 |
} |
} |
|
|
|
|
|
|
|
/* |
|
|
* ppc_cpu_register_match(): |
|
|
*/ |
|
|
void ppc_cpu_register_match(struct machine *m, char *name, |
|
|
int writeflag, uint64_t *valuep, int *match_register) |
|
|
{ |
|
|
int cpunr = 0; |
|
|
|
|
|
/* CPU number: */ |
|
|
|
|
|
/* TODO */ |
|
|
|
|
|
/* Register name: */ |
|
|
if (strcasecmp(name, "pc") == 0) { |
|
|
if (writeflag) { |
|
|
m->cpus[cpunr]->pc = *valuep; |
|
|
} else |
|
|
*valuep = m->cpus[cpunr]->pc; |
|
|
*match_register = 1; |
|
|
} else if (strcasecmp(name, "msr") == 0) { |
|
|
if (writeflag) |
|
|
m->cpus[cpunr]->cd.ppc.msr = *valuep; |
|
|
else |
|
|
*valuep = m->cpus[cpunr]->cd.ppc.msr; |
|
|
*match_register = 1; |
|
|
} else if (strcasecmp(name, "lr") == 0) { |
|
|
if (writeflag) |
|
|
m->cpus[cpunr]->cd.ppc.spr[SPR_LR] = *valuep; |
|
|
else |
|
|
*valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_LR]; |
|
|
*match_register = 1; |
|
|
} else if (strcasecmp(name, "cr") == 0) { |
|
|
if (writeflag) |
|
|
m->cpus[cpunr]->cd.ppc.cr = *valuep; |
|
|
else |
|
|
*valuep = m->cpus[cpunr]->cd.ppc.cr; |
|
|
*match_register = 1; |
|
|
} else if (strcasecmp(name, "dec") == 0) { |
|
|
if (writeflag) |
|
|
m->cpus[cpunr]->cd.ppc.spr[SPR_DEC] = *valuep; |
|
|
else |
|
|
*valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_DEC]; |
|
|
*match_register = 1; |
|
|
} else if (strcasecmp(name, "hdec") == 0) { |
|
|
if (writeflag) |
|
|
m->cpus[cpunr]->cd.ppc.spr[SPR_HDEC] = *valuep; |
|
|
else |
|
|
*valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_HDEC]; |
|
|
*match_register = 1; |
|
|
} else if (strcasecmp(name, "ctr") == 0) { |
|
|
if (writeflag) |
|
|
m->cpus[cpunr]->cd.ppc.spr[SPR_CTR] = *valuep; |
|
|
else |
|
|
*valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_CTR]; |
|
|
*match_register = 1; |
|
|
} else if (name[0] == 'r' && isdigit((int)name[1])) { |
|
|
int nr = atoi(name + 1); |
|
|
if (nr >= 0 && nr < PPC_NGPRS) { |
|
|
if (writeflag) { |
|
|
m->cpus[cpunr]->cd.ppc.gpr[nr] = *valuep; |
|
|
} else |
|
|
*valuep = m->cpus[cpunr]->cd.ppc.gpr[nr]; |
|
|
*match_register = 1; |
|
|
} |
|
|
} else if (strcasecmp(name, "xer") == 0) { |
|
|
if (writeflag) |
|
|
m->cpus[cpunr]->cd.ppc.spr[SPR_XER] = *valuep; |
|
|
else |
|
|
*valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_XER]; |
|
|
*match_register = 1; |
|
|
} else if (strcasecmp(name, "fpscr") == 0) { |
|
|
if (writeflag) |
|
|
m->cpus[cpunr]->cd.ppc.fpscr = *valuep; |
|
|
else |
|
|
*valuep = m->cpus[cpunr]->cd.ppc.fpscr; |
|
|
*match_register = 1; |
|
|
} else if (name[0] == 'f' && isdigit((int)name[1])) { |
|
|
int nr = atoi(name + 1); |
|
|
if (nr >= 0 && nr < PPC_NFPRS) { |
|
|
if (writeflag) { |
|
|
m->cpus[cpunr]->cd.ppc.fpr[nr] = *valuep; |
|
|
} else |
|
|
*valuep = m->cpus[cpunr]->cd.ppc.fpr[nr]; |
|
|
*match_register = 1; |
|
|
} |
|
|
} |
|
|
} |
|
560 |
|
|
561 |
|
|
562 |
/* |
/* |