--- trunk/src/cpus/cpu_ppc.c	2007/10/08 16:19:23	20
+++ trunk/src/cpus/cpu_ppc.c	2007/10/08 16:19:37	22
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2005  Anders Gavare.  All rights reserved.
+ *  Copyright (C) 2005-2006  Anders Gavare.  All rights reserved.
  *
  *  Redistribution and use in source and binary forms, with or without
  *  modification, are permitted provided that the following conditions are met:
@@ -25,7 +25,7 @@
  *  SUCH DAMAGE.
  *
  *
- *  $Id: cpu_ppc.c,v 1.35 2005/11/24 01:15:06 debug Exp $
+ *  $Id: cpu_ppc.c,v 1.45 2006/01/24 21:26:01 debug Exp $
  *
  *  PowerPC/POWER CPU emulation.
  */
@@ -40,6 +40,7 @@
 #include "machine.h"
 #include "memory.h"
 #include "misc.h"
+#include "of.h"
 #include "opcodes_ppc.h"
 #include "ppc_bat.h"
 #include "ppc_pte.h"
@@ -94,6 +95,21 @@
 	cpu->cd.ppc.bits = cpu->cd.ppc.cpu_type.bits;
 	cpu->cd.ppc.spr[SPR_PVR] = cpu->cd.ppc.cpu_type.pvr;
 
+	cpu->cd.ppc.spr[SPR_IBAT0U] = 0x00001ffc | BAT_Vs;
+	cpu->cd.ppc.spr[SPR_IBAT0L] = 0x00000000 | BAT_PP_RW;
+	cpu->cd.ppc.spr[SPR_IBAT1U] = 0xc0001ffc | BAT_Vs;
+	cpu->cd.ppc.spr[SPR_IBAT1L] = 0x00000000 | BAT_PP_RW;
+	cpu->cd.ppc.spr[SPR_IBAT3U] = 0xf0001ffc | BAT_Vs;
+	cpu->cd.ppc.spr[SPR_IBAT3L] = 0xf0000000 | BAT_PP_RW;
+	cpu->cd.ppc.spr[SPR_DBAT0U] = 0x00001ffc | BAT_Vs;
+	cpu->cd.ppc.spr[SPR_DBAT0L] = 0x00000000 | BAT_PP_RW;
+	cpu->cd.ppc.spr[SPR_DBAT1U] = 0xc0001ffc | BAT_Vs;
+	cpu->cd.ppc.spr[SPR_DBAT1L] = 0x00000000 | BAT_PP_RW;
+	cpu->cd.ppc.spr[SPR_DBAT2U] = 0xe0001ffc | BAT_Vs;
+	cpu->cd.ppc.spr[SPR_DBAT2L] = 0xe0000000 | BAT_PP_RW;
+	cpu->cd.ppc.spr[SPR_DBAT3U] = 0xf0001ffc | BAT_Vs;
+	cpu->cd.ppc.spr[SPR_DBAT3L] = 0xf0000000 | BAT_PP_RW;
+
 	cpu->is_32bit = (cpu->cd.ppc.bits == 32)? 1 : 0;
 
 	if (cpu->is_32bit) {
@@ -284,7 +300,7 @@
 
 	cpu->pc = exception_nr * 0x100;
 	if (cpu->cd.ppc.msr & PPC_MSR_IP)
-		cpu->pc += 0xfff00000;
+		cpu->pc += 0xfff00000ULL;
 
 	if (cpu->is_32bit)
 		ppc32_pc_to_pointers(cpu);
@@ -325,9 +341,13 @@
 			debug("%08x", (int)cpu->cd.ppc.spr[SPR_LR]);
 		else
 			debug("%016llx", (long long)cpu->cd.ppc.spr[SPR_LR]);
-		debug("  cr  = 0x%08x\n", (int)cpu->cd.ppc.cr);
+		debug("  cr  = 0x%08x", (int)cpu->cd.ppc.cr);
 
-		debug("cpu%i: ctr = 0x", x);
+		if (bits32)
+			debug("  ");
+		else
+			debug("\ncpu%i: ", x);
+		debug("ctr = 0x", x);
 		if (bits32)
 			debug("%08x", (int)cpu->cd.ppc.spr[SPR_CTR]);
 		else
@@ -363,16 +383,28 @@
 		}
 
 		/*  Other special registers:  */
-		debug("cpu%i: srr0 = 0x%016llx  srr1 = 0x%016llx\n", x,
-		    (long long)cpu->cd.ppc.spr[SPR_SRR0],
-		    (long long)cpu->cd.ppc.spr[SPR_SRR1]);
+		if (bits32) {
+			debug("cpu%i: srr0 = 0x%08x srr1 = 0x%08x\n", x,
+			    (int)cpu->cd.ppc.spr[SPR_SRR0],
+			    (int)cpu->cd.ppc.spr[SPR_SRR1]);
+		} else {
+			debug("cpu%i: srr0 = 0x%016llx  srr1 = 0x%016llx\n", x,
+			    (long long)cpu->cd.ppc.spr[SPR_SRR0],
+			    (long long)cpu->cd.ppc.spr[SPR_SRR1]);
+		}
+		debug("cpu%i: msr = ", x);
 		reg_access_msr(cpu, &tmp, 0, 0);
-		debug("cpu%i: msr = 0x%016llx  ", x, (long long)tmp);
+		if (bits32)
+			debug("0x%08x  ", (int)tmp);
+		else
+			debug("0x%016llx  ", (long long)tmp);
 		debug("tb  = 0x%08x%08x\n", (int)cpu->cd.ppc.spr[SPR_TBU],
 		    (int)cpu->cd.ppc.spr[SPR_TBL]);
-		debug("cpu%i: dec = 0x%08x  hdec = 0x%08x\n",
-		    x, (int)cpu->cd.ppc.spr[SPR_DEC],
-		    (int)cpu->cd.ppc.spr[SPR_HDEC]);
+		debug("cpu%i: dec = 0x%08x", x, (int)cpu->cd.ppc.spr[SPR_DEC]);
+		if (!bits32)
+			debug("  hdec = 0x%08x\n",
+			    (int)cpu->cd.ppc.spr[SPR_HDEC]);
+		debug("\n");
 	}
 
 	if (coprocs & 1) {
@@ -655,6 +687,10 @@
 	hi6 = iword >> 26;
 
 	switch (hi6) {
+	case 0x4:
+		debug("ALTIVEC TODO");
+		/*  vxor etc  */
+		break;
 	case PPC_HI6_MULLI:
 	case PPC_HI6_SUBFIC:
 		rt = (iword >> 21) & 31;
@@ -1077,6 +1113,9 @@
 			}
 			debug("%s%s\tr%i,r%i", mnem, rc? "." : "", rt, ra);
 			break;
+		case PPC_31_WRTEEI:
+			debug("wrteei\t%i", iword & 0x8000? 1 : 0);
+			break;
 		case PPC_31_ADDZE:
 		case PPC_31_ADDZEO:
 			rt = (iword >> 21) & 31;
@@ -1247,6 +1286,12 @@
 			else
 				debug("tlbie\tr%i", rb);
 			break;
+		case PPC_31_TLBSX_DOT:
+			rs = (iword >> 21) & 31;
+			ra = (iword >> 16) & 31;
+			rb = (iword >> 11) & 31;
+			debug("tlbsx.\tr%i,r%i,r%i", rs, ra, rb);
+			break;
 		case PPC_31_TLBSYNC:
 			debug("tlbsync");
 			break;
@@ -1424,6 +1469,18 @@
 			}
 			debug("%s%s\tr%i,r%i", mnem, rc? "." : "", ra, rs);
 			break;
+		case 359:
+			debug("TODO: ALTIVEC 359");
+			break;
+		case PPC_31_LVX:
+			debug("lvx\tTODO: ALTIVEC");
+			break;
+		case PPC_31_STVX:
+			debug("stvx\tTODO: ALTIVEC");
+			break;
+		case PPC_31_STVXL:
+			debug("stvxl\tTODO: ALTIVEC");
+			break;
 		default:
 			debug("unimplemented hi6_31, xo = 0x%x", xo);
 		}