--- trunk/src/cpus/cpu_ppc.c	2007/10/08 16:18:51	14
+++ trunk/src/cpus/cpu_ppc.c	2007/10/08 16:20:26	28
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2005  Anders Gavare.  All rights reserved.
+ *  Copyright (C) 2005-2006  Anders Gavare.  All rights reserved.
  *
  *  Redistribution and use in source and binary forms, with or without
  *  modification, are permitted provided that the following conditions are met:
@@ -25,7 +25,7 @@
  *  SUCH DAMAGE.
  *
  *
- *  $Id: cpu_ppc.c,v 1.12 2005/09/24 23:44:18 debug Exp $
+ *  $Id: cpu_ppc.c,v 1.60 2006/07/16 13:32:26 debug Exp $
  *
  *  PowerPC/POWER CPU emulation.
  */
@@ -40,13 +40,22 @@
 #include "machine.h"
 #include "memory.h"
 #include "misc.h"
+#include "of.h"
 #include "opcodes_ppc.h"
+#include "ppc_bat.h"
+#include "ppc_pte.h"
+#include "ppc_spr.h"
+#include "ppc_spr_strings.h"
 #include "symbol.h"
 
 #define	DYNTRANS_DUALMODE_32
 #include "tmp_ppc_head.c"
 
 
+void ppc_pc_to_pointers(struct cpu *);
+void ppc32_pc_to_pointers(struct cpu *);
+
+
 /*
  *  ppc_cpu_new():
  *
@@ -84,25 +93,45 @@
 
 	/*  Current operating mode:  */
 	cpu->cd.ppc.bits = cpu->cd.ppc.cpu_type.bits;
-	cpu->cd.ppc.pvr = cpu->cd.ppc.cpu_type.pvr;
+	cpu->cd.ppc.spr[SPR_PVR] = cpu->cd.ppc.cpu_type.pvr;
+
+	/*  cpu->cd.ppc.msr = PPC_MSR_IR | PPC_MSR_DR |
+	    PPC_MSR_SF | PPC_MSR_FP;  */
+
+	cpu->cd.ppc.spr[SPR_IBAT0U] = 0x00001ffc | BAT_Vs;
+	cpu->cd.ppc.spr[SPR_IBAT0L] = 0x00000000 | BAT_PP_RW;
+	cpu->cd.ppc.spr[SPR_IBAT1U] = 0xc0001ffc | BAT_Vs;
+	cpu->cd.ppc.spr[SPR_IBAT1L] = 0x00000000 | BAT_PP_RW;
+	cpu->cd.ppc.spr[SPR_IBAT3U] = 0xf0001ffc | BAT_Vs;
+	cpu->cd.ppc.spr[SPR_IBAT3L] = 0xf0000000 | BAT_PP_RW;
+	cpu->cd.ppc.spr[SPR_DBAT0U] = 0x00001ffc | BAT_Vs;
+	cpu->cd.ppc.spr[SPR_DBAT0L] = 0x00000000 | BAT_PP_RW;
+	cpu->cd.ppc.spr[SPR_DBAT1U] = 0xc0001ffc | BAT_Vs;
+	cpu->cd.ppc.spr[SPR_DBAT1L] = 0x00000000 | BAT_PP_RW;
+	cpu->cd.ppc.spr[SPR_DBAT2U] = 0xe0001ffc | BAT_Vs;
+	cpu->cd.ppc.spr[SPR_DBAT2L] = 0xe0000000 | BAT_PP_RW;
+	cpu->cd.ppc.spr[SPR_DBAT3U] = 0xf0001ffc | BAT_Vs;
+	cpu->cd.ppc.spr[SPR_DBAT3L] = 0xf0000000 | BAT_PP_RW;
 
 	cpu->is_32bit = (cpu->cd.ppc.bits == 32)? 1 : 0;
 
 	if (cpu->is_32bit) {
+		cpu->run_instr = ppc32_run_instr;
 		cpu->update_translation_table = ppc32_update_translation_table;
-		cpu->invalidate_translation_caches_paddr =
-		    ppc32_invalidate_translation_caches_paddr;
+		cpu->invalidate_translation_caches =
+		    ppc32_invalidate_translation_caches;
 		cpu->invalidate_code_translation =
 		    ppc32_invalidate_code_translation;
 	} else {
+		cpu->run_instr = ppc_run_instr;
 		cpu->update_translation_table = ppc_update_translation_table;
-		cpu->invalidate_translation_caches_paddr =
-		    ppc_invalidate_translation_caches_paddr;
+		cpu->invalidate_translation_caches =
+		    ppc_invalidate_translation_caches;
 		cpu->invalidate_code_translation =
 		    ppc_invalidate_code_translation;
 	}
 
-	cpu->translate_address = ppc_translate_address;
+	cpu->translate_v2p = ppc_translate_v2p;
 
 	/*  Only show name and caches etc for CPU nr 0 (in SMP machines):  */
 	if (cpu_id == 0) {
@@ -128,7 +157,7 @@
 		}
 	}
 
-	cpu->cd.ppc.pir = cpu_id;
+	cpu->cd.ppc.spr[SPR_PIR] = cpu_id;
 
 	/*  Some default stack pointer value.  TODO: move this?  */
 	cpu->cd.ppc.gpr[1] = machine->physical_ram_in_mb * 1048576 - 4096;
@@ -203,16 +232,36 @@
 /*
  *  reg_access_msr():
  */
-void reg_access_msr(struct cpu *cpu, uint64_t *valuep, int writeflag)
+void reg_access_msr(struct cpu *cpu, uint64_t *valuep, int writeflag,
+	int check_for_interrupts)
 {
+	uint64_t old = cpu->cd.ppc.msr;
+
 	if (valuep == NULL) {
 		fatal("reg_access_msr(): NULL\n");
 		return;
 	}
 
-	if (writeflag)
+	if (writeflag) {
 		cpu->cd.ppc.msr = *valuep;
 
+		/*  Switching between temporary and real gpr 0..3?  */
+		if ((old & PPC_MSR_TGPR) != (cpu->cd.ppc.msr & PPC_MSR_TGPR)) {
+			int i;
+			for (i=0; i<PPC_N_TGPRS; i++) {
+				uint64_t t = cpu->cd.ppc.gpr[i];
+				cpu->cd.ppc.gpr[i] = cpu->cd.ppc.tgpr[i];
+				cpu->cd.ppc.tgpr[i] = t;
+			}
+		}
+
+		if (cpu->cd.ppc.msr & PPC_MSR_IP) {
+			fatal("\n[ Reboot hack for NetBSD/prep. TODO: "
+			    "fix this. ]\n");
+			cpu->running = 0;
+		}
+	}
+
 	/*  TODO: Is the little-endian bit writable?  */
 
 	cpu->cd.ppc.msr &= ~PPC_MSR_LE;
@@ -221,6 +270,47 @@
 
 	if (!writeflag)
 		*valuep = cpu->cd.ppc.msr;
+
+	if (check_for_interrupts && cpu->cd.ppc.msr & PPC_MSR_EE) {
+		if (cpu->cd.ppc.dec_intr_pending) {
+			ppc_exception(cpu, PPC_EXCEPTION_DEC);
+			cpu->cd.ppc.dec_intr_pending = 0;
+		} else if (cpu->cd.ppc.irq_asserted)
+			ppc_exception(cpu, PPC_EXCEPTION_EI);
+	}
+}
+
+
+/*
+ *  ppc_exception():
+ */
+void ppc_exception(struct cpu *cpu, int exception_nr)
+{
+	/*  Save PC and MSR:  */
+	cpu->cd.ppc.spr[SPR_SRR0] = cpu->pc;
+
+	if (exception_nr >= 0x10 && exception_nr <= 0x13)
+		cpu->cd.ppc.spr[SPR_SRR1] = (cpu->cd.ppc.msr & 0xffff)
+		    | (cpu->cd.ppc.cr & 0xf0000000);
+	else
+		cpu->cd.ppc.spr[SPR_SRR1] = (cpu->cd.ppc.msr & 0x87c0ffff);
+
+	if (!quiet_mode)
+		fatal("[ PPC Exception 0x%x; pc=0x%"PRIx64" ]\n", exception_nr,
+		    (long long)cpu->pc);
+
+	/*  Disable External Interrupts, Recoverable Interrupt Mode,
+	    and go to Supervisor mode  */
+	cpu->cd.ppc.msr &= ~(PPC_MSR_EE | PPC_MSR_RI | PPC_MSR_PR);
+
+	cpu->pc = exception_nr * 0x100;
+	if (cpu->cd.ppc.msr & PPC_MSR_IP)
+		cpu->pc += 0xfff00000ULL;
+
+	if (cpu->is_32bit)
+		ppc32_pc_to_pointers(cpu);
+	else
+		ppc_pc_to_pointers(cpu);
 }
 
 
@@ -246,29 +336,35 @@
 
 		debug("cpu%i: pc  = 0x", x);
 		if (bits32)
-			debug("%08x", (int)cpu->pc);
+			debug("%08"PRIx32, (uint32_t)cpu->pc);
 		else
-			debug("%016llx", (long long)cpu->pc);
+			debug("%016"PRIx64, (uint64_t)cpu->pc);
 		debug("  <%s>\n", symbol != NULL? symbol : " no symbol ");
 
 		debug("cpu%i: lr  = 0x", x);
 		if (bits32)
-			debug("%08x", (int)cpu->cd.ppc.lr);
+			debug("%08"PRIx32, (uint32_t)cpu->cd.ppc.spr[SPR_LR]);
 		else
-			debug("%016llx", (long long)cpu->cd.ppc.lr);
-		debug("  cr  = 0x%08x\n", (int)cpu->cd.ppc.cr);
+			debug("%016"PRIx64, (uint64_t)cpu->cd.ppc.spr[SPR_LR]);
+		debug("  cr  = 0x%08"PRIx32, (uint32_t)cpu->cd.ppc.cr);
 
-		debug("cpu%i: ctr = 0x", x);
 		if (bits32)
-			debug("%08x", (int)cpu->cd.ppc.ctr);
+			debug("  ");
+		else
+			debug("\ncpu%i: ", x);
+		debug("ctr = 0x", x);
+		if (bits32)
+			debug("%08"PRIx32, (uint32_t)cpu->cd.ppc.spr[SPR_CTR]);
 		else
-			debug("%016llx", (long long)cpu->cd.ppc.ctr);
+			debug("%016"PRIx64, (uint64_t)cpu->cd.ppc.spr[SPR_CTR]);
 
 		debug("  xer = 0x", x);
 		if (bits32)
-			debug("%08x\n", (int)cpu->cd.ppc.xer);
+			debug("%08"PRIx32, (uint32_t)cpu->cd.ppc.spr[SPR_XER]);
 		else
-			debug("%016llx\n", (long long)cpu->cd.ppc.xer);
+			debug("%016"PRIx64, (uint64_t)cpu->cd.ppc.spr[SPR_XER]);
+
+		debug("\n");
 
 		if (bits32) {
 			/*  32-bit:  */
@@ -294,14 +390,28 @@
 		}
 
 		/*  Other special registers:  */
-		debug("cpu%i: srr0 = 0x%016llx  srr1 = 0x%016llx\n", x,
-		    (long long)cpu->cd.ppc.srr0, (long long)cpu->cd.ppc.srr1);
-		reg_access_msr(cpu, &tmp, 0);
-		debug("cpu%i: msr = 0x%016llx  ", x, (long long)tmp);
-		debug("tb  = 0x%08x%08x\n",
-		    (int)cpu->cd.ppc.tbu, (int)cpu->cd.ppc.tbl);
-		debug("cpu%i: dec = 0x%08x  hdec = 0x%08x\n",
-		    x, (int)cpu->cd.ppc.dec, (int)cpu->cd.ppc.hdec);
+		if (bits32) {
+			debug("cpu%i: srr0 = 0x%08x srr1 = 0x%08x\n", x,
+			    (int)cpu->cd.ppc.spr[SPR_SRR0],
+			    (int)cpu->cd.ppc.spr[SPR_SRR1]);
+		} else {
+			debug("cpu%i: srr0 = 0x%016llx  srr1 = 0x%016llx\n", x,
+			    (long long)cpu->cd.ppc.spr[SPR_SRR0],
+			    (long long)cpu->cd.ppc.spr[SPR_SRR1]);
+		}
+		debug("cpu%i: msr = ", x);
+		reg_access_msr(cpu, &tmp, 0, 0);
+		if (bits32)
+			debug("0x%08x  ", (int)tmp);
+		else
+			debug("0x%016llx  ", (long long)tmp);
+		debug("tb  = 0x%08x%08x\n", (int)cpu->cd.ppc.spr[SPR_TBU],
+		    (int)cpu->cd.ppc.spr[SPR_TBL]);
+		debug("cpu%i: dec = 0x%08x", x, (int)cpu->cd.ppc.spr[SPR_DEC]);
+		if (!bits32)
+			debug("  hdec = 0x%08x\n",
+			    (int)cpu->cd.ppc.spr[SPR_HDEC]);
+		debug("\n");
 	}
 
 	if (coprocs & 1) {
@@ -323,15 +433,80 @@
 
 	if (coprocs & 2) {
 		debug("cpu%i:  sdr1 = 0x%llx\n", x,
-		    (long long)cpu->cd.ppc.sdr1);
-		for (i=0; i<4; i++)
-			debug("cpu%i:  ibat%iu = 0x%08x  ibat%il = 0x%08x\n",
-			    x, i, cpu->cd.ppc.ibat_u[i],
-			    i, cpu->cd.ppc.ibat_l[i]);
-		for (i=0; i<4; i++)
-			debug("cpu%i:  dbat%iu = 0x%08x  dbat%il = 0x%08x\n",
-			    x, i, cpu->cd.ppc.dbat_u[i],
-			    i, cpu->cd.ppc.dbat_l[i]);
+		    (long long)cpu->cd.ppc.spr[SPR_SDR1]);
+		if (cpu->cd.ppc.cpu_type.flags & PPC_601)
+			debug("cpu%i:  PPC601-style, TODO!\n");
+		else {
+			for (i=0; i<8; i++) {
+				int spr = SPR_IBAT0U + i*2;
+				uint32_t upper = cpu->cd.ppc.spr[spr];
+				uint32_t lower = cpu->cd.ppc.spr[spr+1];
+				uint32_t len = (((upper & BAT_BL) << 15)
+				    | 0x1ffff) + 1;
+				debug("cpu%i:  %sbat%i: u=0x%08x l=0x%08x ",
+				    x, i<4? "i" : "d", i&3, upper, lower);
+				if (!(upper & BAT_V)) {
+					debug(" (not valid)\n");
+					continue;
+				}
+				if (len < 1048576)
+					debug(" (%i KB, ", len >> 10);
+				else
+					debug(" (%i MB, ", len >> 20);
+				if (upper & BAT_Vu)
+					debug("user, ");
+				if (upper & BAT_Vs)
+					debug("supervisor, ");
+				if (lower & (BAT_W | BAT_I | BAT_M | BAT_G))
+					debug("%s%s%s%s, ",
+					    lower & BAT_W? "W" : "",
+					    lower & BAT_I? "I" : "",
+					    lower & BAT_M? "M" : "",
+					    lower & BAT_G? "G" : "");
+				switch (lower & BAT_PP) {
+				case BAT_PP_NONE: debug("NO access"); break;
+				case BAT_PP_RO_S: debug("read-only, soft");
+					          break;
+				case BAT_PP_RO:   debug("read-only"); break;
+				case BAT_PP_RW:   debug("read/write"); break;
+				}
+				debug(")\n");
+			}
+		}
+	}
+
+	if (coprocs & 4) {
+		for (i=0; i<16; i++) {
+			uint32_t s = cpu->cd.ppc.sr[i];
+			debug("cpu%i:", x);
+			debug("  sr%2i = 0x%08x", i, (int)s);
+			s &= (SR_TYPE | SR_SUKEY | SR_PRKEY | SR_NOEXEC);
+			if (s != 0) {
+				debug("  (");
+				if (s & SR_TYPE) {
+					debug("NON-memory type");
+					s &= ~SR_TYPE;
+					if (s != 0)
+						debug(", ");
+				}
+				if (s & SR_SUKEY) {
+					debug("supervisor-key");
+					s &= ~SR_SUKEY;
+					if (s != 0)
+						debug(", ");
+				}
+				if (s & SR_PRKEY) {
+					debug("user-key");
+					s &= ~SR_PRKEY;
+					if (s != 0)
+						debug(", ");
+				}
+				if (s & SR_NOEXEC)
+					debug("NOEXEC");
+				debug(")");
+			}
+			debug("\n");
+		}
 	}
 }
 
@@ -363,9 +538,9 @@
 		*match_register = 1;
 	} else if (strcasecmp(name, "lr") == 0) {
 		if (writeflag)
-			m->cpus[cpunr]->cd.ppc.lr = *valuep;
+			m->cpus[cpunr]->cd.ppc.spr[SPR_LR] = *valuep;
 		else
-			*valuep = m->cpus[cpunr]->cd.ppc.lr;
+			*valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_LR];
 		*match_register = 1;
 	} else if (strcasecmp(name, "cr") == 0) {
 		if (writeflag)
@@ -375,21 +550,21 @@
 		*match_register = 1;
 	} else if (strcasecmp(name, "dec") == 0) {
 		if (writeflag)
-			m->cpus[cpunr]->cd.ppc.dec = *valuep;
+			m->cpus[cpunr]->cd.ppc.spr[SPR_DEC] = *valuep;
 		else
-			*valuep = m->cpus[cpunr]->cd.ppc.dec;
+			*valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_DEC];
 		*match_register = 1;
 	} else if (strcasecmp(name, "hdec") == 0) {
 		if (writeflag)
-			m->cpus[cpunr]->cd.ppc.hdec = *valuep;
+			m->cpus[cpunr]->cd.ppc.spr[SPR_HDEC] = *valuep;
 		else
-			*valuep = m->cpus[cpunr]->cd.ppc.hdec;
+			*valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_HDEC];
 		*match_register = 1;
 	} else if (strcasecmp(name, "ctr") == 0) {
 		if (writeflag)
-			m->cpus[cpunr]->cd.ppc.ctr = *valuep;
+			m->cpus[cpunr]->cd.ppc.spr[SPR_CTR] = *valuep;
 		else
-			*valuep = m->cpus[cpunr]->cd.ppc.ctr;
+			*valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_CTR];
 		*match_register = 1;
 	} else if (name[0] == 'r' && isdigit((int)name[1])) {
 		int nr = atoi(name + 1);
@@ -402,9 +577,9 @@
 		}
 	} else if (strcasecmp(name, "xer") == 0) {
 		if (writeflag)
-			m->cpus[cpunr]->cd.ppc.xer = *valuep;
+			m->cpus[cpunr]->cd.ppc.spr[SPR_XER] = *valuep;
 		else
-			*valuep = m->cpus[cpunr]->cd.ppc.xer;
+			*valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_XER];
 		*match_register = 1;
 	} else if (strcasecmp(name, "fpscr") == 0) {
 		if (writeflag)
@@ -426,38 +601,124 @@
 
 
 /*
- *  ppc_cpu_show_full_statistics():
+ *  ppc_cpu_tlbdump():
  *
- *  Show detailed statistics on opcode usage on each cpu.
+ *  Not currently used for PPC.
  */
-void ppc_cpu_show_full_statistics(struct machine *m)
+void ppc_cpu_tlbdump(struct machine *m, int x, int rawflag)
 {
-	fatal("ppc_cpu_show_full_statistics(): TODO\n");
+}
+
+
+static void add_response_word(struct cpu *cpu, char *r, uint64_t value,
+	size_t maxlen, int len)
+{
+	char *format = (len == 4)? "%08"PRIx64 : "%016"PRIx64;
+	if (len == 4)
+		value &= 0xffffffffULL;
+	if (cpu->byte_order == EMUL_LITTLE_ENDIAN) {
+		if (len == 4) {
+			value = ((value & 0xff) << 24) +
+				((value & 0xff00) << 8) +
+				((value & 0xff0000) >> 8) +
+				((value & 0xff000000) >> 24);
+		} else {
+			value = ((value & 0xff) << 56) +
+				((value & 0xff00) << 40) +
+				((value & 0xff0000) << 24) +
+				((value & 0xff000000ULL) << 8) +
+				((value & 0xff00000000ULL) >> 8) +
+				((value & 0xff0000000000ULL) >> 24) +
+				((value & 0xff000000000000ULL) >> 40) +
+				((value & 0xff00000000000000ULL) >> 56);
+		}
+	}
+	snprintf(r + strlen(r), maxlen - strlen(r), format, (uint64_t)value);
 }
 
 
 /*
- *  ppc_cpu_tlbdump():
- *
- *  Called from the debugger to dump the TLB in a readable format.
- *  x is the cpu number to dump, or -1 to dump all CPUs.
+ *  ppc_cpu_gdb_stub():
  *
- *  If rawflag is nonzero, then the TLB contents isn't formated nicely,
- *  just dumped.
+ *  Execute a "remote GDB" command. Returns a newly allocated response string
+ *  on success, NULL on failure.
  */
-void ppc_cpu_tlbdump(struct machine *m, int x, int rawflag)
+char *ppc_cpu_gdb_stub(struct cpu *cpu, char *cmd)
 {
-	fatal("ppc_cpu_tlbdump(): TODO\n");
+	if (strcmp(cmd, "g") == 0) {
+		int i;
+		char *r;
+		size_t wlen = cpu->is_32bit?
+		    sizeof(uint32_t) : sizeof(uint64_t);
+		size_t len = 1 + 76 * wlen;
+		r = malloc(len);
+		if (r == NULL) {
+			fprintf(stderr, "out of memory\n");
+			exit(1);
+		}
+		r[0] = '\0';
+		for (i=0; i<128; i++)
+			add_response_word(cpu, r, i, len, wlen);
+		return r;
+	}
+
+	if (cmd[0] == 'p') {
+		int regnr = strtol(cmd + 1, NULL, 16);
+		size_t wlen = cpu->is_32bit?
+		    sizeof(uint32_t) : sizeof(uint64_t);
+		size_t len = 2 * wlen + 1;
+		char *r = malloc(len);
+		r[0] = '\0';
+		if (regnr >= 0 && regnr <= 31) {
+			add_response_word(cpu, r,
+			    cpu->cd.ppc.gpr[regnr], len, wlen);
+		} else if (regnr == 0x40) {
+			add_response_word(cpu, r, cpu->pc, len, wlen);
+		} else if (regnr == 0x42) {
+			add_response_word(cpu, r, cpu->cd.ppc.cr, len, wlen);
+		} else if (regnr == 0x43) {
+			add_response_word(cpu, r, cpu->cd.ppc.spr[SPR_LR],
+			    len, wlen);
+		} else if (regnr == 0x44) {
+			add_response_word(cpu, r, cpu->cd.ppc.spr[SPR_CTR],
+			    len, wlen);
+		} else if (regnr == 0x45) {
+			add_response_word(cpu, r, cpu->cd.ppc.spr[SPR_XER],
+			    len, wlen);
+		} else {
+			/*  Unimplemented:  */
+			add_response_word(cpu, r, 0xcc000 + regnr, len, wlen);
+		}
+		return r;
+	}
+
+	fatal("ppc_cpu_gdb_stub(): TODO\n");
+	return NULL;
 }
 
 
 /*
  *  ppc_cpu_interrupt():
+ *
+ *  0..31 are used as BeBox interrupt numbers, 32..47 = ISA,
+ *  64 is used as a "re-assert" signal to cpu->machine->md_interrupt().
+ *
+ *  TODO: don't hardcode to BeBox!
  */
 int ppc_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr)
 {
-	fatal("ppc_cpu_interrupt(): TODO\n");
-	return 0;
+	/*  fatal("ppc_cpu_interrupt(): 0x%x\n", (int)irq_nr);  */
+	if (irq_nr <= 64) {
+		if (cpu->machine->md_interrupt != NULL)
+			cpu->machine->md_interrupt(
+			    cpu->machine, cpu, irq_nr, 1);
+		else
+			fatal("ppc_cpu_interrupt(): md_interrupt == NULL\n");
+	} else {
+		/*  Assert PPC IRQ:  */
+		cpu->cd.ppc.irq_asserted = 1;
+	}
+	return 1;
 }
 
 
@@ -466,8 +727,15 @@
  */
 int ppc_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr)
 {
-	/*  fatal("ppc_cpu_interrupt_ack(): TODO\n");  */
-	return 0;
+	if (irq_nr <= 64) {
+		if (cpu->machine->md_interrupt != NULL)
+			cpu->machine->md_interrupt(cpu->machine,
+			    cpu, irq_nr, 0);
+	} else {
+		/*  De-assert PPC IRQ:  */
+		cpu->cd.ppc.irq_asserted = 0;
+	}
+	return 1;
 }
 
 
@@ -484,7 +752,7 @@
  *  cpu->pc for relative addresses.
  */
 int ppc_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr,
-	int running, uint64_t dumpaddr, int bintrans)
+	int running, uint64_t dumpaddr)
 {
 	int hi6, xo, lev, rt, rs, ra, rb, imm, sh, me, rc, l_bit, oe_bit;
 	int spr, aa_bit, lk_bit, bf, bh, bi, bo, mb, nb, bt, ba, bb, fpreg;
@@ -523,6 +791,10 @@
 	hi6 = iword >> 26;
 
 	switch (hi6) {
+	case 0x4:
+		debug("ALTIVEC TODO");
+		/*  vxor etc  */
+		break;
 	case PPC_HI6_MULLI:
 	case PPC_HI6_SUBFIC:
 		rt = (iword >> 21) & 31;
@@ -715,22 +987,27 @@
 			debug("unimplemented hi6_19, xo = 0x%x", xo);
 		}
 		break;
+	case PPC_HI6_RLWNM:
 	case PPC_HI6_RLWIMI:
 	case PPC_HI6_RLWINM:
 		rs = (iword >> 21) & 31;
 		ra = (iword >> 16) & 31;
-		sh = (iword >> 11) & 31;
+		sh = (iword >> 11) & 31;	/*  actually rb for rlwnm  */
 		mb = (iword >> 6) & 31;
 		me = (iword >> 1) & 31;
 		rc = iword & 1;
 		switch (hi6) {
+		case PPC_HI6_RLWNM:
+			mnem = power? "rlnm" : "rlwnm"; break;
 		case PPC_HI6_RLWIMI:
 			mnem = power? "rlimi" : "rlwimi"; break;
 		case PPC_HI6_RLWINM:
 			mnem = power? "rlinm" : "rlwinm"; break;
 		}
-		debug("%s%s\tr%i,r%i,%i,%i,%i",
-		    mnem, rc?".":"", ra, rs, sh, mb, me);
+		debug("%s%s\tr%i,r%i,%s%i,%i,%i",
+		    mnem, rc?".":"", ra, rs,
+		    hi6 == PPC_HI6_RLWNM? "r" : "",
+		    sh, mb, me);
 		break;
 	case PPC_HI6_ORI:
 	case PPC_HI6_ORIS:
@@ -769,14 +1046,22 @@
 	case PPC_HI6_30:
 		xo = (iword >> 2) & 7;
 		switch (xo) {
+		case PPC_30_RLDICL:
 		case PPC_30_RLDICR:
+		case PPC_30_RLDIMI:	/*  mb, not me  */
+			mnem = NULL;
+			switch (xo) {
+			case PPC_30_RLDICL: mnem = "rldicl"; break;
+			case PPC_30_RLDICR: mnem = "rldicr"; break;
+			case PPC_30_RLDIMI: mnem = "rldimi"; break;
+			}
 			rs = (iword >> 21) & 31;
 			ra = (iword >> 16) & 31;
 			sh = ((iword >> 11) & 31) | ((iword & 2) << 4);
 			me = ((iword >> 6) & 31) | (iword & 0x20);
 			rc = iword & 1;
-			debug("rldicr%s\tr%i,r%i,%i,%i",
-			    rc?".":"", ra, rs, sh, me);
+			debug("%s%s\tr%i,r%i,%i,%i",
+			    mnem, rc?".":"", ra, rs, sh, me);
 			break;
 		default:
 			debug("unimplemented hi6_30, xo = 0x%x", xo);
@@ -836,10 +1121,16 @@
 		case PPC_31_LDARX:
 		case PPC_31_LBZX:
 		case PPC_31_LBZUX:
+		case PPC_31_LHAX:
+		case PPC_31_LHAUX:
 		case PPC_31_LHZX:
 		case PPC_31_LHZUX:
 		case PPC_31_LWZX:
 		case PPC_31_LWZUX:
+		case PPC_31_LHBRX:
+		case PPC_31_LWBRX:
+		case PPC_31_LFDX:
+		case PPC_31_LFSX:
 		case PPC_31_STWCX_DOT:
 		case PPC_31_STDCX_DOT:
 		case PPC_31_STBX:
@@ -850,8 +1141,12 @@
 		case PPC_31_STWUX:
 		case PPC_31_STDX:
 		case PPC_31_STDUX:
+		case PPC_31_STHBRX:
+		case PPC_31_STWBRX:
+		case PPC_31_STFDX:
+		case PPC_31_STFSX:
 			/*  rs for stores, rt for loads, actually  */
-			load = 0; wlen = 0;
+			load = 0; wlen = 0; fpreg = 0;
 			rs = (iword >> 21) & 31;
 			ra = (iword >> 16) & 31;
 			rb = (iword >> 11) & 31;
@@ -860,6 +1155,8 @@
 			case PPC_31_LDARX: wlen=8;load=1; mnem = "ldarx"; break;
 			case PPC_31_LBZX:  wlen=1;load=1; mnem = "lbzx"; break;
 			case PPC_31_LBZUX: wlen=1;load=1; mnem = "lbzux"; break;
+			case PPC_31_LHAX:  wlen=2;load=1; mnem = "lhax"; break;
+			case PPC_31_LHAUX: wlen=2;load=1; mnem = "lhaux"; break;
 			case PPC_31_LHZX:  wlen=2;load=1; mnem = "lhzx"; break;
 			case PPC_31_LHZUX: wlen=2;load=1; mnem = "lhzux"; break;
 			case PPC_31_LWZX:  wlen = 4; load = 1;
@@ -868,6 +1165,10 @@
 			case PPC_31_LWZUX: wlen = 4; load = 1;
 				mnem = power? "lux":"lwzux";
 				break;
+			case PPC_31_LFDX: fpreg = 1; wlen = 8; load = 1;
+				mnem = "lfdx"; break;
+			case PPC_31_LFSX: fpreg = 1; wlen = 4; load = 1;
+				mnem = "lfsx"; break;
 			case PPC_31_STWCX_DOT: wlen=4; mnem = "stwcx."; break;
 			case PPC_31_STDCX_DOT: wlen=8; mnem = "stdcx."; break;
 			case PPC_31_STBX:  wlen=1; mnem = "stbx"; break;
@@ -882,19 +1183,32 @@
 				break;
 			case PPC_31_STDX:  wlen = 8; mnem = "stdx"; break;
 			case PPC_31_STDUX: wlen = 8; mnem = "stdux"; break;
+			case PPC_31_LHBRX:  wlen = 2; mnem = "lhbrx"; break;
+			case PPC_31_LWBRX:  wlen = 4; mnem = power?
+					    "lbrx" : "lwbrx"; break;
+			case PPC_31_STHBRX: wlen = 2; mnem = "sthbrx"; break;
+			case PPC_31_STWBRX: wlen = 4; mnem = power?
+					    "stbrx" : "stwbrx"; break;
+			case PPC_31_STFDX: fpreg = 1; wlen = 8;
+				mnem = "stfdx"; break;
+			case PPC_31_STFSX: fpreg = 1; wlen = 4;
+				mnem = "stfsx"; break;
 			}
-			debug("%s\tr%i,r%i,r%i", mnem, rs, ra, rb);
+			debug("%s\t%s%i,r%i,r%i", mnem,
+			    fpreg? "f" : "r", rs, ra, rb);
 			if (!running)
 				break;
 			addr = (ra==0? 0 : cpu->cd.ppc.gpr[ra]) +
 			    cpu->cd.ppc.gpr[rb];
+			if (cpu->cd.ppc.bits == 32)
+				addr &= 0xffffffff;
 			symbol = get_symbol_name(&cpu->machine->symbol_context,
 			    addr, &offset);
 			if (symbol != NULL)
 				debug(" \t<%s", symbol);
 			else
 				debug(" \t<0x%llx", (long long)addr);
-			if (wlen > 0) {
+			if (wlen > 0 && !fpreg /* && !reverse */) {
 				/*  TODO  */
 			}
 			debug(">");
@@ -911,6 +1225,17 @@
 			}
 			debug("%s%s\tr%i,r%i", mnem, rc? "." : "", rt, ra);
 			break;
+		case PPC_31_WRTEEI:
+			debug("wrteei\t%i", iword & 0x8000? 1 : 0);
+			break;
+		case PPC_31_MTMSRD:
+			/*  TODO: Just a guess based on MTMSR  */
+			rs = (iword >> 21) & 31;
+			l_bit = (iword >> 16) & 1;
+			debug("mtmsrd\tr%i", rs);
+			if (l_bit)
+				debug(",%i", l_bit);
+			break;
 		case PPC_31_ADDZE:
 		case PPC_31_ADDZEO:
 			rt = (iword >> 21) & 31;
@@ -928,10 +1253,15 @@
 			debug("%s%s\tr%i,r%i", mnem, rc? "." : "", rt, ra);
 			break;
 		case PPC_31_MTSR:
-			/*  Move to segment register  */
+		case PPC_31_MFSR:
+			/*  Move to/from segment register  */
 			rt = (iword >> 21) & 31;
 			ra = (iword >> 16) & 15;	/*  actually: sr  */
-			debug("mtsr\t%i,r%i", ra, rt);
+			switch (xo) {
+			case PPC_31_MTSR:  mnem = "mtsr"; break;
+			case PPC_31_MFSR:  mnem = "mfsr"; break;
+			}
+			debug("%s\tr%i,%i", mnem, rt, ra);
 			break;
 		case PPC_31_MTSRIN:
 		case PPC_31_MFSRIN:
@@ -962,6 +1292,8 @@
 		case PPC_31_SUBFCO:
 		case PPC_31_SUBFE:
 		case PPC_31_SUBFEO:
+		case PPC_31_SUBFME:
+		case PPC_31_SUBFMEO:
 		case PPC_31_SUBFZE:
 		case PPC_31_SUBFZEO:
 			rt = (iword >> 21) & 31;
@@ -1007,17 +1339,17 @@
 			case PPC_31_SUBF:   mnem = "subf"; break;
 			case PPC_31_SUBFO:  mnem = "subfo"; break;
 			case PPC_31_SUBFC:
-				mnem = power? "sf" : "subfc";
-				break;
+				mnem = power? "sf" : "subfc"; break;
 			case PPC_31_SUBFCO:
-				mnem = power? "sfo" : "subfco";
-				break;
+				mnem = power? "sfo" : "subfco"; break;
 			case PPC_31_SUBFE:
-				mnem = power? "sfe" : "subfe";
-				break;
+				mnem = power? "sfe" : "subfe"; break;
 			case PPC_31_SUBFEO:
-				mnem = power? "sfeo" : "subfeo";
-				break;
+				mnem = power? "sfeo" : "subfeo"; break;
+			case PPC_31_SUBFME:
+				mnem = power? "sfme" : "subfme"; break;
+			case PPC_31_SUBFMEO:
+				mnem = power? "sfmeo" : "subfmeo"; break;
 			case PPC_31_SUBFZE:
 				mnem = power? "sfze" : "subfze";
 				no_rb = 1;
@@ -1035,22 +1367,35 @@
 			rt = (iword >> 21) & 31;
 			spr = ((iword >> 6) & 0x3e0) + ((iword >> 16) & 31);
 			switch (spr) {
+			/*  Some very common ones:  */
 			case 8:	   debug("mflr\tr%i", rt); break;
 			case 9:	   debug("mfctr\tr%i", rt); break;
-			case 26:   debug("mfsrr0\tr%i", rt); break;
-			case 27:   debug("mfsrr1\tr%i", rt); break;
-			case 272:  debug("mfsprg\t0,r%i", rt); break;
-			case 273:  debug("mfsprg\t1,r%i", rt); break;
-			case 274:  debug("mfsprg\t2,r%i", rt); break;
-			case 275:  debug("mfsprg\t3,r%i", rt); break;
-			case 287:  debug("mfpvr\tr%i", rt); break;
-			/*  TODO: 1008 = hid0?  */
-			case 1008: debug("mfdbsr\tr%i", rt); break;
-			case 1009: debug("mfhid1\tr%i", rt); break;
-			case 1017: debug("mfl2cr\tr%i", rt); break;
-			case 1018: debug("mfl3cr\tr%i", rt); break;
 			default:debug("mfspr\tr%i,spr%i", rt, spr);
 			}
+			if (spr == 8 || spr == 9)
+				debug("\t");
+			debug("\t<%s%s", running? "read from " : "",
+			    ppc_spr_names[spr]==NULL? "?" : ppc_spr_names[spr]);
+			if (running) {
+				if (cpu->cd.ppc.bits == 32)
+					debug(": 0x%x", (int)
+					    cpu->cd.ppc.spr[spr]);
+				else
+					debug(": 0x%llx", (long long)
+					    cpu->cd.ppc.spr[spr]);
+			}
+			debug(">");
+			break;
+		case PPC_31_TLBIA:
+			debug("tlbia");
+			break;
+		case PPC_31_SLBIA:
+			debug("slbia");
+			break;
+		case PPC_31_TLBLD:
+		case PPC_31_TLBLI:
+			rb = (iword >> 11) & 31;
+			debug("tlbl%s\tr%i", xo == PPC_31_TLBLD? "d" : "i", rb);
 			break;
 		case PPC_31_TLBIE:
 			/*  TODO: what is ra? The IBM online docs didn't say  */
@@ -1061,6 +1406,12 @@
 			else
 				debug("tlbie\tr%i", rb);
 			break;
+		case PPC_31_TLBSX_DOT:
+			rs = (iword >> 21) & 31;
+			ra = (iword >> 16) & 31;
+			rb = (iword >> 11) & 31;
+			debug("tlbsx.\tr%i,r%i,r%i", rs, ra, rb);
+			break;
 		case PPC_31_TLBSYNC:
 			debug("tlbsync");
 			break;
@@ -1105,11 +1456,13 @@
 			debug("%s\tr%i,r%i", mnem, ra, rb);
 			break;
 		case PPC_31_SLW:
+		case PPC_31_SLD:
 		case PPC_31_SRAW:
 		case PPC_31_SRW:
 		case PPC_31_AND:
 		case PPC_31_ANDC:
 		case PPC_31_NOR:
+		case PPC_31_EQV:
 		case PPC_31_OR:
 		case PPC_31_ORC:
 		case PPC_31_XOR:
@@ -1124,6 +1477,7 @@
 				switch (xo) {
 				case PPC_31_SLW:  mnem =
 					power? "sl" : "slw"; break;
+				case PPC_31_SLD:  mnem = "sld"; break;
 				case PPC_31_SRAW:  mnem =
 					power? "sra" : "sraw"; break;
 				case PPC_31_SRW:  mnem =
@@ -1132,6 +1486,7 @@
 				case PPC_31_NAND: mnem = "nand"; break;
 				case PPC_31_ANDC: mnem = "andc"; break;
 				case PPC_31_NOR:  mnem = "nor"; break;
+				case PPC_31_EQV:  mnem = "eqv"; break;
 				case PPC_31_OR:   mnem = "or"; break;
 				case PPC_31_ORC:  mnem = "orc"; break;
 				case PPC_31_XOR:  mnem = "xor"; break;
@@ -1172,33 +1527,24 @@
 			rs = (iword >> 21) & 31;
 			spr = ((iword >> 6) & 0x3e0) + ((iword >> 16) & 31);
 			switch (spr) {
+			/*  Some very common ones:  */
 			case 8:	   debug("mtlr\tr%i", rs); break;
 			case 9:	   debug("mtctr\tr%i", rs); break;
-			case 26:   debug("mtsrr0\tr%i", rs); break;
-			case 27:   debug("mtsrr1\tr%i", rs); break;
-			case 272:  debug("mtsprg\t0,r%i", rs); break;
-			case 273:  debug("mtsprg\t1,r%i", rs); break;
-			case 274:  debug("mtsprg\t2,r%i", rs); break;
-			case 275:  debug("mtsprg\t3,r%i", rs); break;
-			case 528:  debug("mtibatu\t0,r%i", rs); break;
-			case 529:  debug("mtibatl\t0,r%i", rs); break;
-			case 530:  debug("mtibatu\t1,r%i", rs); break;
-			case 531:  debug("mtibatl\t1,r%i", rs); break;
-			case 532:  debug("mtibatu\t2,r%i", rs); break;
-			case 533:  debug("mtibatl\t2,r%i", rs); break;
-			case 534:  debug("mtibatu\t3,r%i", rs); break;
-			case 535:  debug("mtibatl\t3,r%i", rs); break;
-			case 536:  debug("mtdbatu\t0,r%i", rs); break;
-			case 537:  debug("mtdbatl\t0,r%i", rs); break;
-			case 538:  debug("mtdbatu\t1,r%i", rs); break;
-			case 539:  debug("mtdbatl\t1,r%i", rs); break;
-			case 540:  debug("mtdbatu\t2,r%i", rs); break;
-			case 541:  debug("mtdbatl\t2,r%i", rs); break;
-			case 542:  debug("mtdbatu\t3,r%i", rs); break;
-			case 543:  debug("mtdbatl\t3,r%i", rs); break;
-			case 1008: debug("mtdbsr\tr%i", rs); break;
 			default:debug("mtspr\tspr%i,r%i", spr, rs);
 			}
+			if (spr == 8 || spr == 9)
+				debug("\t");
+			debug("\t<%s%s", running? "write to " : "",
+			    ppc_spr_names[spr]==NULL? "?" : ppc_spr_names[spr]);
+			if (running) {
+				if (cpu->cd.ppc.bits == 32)
+					debug(": 0x%x", (int)
+					    cpu->cd.ppc.gpr[rs]);
+				else
+					debug(": 0x%llx", (long long)
+					    cpu->cd.ppc.gpr[rs]);
+			}
+			debug(">");
 			break;
 		case PPC_31_SYNC:
 			debug("%s", power? "dcs" : "sync");
@@ -1216,23 +1562,6 @@
 			}
 			debug("%s\tr%i,r%i,%i", mnem, rs, ra, nb);
 			break;
-		case PPC_31_LHBRX:
-		case PPC_31_LWBRX:
-		case PPC_31_STHBRX:
-		case PPC_31_STWBRX:
-			rt = (iword >> 21) & 31;	/*  stores use rs  */
-			ra = (iword >> 16) & 31;
-			rb = (iword >> 11) & 31;
-			switch (xo) {
-			case PPC_31_LHBRX:  mnem = "lhbrx"; break;
-			case PPC_31_LWBRX:  mnem = power?
-					    "lbrx" : "lwbrx"; break;
-			case PPC_31_STHBRX: mnem = "sthbrx"; break;
-			case PPC_31_STWBRX: mnem = power?
-					    "stbrx" : "stwbrx"; break;
-			}
-			debug("%s\tr%i,r%i,r%i", mnem, rt, ra, rb);
-			break;
 		case PPC_31_SRAWI:
 			rs = (iword >> 21) & 31;
 			ra = (iword >> 16) & 31;
@@ -1242,6 +1571,9 @@
 			debug("%s%s\tr%i,r%i,%i", mnem,
 			    rc? "." : "", ra, rs, sh);
 			break;
+		case PPC_31_DSSALL:
+			debug("dssall");
+			break;
 		case PPC_31_EIEIO:
 			debug("%s", power? "eieio?" : "eieio");
 			break;
@@ -1264,10 +1596,28 @@
 			}
 			debug("%s%s\tr%i,r%i", mnem, rc? "." : "", ra, rs);
 			break;
+		case PPC_31_LVX:
+		case PPC_31_LVXL:
+		case PPC_31_STVX:
+		case PPC_31_STVXL:
+			rs = (iword >> 21) & 31;	/*  vs for stores,  */
+			ra = (iword >> 16) & 31;	/*  rs=vl for loads  */
+			rb = (iword >> 11) & 31;
+			rc = iword & 1;
+			switch (xo) {
+			case PPC_31_LVX:   mnem = "lvx";  break;
+			case PPC_31_LVXL:  mnem = "lvxl"; break;
+			case PPC_31_STVX:  mnem = "stvx";  break;
+			case PPC_31_STVXL: mnem = "stvxl"; break;
+			}
+			debug("%s%s\tv%i,r%i,r%i", mnem, rc? "." : "",
+			    rs, ra, rb);
+			break;
 		default:
 			debug("unimplemented hi6_31, xo = 0x%x", xo);
 		}
 		break;
+	case PPC_HI6_LD:
 	case PPC_HI6_LWZ:
 	case PPC_HI6_LWZU:
 	case PPC_HI6_LHZ:
@@ -1276,7 +1626,10 @@
 	case PPC_HI6_LHAU:
 	case PPC_HI6_LBZ:
 	case PPC_HI6_LBZU:
+	case PPC_HI6_LFD:
+	case PPC_HI6_LFS:
 	case PPC_HI6_LMW:
+	case PPC_HI6_STD:
 	case PPC_HI6_STW:
 	case PPC_HI6_STWU:
 	case PPC_HI6_STH:
@@ -1284,8 +1637,8 @@
 	case PPC_HI6_STB:
 	case PPC_HI6_STBU:
 	case PPC_HI6_STMW:
-	case PPC_HI6_LFD:
 	case PPC_HI6_STFD:
+	case PPC_HI6_STFS:
 		/*  NOTE: Loads use rt, not rs, but are otherwise similar
 		    to stores  */
 		load = 0; wlen = 0;
@@ -1294,6 +1647,7 @@
 		imm = (int16_t)(iword & 0xffff);
 		fpreg = 0;
 		switch (hi6) {
+		case PPC_HI6_LD:  load=1; wlen = 8; mnem = "ld"; break;
 		case PPC_HI6_LWZ:  load=1; wlen = 4;
 			mnem = power? "l" : "lwz"; break;
 		case PPC_HI6_LWZU: load=1; wlen = 4;
@@ -1310,6 +1664,9 @@
 			mnem = "lbz"; break;
 		case PPC_HI6_LBZU: load=1; wlen = 1;
 			mnem = "lbzu"; break;
+		case PPC_HI6_LFD:  load=1; fpreg=1; wlen=8; mnem = "lfd"; break;
+		case PPC_HI6_LFS:  load=1; fpreg=1; wlen=4; mnem = "lfs"; break;
+		case PPC_HI6_STD:  wlen=8; mnem = "std"; break;
 		case PPC_HI6_STW:  wlen=4; mnem = power? "st" : "stw"; break;
 		case PPC_HI6_STWU: wlen=4; mnem = power? "stu" : "stwu"; break;
 		case PPC_HI6_STH:  wlen=2; mnem = "sth"; break;
@@ -1318,8 +1675,8 @@
 		case PPC_HI6_STBU: wlen=1; mnem = "stbu"; break;
 		case PPC_HI6_LMW:  load=1; mnem = power? "lm" : "lmw"; break;
 		case PPC_HI6_STMW: mnem = power? "stm" : "stmw"; break;
-		case PPC_HI6_LFD:  load=1; fpreg = 1; mnem = "lfd"; break;
-		case PPC_HI6_STFD: fpreg = 1; mnem = "stfd"; break;
+		case PPC_HI6_STFD: fpreg=1; wlen=8; mnem = "stfd"; break;
+		case PPC_HI6_STFS: fpreg=1; wlen=4; mnem = "stfs"; break;
 		}
 		debug("%s\t", mnem);
 		if (fpreg)
@@ -1330,6 +1687,8 @@
 		if (!running)
 			break;
 		addr = (ra==0? 0 : cpu->cd.ppc.gpr[ra]) + imm;
+		if (cpu->cd.ppc.bits == 32)
+			addr &= 0xffffffff;
 		symbol = get_symbol_name(&cpu->machine->symbol_context,
 		    addr, &offset);
 		if (symbol != NULL)
@@ -1374,7 +1733,7 @@
 			int i;
 			for (i=0; i<wlen; i++)
 				tdata |= (cpu->cd.ppc.gpr[rs] &
-				    ((uint64_t)0xff << i));
+				    ((uint64_t)0xff << (i*8)));
 			debug(": ");
 			if (wlen >= 4) {
 				symbol = get_symbol_name(&cpu->machine->
@@ -1382,8 +1741,7 @@
 				if (symbol != NULL)
 					debug("%s", symbol);
 				else
-					debug("0x%llx",
-					    (long long)tdata);
+					debug("0x%llx", (long long)tdata);
 			} else {
 				if (tdata > -256 && tdata < 256)
 					debug("%i", (int)tdata);
@@ -1393,22 +1751,131 @@
 		}
 		debug(">");
 		break;
+	case PPC_HI6_59:
+		xo = (iword >> 1) & 1023;
+		/*  NOTE: Some floating point instructions only use the
+		    lowest 5 bits of xo, some use all 10 bits!  */
+		switch (xo & 31) {
+		case PPC_59_FDIVS:
+		case PPC_59_FSUBS:
+		case PPC_59_FADDS:
+		case PPC_59_FMULS:
+		case PPC_59_FMADDS:
+			rt = (iword >> 21) & 31;
+			ra = (iword >> 16) & 31;
+			rb = (iword >> 11) & 31;
+			rs = (iword >>  6) & 31;	/*  actually frc  */
+			rc = iword & 1;
+			switch (xo & 31) {
+			case PPC_59_FDIVS:	mnem = "fdivs"; break;
+			case PPC_59_FSUBS:	mnem = "fsubs"; break;
+			case PPC_59_FADDS:	mnem = "fadds"; break;
+			case PPC_59_FMULS:	mnem = "fmuls"; break;
+			case PPC_59_FMADDS:	mnem = "fmadds"; break;
+			}
+			debug("%s%s\t", mnem, rc? "." : "");
+			switch (xo & 31) {
+			case PPC_59_FMULS:
+				debug("f%i,f%i,f%i", rt, ra, rs);
+				break;
+			case PPC_59_FMADDS:
+				debug("f%i,f%i,f%i,f%i", rt, ra, rs, rb);
+				break;
+			default:debug("f%i,f%i,f%i", rt, ra, rb);
+			}
+			break;
+		default:/*  TODO: similar to hi6_63  */
+			debug("unimplemented hi6_59, xo = 0x%x", xo);
+		}
+		break;
 	case PPC_HI6_63:
 		xo = (iword >> 1) & 1023;
-		switch (xo) {
-		case PPC_63_FMR:
+		/*  NOTE: Some floating point instructions only use the
+		    lowest 5 bits of xo, some use all 10 bits!  */
+		switch (xo & 31) {
+		case PPC_63_FDIV:
+		case PPC_63_FSUB:
+		case PPC_63_FADD:
+		case PPC_63_FMUL:
+		case PPC_63_FMSUB:
+		case PPC_63_FMADD:
 			rt = (iword >> 21) & 31;
 			ra = (iword >> 16) & 31;
 			rb = (iword >> 11) & 31;
+			rs = (iword >>  6) & 31;	/*  actually frc  */
+			rc = iword & 1;
+			switch (xo & 31) {
+			case PPC_63_FDIV:
+				mnem = power? "fd" : "fdiv"; break;
+			case PPC_63_FSUB:
+				mnem = power? "fs" : "fsub"; break;
+			case PPC_63_FADD:
+				mnem = power? "fa" : "fadd"; break;
+			case PPC_63_FMUL:
+				mnem = power? "fm" : "fmul"; break;
+			case PPC_63_FMSUB:
+				mnem = power? "fms" : "fmsub"; break;
+			case PPC_63_FMADD:
+				mnem = power? "fma" : "fmadd"; break;
+			}
+			debug("%s%s\t", mnem, rc? "." : "");
+			switch (xo & 31) {
+			case PPC_63_FMUL:
+				debug("f%i,f%i,f%i", rt, ra, rs);
+				break;
+			case PPC_63_FMADD:
+				debug("f%i,f%i,f%i,f%i", rt, ra, rs, rb);
+				break;
+			default:debug("f%i,f%i,f%i", rt, ra, rb);
+			}
+			break;
+		default:rt = (iword >> 21) & 31;
+			ra = (iword >> 16) & 31;
+			rb = (iword >> 11) & 31;
 			rc = iword & 1;
 			switch (xo) {
+			case PPC_63_FCMPU:
+			case PPC_63_FRSP:
+			case PPC_63_FCTIWZ:
+			case PPC_63_FNEG:
 			case PPC_63_FMR:
-				debug("fmr%s\tf%i,f%i", rc? "." : "", rt, rb);
+			case PPC_63_FNABS:
+			case PPC_63_FABS:
+				switch (xo) {
+				case PPC_63_FCMPU:	mnem = "fcmpu"; break;
+				case PPC_63_FCTIWZ:
+					mnem = power? "fcirz" : "fctiwz"; break;
+				case PPC_63_FRSP:	mnem = "frsp"; break;
+				case PPC_63_FNEG:	mnem = "fneg"; break;
+				case PPC_63_FMR:	mnem = "fmr"; break;
+				case PPC_63_FNABS:	mnem = "fnabs"; break;
+				case PPC_63_FABS:	mnem = "fabs"; break;
+				}
+				debug("%s%s\t", mnem, rc? "." : "");
+				switch (xo) {
+				case PPC_63_FCMPU:
+					debug("%i,f%i,f%i", rt >> 2, ra, rb);
+					break;
+				case PPC_63_FCTIWZ:
+				case PPC_63_FRSP:
+				case PPC_63_FNEG:
+				case PPC_63_FMR:
+				case PPC_63_FNABS:
+				case PPC_63_FABS:
+					debug("f%i,f%i", rt, rb);
+					break;
+				default:debug("f%i,f%i,f%i", rt, ra, rb);
+				}
+				break;
+			case PPC_63_MFFS:
+				debug("mffs%s\tf%i", rc?".":"", rt);
 				break;
+			case PPC_63_MTFSF:
+				ra = (iword >> 17) & 255;	/*  flm  */
+				debug("mtfsf%s\t0x%02x,f%i", rc?".":"", ra, rb);
+				break;
+			default:debug("unimplemented hi6_63, xo = 0x%x", xo);
 			}
-			break;
-		default:
-			debug("unimplemented hi6_31, xo = 0x%x", xo);
 		}
 		break;
 	default:
@@ -1422,6 +1889,64 @@
 
 
 /*
+ *  debug_spr_usage():
+ *
+ *  Helper function. To speed up overall development speed of the emulator,
+ *  all SPR accesses are allowed. This function causes unknown/unimplemented
+ *  SPRs to give a warning.
+ */
+static void debug_spr_usage(uint64_t pc, int spr)
+{
+	static uint32_t spr_used[1024 / sizeof(uint32_t)];
+	static int initialized = 0;
+
+	if (!initialized) {
+		memset(spr_used, 0, sizeof(spr_used));
+		initialized = 1;
+	}
+
+	spr &= 1023;
+	if (spr_used[spr >> 2] & (1 << (spr & 3)))
+		return;
+
+	switch (spr) {
+	/*  Known/implemented SPRs:  */
+	case SPR_XER:
+	case SPR_LR:
+	case SPR_CTR:
+	case SPR_DSISR:
+	case SPR_DAR:
+	case SPR_DEC:
+	case SPR_SDR1:
+	case SPR_SRR0:
+	case SPR_SRR1:
+	case SPR_SPRG0:
+	case SPR_SPRG1:
+	case SPR_SPRG2:
+	case SPR_SPRG3:
+	case SPR_PVR:
+	case SPR_DMISS:
+	case SPR_DCMP:
+	case SPR_HASH1:
+	case SPR_HASH2:
+	case SPR_IMISS:
+	case SPR_ICMP:
+	case SPR_DBSR:
+	case SPR_PIR:
+		break;
+	default:if (spr >= SPR_IBAT0U && spr <= SPR_DBAT3L) {
+			break;
+		} else
+			fatal("[ using UNIMPLEMENTED spr %i (%s), pc = "
+			    "0x%llx ]\n", spr, ppc_spr_names[spr] == NULL?
+			    "UNKNOWN" : ppc_spr_names[spr], (long long)pc);
+	}
+
+	spr_used[spr >> 2] |= (1 << (spr & 3));
+}
+
+
+/*
  *  update_cr0():
  *
  *  Sets the top 4 bits of the CR register.
@@ -1447,7 +1972,7 @@
 	}
 
 	/*  SO bit, copied from XER:  */
-	c |= ((cpu->cd.ppc.xer >> 31) & 1);
+	c |= ((cpu->cd.ppc.spr[SPR_XER] >> 31) & 1);
 
 	cpu->cd.ppc.cr &= ~((uint32_t)0xf << 28);
 	cpu->cd.ppc.cr |= ((uint32_t)c << 28);
@@ -1459,3 +1984,4 @@
 
 #include "tmp_ppc_tail.c"
 
+