--- trunk/src/cpus/cpu_ppc.c 2007/10/08 16:19:23 20 +++ trunk/src/cpus/cpu_ppc.c 2007/10/08 16:22:56 44 @@ -1,5 +1,5 @@ /* - * Copyright (C) 2005 Anders Gavare. All rights reserved. + * Copyright (C) 2005-2007 Anders Gavare. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -25,7 +25,7 @@ * SUCH DAMAGE. * * - * $Id: cpu_ppc.c,v 1.35 2005/11/24 01:15:06 debug Exp $ + * $Id: cpu_ppc.c,v 1.72 2007/06/28 13:36:46 debug Exp $ * * PowerPC/POWER CPU emulation. */ @@ -37,15 +37,20 @@ #include "cpu.h" #include "devices.h" +#include "interrupt.h" #include "machine.h" #include "memory.h" #include "misc.h" +#include "of.h" #include "opcodes_ppc.h" #include "ppc_bat.h" #include "ppc_pte.h" #include "ppc_spr.h" #include "ppc_spr_strings.h" +#include "settings.h" #include "symbol.h" +#include "useremul.h" + #define DYNTRANS_DUALMODE_32 #include "tmp_ppc_head.c" @@ -54,6 +59,9 @@ void ppc_pc_to_pointers(struct cpu *); void ppc32_pc_to_pointers(struct cpu *); +void ppc_irq_interrupt_assert(struct interrupt *interrupt); +void ppc_irq_interrupt_deassert(struct interrupt *interrupt); + /* * ppc_cpu_new(): @@ -85,24 +93,44 @@ cpu->memory_rw = ppc_memory_rw; - cpu->cd.ppc.cpu_type = cpu_type_defs[found]; - cpu->name = cpu->cd.ppc.cpu_type.name; - cpu->byte_order = EMUL_BIG_ENDIAN; - cpu->cd.ppc.mode = MODE_PPC; /* TODO */ + cpu->cd.ppc.cpu_type = cpu_type_defs[found]; + cpu->name = cpu->cd.ppc.cpu_type.name; + cpu->byte_order = EMUL_BIG_ENDIAN; + cpu->cd.ppc.mode = MODE_PPC; /* TODO */ /* Current operating mode: */ cpu->cd.ppc.bits = cpu->cd.ppc.cpu_type.bits; cpu->cd.ppc.spr[SPR_PVR] = cpu->cd.ppc.cpu_type.pvr; + /* cpu->cd.ppc.msr = PPC_MSR_IR | PPC_MSR_DR | + PPC_MSR_SF | PPC_MSR_FP; */ + + cpu->cd.ppc.spr[SPR_IBAT0U] = 0x00001ffc | BAT_Vs; + cpu->cd.ppc.spr[SPR_IBAT0L] = 0x00000000 | BAT_PP_RW; + cpu->cd.ppc.spr[SPR_IBAT1U] = 0xc0001ffc | BAT_Vs; + cpu->cd.ppc.spr[SPR_IBAT1L] = 0x00000000 | BAT_PP_RW; + cpu->cd.ppc.spr[SPR_IBAT3U] = 0xf0001ffc | BAT_Vs; + cpu->cd.ppc.spr[SPR_IBAT3L] = 0xf0000000 | BAT_PP_RW; + cpu->cd.ppc.spr[SPR_DBAT0U] = 0x00001ffc | BAT_Vs; + cpu->cd.ppc.spr[SPR_DBAT0L] = 0x00000000 | BAT_PP_RW; + cpu->cd.ppc.spr[SPR_DBAT1U] = 0xc0001ffc | BAT_Vs; + cpu->cd.ppc.spr[SPR_DBAT1L] = 0x00000000 | BAT_PP_RW; + cpu->cd.ppc.spr[SPR_DBAT2U] = 0xe0001ffc | BAT_Vs; + cpu->cd.ppc.spr[SPR_DBAT2L] = 0xe0000000 | BAT_PP_RW; + cpu->cd.ppc.spr[SPR_DBAT3U] = 0xf0001ffc | BAT_Vs; + cpu->cd.ppc.spr[SPR_DBAT3L] = 0xf0000000 | BAT_PP_RW; + cpu->is_32bit = (cpu->cd.ppc.bits == 32)? 1 : 0; if (cpu->is_32bit) { + cpu->run_instr = ppc32_run_instr; cpu->update_translation_table = ppc32_update_translation_table; cpu->invalidate_translation_caches = ppc32_invalidate_translation_caches; cpu->invalidate_code_translation = ppc32_invalidate_code_translation; } else { + cpu->run_instr = ppc_run_instr; cpu->update_translation_table = ppc_update_translation_table; cpu->invalidate_translation_caches = ppc_invalidate_translation_caches; @@ -110,7 +138,7 @@ ppc_invalidate_code_translation; } - cpu->translate_address = ppc_translate_address; + cpu->translate_v2p = ppc_translate_v2p; /* Only show name and caches etc for CPU nr 0 (in SMP machines): */ if (cpu_id == 0) { @@ -147,6 +175,66 @@ if (cpu->machine->prom_emulation) cpu->cd.ppc.of_emul_addr = 0xfff00000; + /* Add all register names to the settings: */ + CPU_SETTINGS_ADD_REGISTER64("pc", cpu->pc); + CPU_SETTINGS_ADD_REGISTER64("msr", cpu->cd.ppc.msr); + CPU_SETTINGS_ADD_REGISTER64("ctr", cpu->cd.ppc.spr[SPR_CTR]); + CPU_SETTINGS_ADD_REGISTER64("xer", cpu->cd.ppc.spr[SPR_XER]); + CPU_SETTINGS_ADD_REGISTER64("dec", cpu->cd.ppc.spr[SPR_DEC]); + CPU_SETTINGS_ADD_REGISTER64("hdec", cpu->cd.ppc.spr[SPR_HDEC]); + CPU_SETTINGS_ADD_REGISTER64("srr0", cpu->cd.ppc.spr[SPR_SRR0]); + CPU_SETTINGS_ADD_REGISTER64("srr1", cpu->cd.ppc.spr[SPR_SRR1]); + CPU_SETTINGS_ADD_REGISTER64("sdr1", cpu->cd.ppc.spr[SPR_SDR1]); + CPU_SETTINGS_ADD_REGISTER64("ibat0u", cpu->cd.ppc.spr[SPR_IBAT0U]); + CPU_SETTINGS_ADD_REGISTER64("ibat0l", cpu->cd.ppc.spr[SPR_IBAT0L]); + CPU_SETTINGS_ADD_REGISTER64("ibat1u", cpu->cd.ppc.spr[SPR_IBAT1U]); + CPU_SETTINGS_ADD_REGISTER64("ibat1l", cpu->cd.ppc.spr[SPR_IBAT1L]); + CPU_SETTINGS_ADD_REGISTER64("ibat2u", cpu->cd.ppc.spr[SPR_IBAT2U]); + CPU_SETTINGS_ADD_REGISTER64("ibat2l", cpu->cd.ppc.spr[SPR_IBAT2L]); + CPU_SETTINGS_ADD_REGISTER64("ibat3u", cpu->cd.ppc.spr[SPR_IBAT3U]); + CPU_SETTINGS_ADD_REGISTER64("ibat3l", cpu->cd.ppc.spr[SPR_IBAT3L]); + CPU_SETTINGS_ADD_REGISTER64("dbat0u", cpu->cd.ppc.spr[SPR_DBAT0U]); + CPU_SETTINGS_ADD_REGISTER64("dbat0l", cpu->cd.ppc.spr[SPR_DBAT0L]); + CPU_SETTINGS_ADD_REGISTER64("dbat1u", cpu->cd.ppc.spr[SPR_DBAT1U]); + CPU_SETTINGS_ADD_REGISTER64("dbat1l", cpu->cd.ppc.spr[SPR_DBAT1L]); + CPU_SETTINGS_ADD_REGISTER64("dbat2u", cpu->cd.ppc.spr[SPR_DBAT2U]); + CPU_SETTINGS_ADD_REGISTER64("dbat2l", cpu->cd.ppc.spr[SPR_DBAT2L]); + CPU_SETTINGS_ADD_REGISTER64("dbat3u", cpu->cd.ppc.spr[SPR_DBAT3U]); + CPU_SETTINGS_ADD_REGISTER64("dbat3l", cpu->cd.ppc.spr[SPR_DBAT3L]); + CPU_SETTINGS_ADD_REGISTER64("lr", cpu->cd.ppc.spr[SPR_LR]); + CPU_SETTINGS_ADD_REGISTER32("cr", cpu->cd.ppc.cr); + CPU_SETTINGS_ADD_REGISTER32("fpscr", cpu->cd.ppc.fpscr); + /* Integer GPRs, floating point registers, and segment registers: */ + for (i=0; icd.ppc.gpr[i]); + } + for (i=0; icd.ppc.fpr[i]); + } + for (i=0; i<16; i++) { + char tmpstr[5]; + snprintf(tmpstr, sizeof(tmpstr), "sr%i", i); + CPU_SETTINGS_ADD_REGISTER32(tmpstr, cpu->cd.ppc.sr[i]); + } + + /* Register the CPU as an interrupt handler: */ + { + struct interrupt template; + char name[150]; + snprintf(name, sizeof(name), "%s", cpu->path); + memset(&template, 0, sizeof(template)); + template.line = 0; + template.name = name; + template.extra = cpu; + template.interrupt_assert = ppc_irq_interrupt_assert; + template.interrupt_deassert = ppc_irq_interrupt_deassert; + interrupt_handler_register(&template); + } + return 1; } @@ -251,7 +339,8 @@ *valuep = cpu->cd.ppc.msr; if (check_for_interrupts && cpu->cd.ppc.msr & PPC_MSR_EE) { - if (cpu->cd.ppc.dec_intr_pending) { + if (cpu->cd.ppc.dec_intr_pending && + !(cpu->cd.ppc.cpu_type.flags & PPC_NO_DEC)) { ppc_exception(cpu, PPC_EXCEPTION_DEC); cpu->cd.ppc.dec_intr_pending = 0; } else if (cpu->cd.ppc.irq_asserted) @@ -275,8 +364,8 @@ cpu->cd.ppc.spr[SPR_SRR1] = (cpu->cd.ppc.msr & 0x87c0ffff); if (!quiet_mode) - fatal("[ PPC Exception 0x%x; pc=0x%llx ]\n", exception_nr, - (long long)cpu->pc); + fatal("[ PPC Exception 0x%x; pc=0x%"PRIx64" ]\n", + exception_nr, cpu->pc); /* Disable External Interrupts, Recoverable Interrupt Mode, and go to Supervisor mode */ @@ -284,7 +373,7 @@ cpu->pc = exception_nr * 0x100; if (cpu->cd.ppc.msr & PPC_MSR_IP) - cpu->pc += 0xfff00000; + cpu->pc += 0xfff00000ULL; if (cpu->is_32bit) ppc32_pc_to_pointers(cpu); @@ -315,37 +404,43 @@ debug("cpu%i: pc = 0x", x); if (bits32) - debug("%08x", (int)cpu->pc); + debug("%08"PRIx32, (uint32_t)cpu->pc); else - debug("%016llx", (long long)cpu->pc); + debug("%016"PRIx64, (uint64_t)cpu->pc); debug(" <%s>\n", symbol != NULL? symbol : " no symbol "); debug("cpu%i: lr = 0x", x); if (bits32) - debug("%08x", (int)cpu->cd.ppc.spr[SPR_LR]); + debug("%08"PRIx32, (uint32_t)cpu->cd.ppc.spr[SPR_LR]); else - debug("%016llx", (long long)cpu->cd.ppc.spr[SPR_LR]); - debug(" cr = 0x%08x\n", (int)cpu->cd.ppc.cr); + debug("%016"PRIx64, (uint64_t)cpu->cd.ppc.spr[SPR_LR]); + debug(" cr = 0x%08"PRIx32, (uint32_t)cpu->cd.ppc.cr); - debug("cpu%i: ctr = 0x", x); if (bits32) - debug("%08x", (int)cpu->cd.ppc.spr[SPR_CTR]); + debug(" "); + else + debug("\ncpu%i: ", x); + debug("ctr = 0x", x); + if (bits32) + debug("%08"PRIx32, (uint32_t)cpu->cd.ppc.spr[SPR_CTR]); else - debug("%016llx", (long long)cpu->cd.ppc.spr[SPR_CTR]); + debug("%016"PRIx64, (uint64_t)cpu->cd.ppc.spr[SPR_CTR]); debug(" xer = 0x", x); if (bits32) - debug("%08x\n", (int)cpu->cd.ppc.spr[SPR_XER]); + debug("%08"PRIx32, (uint32_t)cpu->cd.ppc.spr[SPR_XER]); else - debug("%016llx\n", (long long)cpu->cd.ppc.spr[SPR_XER]); + debug("%016"PRIx64, (uint64_t)cpu->cd.ppc.spr[SPR_XER]); + + debug("\n"); if (bits32) { /* 32-bit: */ for (i=0; icd.ppc.gpr[i]); + debug(" r%02i = 0x%08"PRIx32" ", i, + (uint32_t) cpu->cd.ppc.gpr[i]); if ((i % 4) == 3) debug("\n"); } @@ -355,28 +450,49 @@ int r = (i >> 1) + ((i & 1) << 4); if ((i % 2) == 0) debug("cpu%i:", x); - debug(" r%02i = 0x%016llx ", r, - (long long)cpu->cd.ppc.gpr[r]); + debug(" r%02i = 0x%016"PRIx64" ", r, + (uint64_t) cpu->cd.ppc.gpr[r]); if ((i % 2) == 1) debug("\n"); } } /* Other special registers: */ - debug("cpu%i: srr0 = 0x%016llx srr1 = 0x%016llx\n", x, - (long long)cpu->cd.ppc.spr[SPR_SRR0], - (long long)cpu->cd.ppc.spr[SPR_SRR1]); + if (bits32) { + debug("cpu%i: srr0 = 0x%08"PRIx32 + " srr1 = 0x%08"PRIx32"\n", x, + (uint32_t) cpu->cd.ppc.spr[SPR_SRR0], + (uint32_t) cpu->cd.ppc.spr[SPR_SRR1]); + } else { + debug("cpu%i: srr0 = 0x%016"PRIx64 + " srr1 = 0x%016"PRIx64"\n", x, + (uint64_t) cpu->cd.ppc.spr[SPR_SRR0], + (uint64_t) cpu->cd.ppc.spr[SPR_SRR1]); + } + + debug("cpu%i: msr = ", x); reg_access_msr(cpu, &tmp, 0, 0); - debug("cpu%i: msr = 0x%016llx ", x, (long long)tmp); - debug("tb = 0x%08x%08x\n", (int)cpu->cd.ppc.spr[SPR_TBU], - (int)cpu->cd.ppc.spr[SPR_TBL]); - debug("cpu%i: dec = 0x%08x hdec = 0x%08x\n", - x, (int)cpu->cd.ppc.spr[SPR_DEC], - (int)cpu->cd.ppc.spr[SPR_HDEC]); + if (bits32) + debug("0x%08"PRIx32, (uint32_t) tmp); + else + debug("0x%016"PRIx64, (uint64_t) tmp); + + debug(" tb = 0x%08"PRIx32"%08"PRIx32"\n", + (uint32_t) cpu->cd.ppc.spr[SPR_TBU], + (uint32_t) cpu->cd.ppc.spr[SPR_TBL]); + + debug("cpu%i: dec = 0x%08"PRIx32, + x, (uint32_t) cpu->cd.ppc.spr[SPR_DEC]); + if (!bits32) + debug(" hdec = 0x%08"PRIx32"\n", + (uint32_t) cpu->cd.ppc.spr[SPR_HDEC]); + + debug("\n"); } if (coprocs & 1) { - debug("cpu%i: fpscr = 0x%08x\n", x, (int)cpu->cd.ppc.fpscr); + debug("cpu%i: fpscr = 0x%08"PRIx32"\n", + x, (uint32_t) cpu->cd.ppc.fpscr); /* TODO: show floating-point values :-) */ @@ -385,16 +501,16 @@ for (i=0; icd.ppc.fpr[i]); + debug(" f%02i = 0x%016"PRIx64" ", i, + (uint64_t) cpu->cd.ppc.fpr[i]); if ((i % 2) == 1) debug("\n"); } } if (coprocs & 2) { - debug("cpu%i: sdr1 = 0x%llx\n", x, - (long long)cpu->cd.ppc.spr[SPR_SDR1]); + debug("cpu%i: sdr1 = 0x%"PRIx64"\n", x, + (uint64_t) cpu->cd.ppc.spr[SPR_SDR1]); if (cpu->cd.ppc.cpu_type.flags & PPC_601) debug("cpu%i: PPC601-style, TODO!\n"); else { @@ -404,7 +520,8 @@ uint32_t lower = cpu->cd.ppc.spr[spr+1]; uint32_t len = (((upper & BAT_BL) << 15) | 0x1ffff) + 1; - debug("cpu%i: %sbat%i: u=0x%08x l=0x%08x ", + debug("cpu%i: %sbat%i: u=0x%08"PRIx32 + " l=0x%08"PRIx32" ", x, i<4? "i" : "d", i&3, upper, lower); if (!(upper & BAT_V)) { debug(" (not valid)\n"); @@ -439,8 +556,10 @@ if (coprocs & 4) { for (i=0; i<16; i++) { uint32_t s = cpu->cd.ppc.sr[i]; + debug("cpu%i:", x); - debug(" sr%2i = 0x%08x", i, (int)s); + debug(" sr%-2i = 0x%08"PRIx32, i, s); + s &= (SR_TYPE | SR_SUKEY | SR_PRKEY | SR_NOEXEC); if (s != 0) { debug(" ("); @@ -473,133 +592,32 @@ /* - * ppc_cpu_register_match(): + * ppc_cpu_tlbdump(): + * + * Not currently used for PPC. */ -void ppc_cpu_register_match(struct machine *m, char *name, - int writeflag, uint64_t *valuep, int *match_register) +void ppc_cpu_tlbdump(struct machine *m, int x, int rawflag) { - int cpunr = 0; - - /* CPU number: */ - - /* TODO */ - - /* Register name: */ - if (strcasecmp(name, "pc") == 0) { - if (writeflag) { - m->cpus[cpunr]->pc = *valuep; - } else - *valuep = m->cpus[cpunr]->pc; - *match_register = 1; - } else if (strcasecmp(name, "msr") == 0) { - if (writeflag) - m->cpus[cpunr]->cd.ppc.msr = *valuep; - else - *valuep = m->cpus[cpunr]->cd.ppc.msr; - *match_register = 1; - } else if (strcasecmp(name, "lr") == 0) { - if (writeflag) - m->cpus[cpunr]->cd.ppc.spr[SPR_LR] = *valuep; - else - *valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_LR]; - *match_register = 1; - } else if (strcasecmp(name, "cr") == 0) { - if (writeflag) - m->cpus[cpunr]->cd.ppc.cr = *valuep; - else - *valuep = m->cpus[cpunr]->cd.ppc.cr; - *match_register = 1; - } else if (strcasecmp(name, "dec") == 0) { - if (writeflag) - m->cpus[cpunr]->cd.ppc.spr[SPR_DEC] = *valuep; - else - *valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_DEC]; - *match_register = 1; - } else if (strcasecmp(name, "hdec") == 0) { - if (writeflag) - m->cpus[cpunr]->cd.ppc.spr[SPR_HDEC] = *valuep; - else - *valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_HDEC]; - *match_register = 1; - } else if (strcasecmp(name, "ctr") == 0) { - if (writeflag) - m->cpus[cpunr]->cd.ppc.spr[SPR_CTR] = *valuep; - else - *valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_CTR]; - *match_register = 1; - } else if (name[0] == 'r' && isdigit((int)name[1])) { - int nr = atoi(name + 1); - if (nr >= 0 && nr < PPC_NGPRS) { - if (writeflag) { - m->cpus[cpunr]->cd.ppc.gpr[nr] = *valuep; - } else - *valuep = m->cpus[cpunr]->cd.ppc.gpr[nr]; - *match_register = 1; - } - } else if (strcasecmp(name, "xer") == 0) { - if (writeflag) - m->cpus[cpunr]->cd.ppc.spr[SPR_XER] = *valuep; - else - *valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_XER]; - *match_register = 1; - } else if (strcasecmp(name, "fpscr") == 0) { - if (writeflag) - m->cpus[cpunr]->cd.ppc.fpscr = *valuep; - else - *valuep = m->cpus[cpunr]->cd.ppc.fpscr; - *match_register = 1; - } else if (name[0] == 'f' && isdigit((int)name[1])) { - int nr = atoi(name + 1); - if (nr >= 0 && nr < PPC_NFPRS) { - if (writeflag) { - m->cpus[cpunr]->cd.ppc.fpr[nr] = *valuep; - } else - *valuep = m->cpus[cpunr]->cd.ppc.fpr[nr]; - *match_register = 1; - } - } } /* - * ppc_cpu_interrupt(): - * - * 0..31 are used as BeBox interrupt numbers, 32..47 = ISA, - * 64 is used as a "re-assert" signal to cpu->machine->md_interrupt(). - * - * TODO: don't hardcode to BeBox! + * ppc_irq_interrupt_assert(): */ -int ppc_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr) +void ppc_irq_interrupt_assert(struct interrupt *interrupt) { - /* fatal("ppc_cpu_interrupt(): 0x%x\n", (int)irq_nr); */ - if (irq_nr <= 64) { - if (cpu->machine->md_interrupt != NULL) - cpu->machine->md_interrupt( - cpu->machine, cpu, irq_nr, 1); - else - fatal("ppc_cpu_interrupt(): md_interrupt == NULL\n"); - } else { - /* Assert PPC IRQ: */ - cpu->cd.ppc.irq_asserted = 1; - } - return 1; + struct cpu *cpu = (struct cpu *) interrupt->extra; + cpu->cd.ppc.irq_asserted = 1; } /* - * ppc_cpu_interrupt_ack(): + * ppc_irq_interrupt_deassert(): */ -int ppc_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr) +void ppc_irq_interrupt_deassert(struct interrupt *interrupt) { - if (irq_nr <= 64) { - if (cpu->machine->md_interrupt != NULL) - cpu->machine->md_interrupt(cpu->machine, - cpu, irq_nr, 0); - } else { - /* De-assert PPC IRQ: */ - cpu->cd.ppc.irq_asserted = 0; - } - return 1; + struct cpu *cpu = (struct cpu *) interrupt->extra; + cpu->cd.ppc.irq_asserted = 0; } @@ -616,7 +634,7 @@ * cpu->pc for relative addresses. */ int ppc_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr, - int running, uint64_t dumpaddr, int bintrans) + int running, uint64_t dumpaddr) { int hi6, xo, lev, rt, rs, ra, rb, imm, sh, me, rc, l_bit, oe_bit; int spr, aa_bit, lk_bit, bf, bh, bi, bo, mb, nb, bt, ba, bb, fpreg; @@ -638,15 +656,15 @@ debug("cpu%i: ", cpu->cpu_id); if (cpu->cd.ppc.bits == 32) - debug("%08x", (int)dumpaddr); + debug("%08"PRIx32, (uint32_t) dumpaddr); else - debug("%016llx", (long long)dumpaddr); + debug("%016"PRIx64, (uint64_t) dumpaddr); /* NOTE: Fixed to big-endian. */ iword = (instr[0] << 24) + (instr[1] << 16) + (instr[2] << 8) + instr[3]; - debug(": %08x\t", iword); + debug(": %08"PRIx32"\t", iword); /* * Decode the instruction: @@ -655,6 +673,10 @@ hi6 = iword >> 26; switch (hi6) { + case 0x4: + debug("ALTIVEC TODO"); + /* vxor etc */ + break; case PPC_HI6_MULLI: case PPC_HI6_SUBFIC: rt = (iword >> 21) & 31; @@ -743,9 +765,9 @@ if (cpu->cd.ppc.bits == 32) addr &= 0xffffffff; if (cpu->cd.ppc.bits == 32) - debug("0x%x", (int)addr); + debug("0x%"PRIx32, (uint32_t) addr); else - debug("0x%llx", (long long)addr); + debug("0x%"PRIx64, (uint64_t) addr); symbol = get_symbol_name(&cpu->machine->symbol_context, addr, &offset); if (symbol != NULL) @@ -776,9 +798,9 @@ if (cpu->cd.ppc.bits == 32) addr &= 0xffffffff; if (cpu->cd.ppc.bits == 32) - debug("\t0x%x", (int)addr); + debug("\t0x%"PRIx32, (uint32_t) addr); else - debug("\t0x%llx", (long long)addr); + debug("\t0x%"PRIx64, (uint64_t) addr); symbol = get_symbol_name(&cpu->machine->symbol_context, addr, &offset); if (symbol != NULL) @@ -906,14 +928,22 @@ case PPC_HI6_30: xo = (iword >> 2) & 7; switch (xo) { + case PPC_30_RLDICL: case PPC_30_RLDICR: + case PPC_30_RLDIMI: /* mb, not me */ + mnem = NULL; + switch (xo) { + case PPC_30_RLDICL: mnem = "rldicl"; break; + case PPC_30_RLDICR: mnem = "rldicr"; break; + case PPC_30_RLDIMI: mnem = "rldimi"; break; + } rs = (iword >> 21) & 31; ra = (iword >> 16) & 31; sh = ((iword >> 11) & 31) | ((iword & 2) << 4); me = ((iword >> 6) & 31) | (iword & 0x20); rc = iword & 1; - debug("rldicr%s\tr%i,r%i,%i,%i", - rc?".":"", ra, rs, sh, me); + debug("%s%s\tr%i,r%i,%i,%i", + mnem, rc?".":"", ra, rs, sh, me); break; default: debug("unimplemented hi6_30, xo = 0x%x", xo); @@ -1059,7 +1089,7 @@ if (symbol != NULL) debug(" \t<%s", symbol); else - debug(" \t<0x%llx", (long long)addr); + debug(" \t<0x%"PRIx64, (uint64_t) addr); if (wlen > 0 && !fpreg /* && !reverse */) { /* TODO */ } @@ -1077,6 +1107,17 @@ } debug("%s%s\tr%i,r%i", mnem, rc? "." : "", rt, ra); break; + case PPC_31_WRTEEI: + debug("wrteei\t%i", iword & 0x8000? 1 : 0); + break; + case PPC_31_MTMSRD: + /* TODO: Just a guess based on MTMSR */ + rs = (iword >> 21) & 31; + l_bit = (iword >> 16) & 1; + debug("mtmsrd\tr%i", rs); + if (l_bit) + debug(",%i", l_bit); + break; case PPC_31_ADDZE: case PPC_31_ADDZEO: rt = (iword >> 21) & 31; @@ -1219,10 +1260,10 @@ ppc_spr_names[spr]==NULL? "?" : ppc_spr_names[spr]); if (running) { if (cpu->cd.ppc.bits == 32) - debug(": 0x%x", (int) + debug(": 0x%"PRIx32, (uint32_t) cpu->cd.ppc.spr[spr]); else - debug(": 0x%llx", (long long) + debug(": 0x%"PRIx64, (uint64_t) cpu->cd.ppc.spr[spr]); } debug(">"); @@ -1247,6 +1288,12 @@ else debug("tlbie\tr%i", rb); break; + case PPC_31_TLBSX_DOT: + rs = (iword >> 21) & 31; + ra = (iword >> 16) & 31; + rb = (iword >> 11) & 31; + debug("tlbsx.\tr%i,r%i,r%i", rs, ra, rb); + break; case PPC_31_TLBSYNC: debug("tlbsync"); break; @@ -1291,11 +1338,13 @@ debug("%s\tr%i,r%i", mnem, ra, rb); break; case PPC_31_SLW: + case PPC_31_SLD: case PPC_31_SRAW: case PPC_31_SRW: case PPC_31_AND: case PPC_31_ANDC: case PPC_31_NOR: + case PPC_31_EQV: case PPC_31_OR: case PPC_31_ORC: case PPC_31_XOR: @@ -1310,6 +1359,7 @@ switch (xo) { case PPC_31_SLW: mnem = power? "sl" : "slw"; break; + case PPC_31_SLD: mnem = "sld"; break; case PPC_31_SRAW: mnem = power? "sra" : "sraw"; break; case PPC_31_SRW: mnem = @@ -1318,6 +1368,7 @@ case PPC_31_NAND: mnem = "nand"; break; case PPC_31_ANDC: mnem = "andc"; break; case PPC_31_NOR: mnem = "nor"; break; + case PPC_31_EQV: mnem = "eqv"; break; case PPC_31_OR: mnem = "or"; break; case PPC_31_ORC: mnem = "orc"; break; case PPC_31_XOR: mnem = "xor"; break; @@ -1369,10 +1420,10 @@ ppc_spr_names[spr]==NULL? "?" : ppc_spr_names[spr]); if (running) { if (cpu->cd.ppc.bits == 32) - debug(": 0x%x", (int) + debug(": 0x%"PRIx32, (uint32_t) cpu->cd.ppc.gpr[rs]); else - debug(": 0x%llx", (long long) + debug(": 0x%"PRIx64, (uint64_t) cpu->cd.ppc.gpr[rs]); } debug(">"); @@ -1402,6 +1453,9 @@ debug("%s%s\tr%i,r%i,%i", mnem, rc? "." : "", ra, rs, sh); break; + case PPC_31_DSSALL: + debug("dssall"); + break; case PPC_31_EIEIO: debug("%s", power? "eieio?" : "eieio"); break; @@ -1424,6 +1478,23 @@ } debug("%s%s\tr%i,r%i", mnem, rc? "." : "", ra, rs); break; + case PPC_31_LVX: + case PPC_31_LVXL: + case PPC_31_STVX: + case PPC_31_STVXL: + rs = (iword >> 21) & 31; /* vs for stores, */ + ra = (iword >> 16) & 31; /* rs=vl for loads */ + rb = (iword >> 11) & 31; + rc = iword & 1; + switch (xo) { + case PPC_31_LVX: mnem = "lvx"; break; + case PPC_31_LVXL: mnem = "lvxl"; break; + case PPC_31_STVX: mnem = "stvx"; break; + case PPC_31_STVXL: mnem = "stvxl"; break; + } + debug("%s%s\tv%i,r%i,r%i", mnem, rc? "." : "", + rs, ra, rb); + break; default: debug("unimplemented hi6_31, xo = 0x%x", xo); } @@ -1505,7 +1576,7 @@ if (symbol != NULL) debug(" \t<%s", symbol); else - debug(" \t<0x%llx", (long long)addr); + debug(" \t<0x%"PRIx64, (uint64_t) addr); if (wlen > 0 && load && wlen > 0) { unsigned char tw[8]; uint64_t tdata = 0; @@ -1529,12 +1600,12 @@ if (symbol != NULL) debug("%s", symbol); else - debug("0x%llx", - (long long)tdata); + debug("0x%"PRIx64, + (uint64_t) tdata); } else { /* TODO: if load==2, then this is a _signed_ load. */ - debug("0x%llx", (long long)tdata); + debug("0x%"PRIx64, (uint64_t) tdata); } } else debug(": unreadable"); @@ -1552,12 +1623,12 @@ if (symbol != NULL) debug("%s", symbol); else - debug("0x%llx", (long long)tdata); + debug("0x%"PRIx64, (uint64_t) tdata); } else { if (tdata > -256 && tdata < 256) debug("%i", (int)tdata); else - debug("0x%llx", (long long)tdata); + debug("0x%"PRIx64, (uint64_t) tdata); } } debug(">"); @@ -1749,8 +1820,8 @@ break; } else fatal("[ using UNIMPLEMENTED spr %i (%s), pc = " - "0x%llx ]\n", spr, ppc_spr_names[spr] == NULL? - "UNKNOWN" : ppc_spr_names[spr], (long long)pc); + "0x%"PRIx64" ]\n", spr, ppc_spr_names[spr] == NULL? + "UNKNOWN" : ppc_spr_names[spr], (uint64_t) pc); } spr_used[spr >> 2] |= (1 << (spr & 3)); @@ -1795,3 +1866,4 @@ #include "tmp_ppc_tail.c" +