1 |
/* |
/* |
2 |
* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
3 |
* |
* |
4 |
* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
5 |
* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: cpu_ppc.c,v 1.60 2006/07/16 13:32:26 debug Exp $ |
* $Id: cpu_ppc.c,v 1.70 2007/06/15 00:41:21 debug Exp $ |
29 |
* |
* |
30 |
* PowerPC/POWER CPU emulation. |
* PowerPC/POWER CPU emulation. |
31 |
*/ |
*/ |
37 |
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#include "cpu.h" |
#include "cpu.h" |
39 |
#include "devices.h" |
#include "devices.h" |
40 |
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#include "interrupt.h" |
41 |
#include "machine.h" |
#include "machine.h" |
42 |
#include "memory.h" |
#include "memory.h" |
43 |
#include "misc.h" |
#include "misc.h" |
47 |
#include "ppc_pte.h" |
#include "ppc_pte.h" |
48 |
#include "ppc_spr.h" |
#include "ppc_spr.h" |
49 |
#include "ppc_spr_strings.h" |
#include "ppc_spr_strings.h" |
50 |
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#include "settings.h" |
51 |
#include "symbol.h" |
#include "symbol.h" |
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#include "timer.h" |
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#include "useremul.h" |
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#define DYNTRANS_DUALMODE_32 |
#define DYNTRANS_DUALMODE_32 |
57 |
#include "tmp_ppc_head.c" |
#include "tmp_ppc_head.c" |
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60 |
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extern int native_code_translation_enabled; |
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void ppc_pc_to_pointers(struct cpu *); |
void ppc_pc_to_pointers(struct cpu *); |
63 |
void ppc32_pc_to_pointers(struct cpu *); |
void ppc32_pc_to_pointers(struct cpu *); |
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65 |
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void ppc_irq_interrupt_assert(struct interrupt *interrupt); |
66 |
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void ppc_irq_interrupt_deassert(struct interrupt *interrupt); |
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69 |
/* |
/* |
70 |
* ppc_cpu_new(): |
* ppc_cpu_new(): |
96 |
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97 |
cpu->memory_rw = ppc_memory_rw; |
cpu->memory_rw = ppc_memory_rw; |
98 |
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99 |
cpu->cd.ppc.cpu_type = cpu_type_defs[found]; |
cpu->cd.ppc.cpu_type = cpu_type_defs[found]; |
100 |
cpu->name = cpu->cd.ppc.cpu_type.name; |
cpu->name = cpu->cd.ppc.cpu_type.name; |
101 |
cpu->byte_order = EMUL_BIG_ENDIAN; |
cpu->byte_order = EMUL_BIG_ENDIAN; |
102 |
cpu->cd.ppc.mode = MODE_PPC; /* TODO */ |
cpu->cd.ppc.mode = MODE_PPC; /* TODO */ |
103 |
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/* Current operating mode: */ |
/* Current operating mode: */ |
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cpu->cd.ppc.bits = cpu->cd.ppc.cpu_type.bits; |
cpu->cd.ppc.bits = cpu->cd.ppc.cpu_type.bits; |
178 |
if (cpu->machine->prom_emulation) |
if (cpu->machine->prom_emulation) |
179 |
cpu->cd.ppc.of_emul_addr = 0xfff00000; |
cpu->cd.ppc.of_emul_addr = 0xfff00000; |
180 |
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181 |
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/* Add all register names to the settings: */ |
182 |
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CPU_SETTINGS_ADD_REGISTER64("pc", cpu->pc); |
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CPU_SETTINGS_ADD_REGISTER64("msr", cpu->cd.ppc.msr); |
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CPU_SETTINGS_ADD_REGISTER64("ctr", cpu->cd.ppc.spr[SPR_CTR]); |
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CPU_SETTINGS_ADD_REGISTER64("xer", cpu->cd.ppc.spr[SPR_XER]); |
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CPU_SETTINGS_ADD_REGISTER64("dec", cpu->cd.ppc.spr[SPR_DEC]); |
187 |
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CPU_SETTINGS_ADD_REGISTER64("hdec", cpu->cd.ppc.spr[SPR_HDEC]); |
188 |
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CPU_SETTINGS_ADD_REGISTER64("srr0", cpu->cd.ppc.spr[SPR_SRR0]); |
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CPU_SETTINGS_ADD_REGISTER64("srr1", cpu->cd.ppc.spr[SPR_SRR1]); |
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CPU_SETTINGS_ADD_REGISTER64("sdr1", cpu->cd.ppc.spr[SPR_SDR1]); |
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CPU_SETTINGS_ADD_REGISTER64("ibat0u", cpu->cd.ppc.spr[SPR_IBAT0U]); |
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CPU_SETTINGS_ADD_REGISTER64("ibat0l", cpu->cd.ppc.spr[SPR_IBAT0L]); |
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CPU_SETTINGS_ADD_REGISTER64("ibat1u", cpu->cd.ppc.spr[SPR_IBAT1U]); |
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CPU_SETTINGS_ADD_REGISTER64("ibat1l", cpu->cd.ppc.spr[SPR_IBAT1L]); |
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CPU_SETTINGS_ADD_REGISTER64("ibat2u", cpu->cd.ppc.spr[SPR_IBAT2U]); |
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CPU_SETTINGS_ADD_REGISTER64("ibat2l", cpu->cd.ppc.spr[SPR_IBAT2L]); |
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CPU_SETTINGS_ADD_REGISTER64("ibat3u", cpu->cd.ppc.spr[SPR_IBAT3U]); |
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CPU_SETTINGS_ADD_REGISTER64("ibat3l", cpu->cd.ppc.spr[SPR_IBAT3L]); |
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CPU_SETTINGS_ADD_REGISTER64("dbat0u", cpu->cd.ppc.spr[SPR_DBAT0U]); |
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CPU_SETTINGS_ADD_REGISTER64("dbat0l", cpu->cd.ppc.spr[SPR_DBAT0L]); |
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CPU_SETTINGS_ADD_REGISTER64("dbat1u", cpu->cd.ppc.spr[SPR_DBAT1U]); |
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CPU_SETTINGS_ADD_REGISTER64("dbat1l", cpu->cd.ppc.spr[SPR_DBAT1L]); |
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CPU_SETTINGS_ADD_REGISTER64("dbat2u", cpu->cd.ppc.spr[SPR_DBAT2U]); |
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CPU_SETTINGS_ADD_REGISTER64("dbat2l", cpu->cd.ppc.spr[SPR_DBAT2L]); |
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CPU_SETTINGS_ADD_REGISTER64("dbat3u", cpu->cd.ppc.spr[SPR_DBAT3U]); |
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CPU_SETTINGS_ADD_REGISTER64("dbat3l", cpu->cd.ppc.spr[SPR_DBAT3L]); |
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CPU_SETTINGS_ADD_REGISTER64("lr", cpu->cd.ppc.spr[SPR_LR]); |
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CPU_SETTINGS_ADD_REGISTER32("cr", cpu->cd.ppc.cr); |
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CPU_SETTINGS_ADD_REGISTER32("fpscr", cpu->cd.ppc.fpscr); |
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/* Integer GPRs, floating point registers, and segment registers: */ |
211 |
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for (i=0; i<PPC_NGPRS; i++) { |
212 |
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char tmpstr[5]; |
213 |
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snprintf(tmpstr, sizeof(tmpstr), "r%i", i); |
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CPU_SETTINGS_ADD_REGISTER64(tmpstr, cpu->cd.ppc.gpr[i]); |
215 |
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} |
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for (i=0; i<PPC_NFPRS; i++) { |
217 |
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char tmpstr[5]; |
218 |
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snprintf(tmpstr, sizeof(tmpstr), "f%i", i); |
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CPU_SETTINGS_ADD_REGISTER64(tmpstr, cpu->cd.ppc.fpr[i]); |
220 |
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} |
221 |
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for (i=0; i<16; i++) { |
222 |
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char tmpstr[5]; |
223 |
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snprintf(tmpstr, sizeof(tmpstr), "sr%i", i); |
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CPU_SETTINGS_ADD_REGISTER32(tmpstr, cpu->cd.ppc.sr[i]); |
225 |
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} |
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/* Register the CPU as an interrupt handler: */ |
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{ |
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struct interrupt template; |
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char name[150]; |
231 |
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snprintf(name, sizeof(name), "%s", cpu->path); |
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memset(&template, 0, sizeof(template)); |
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template.line = 0; |
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template.name = name; |
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template.extra = cpu; |
236 |
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template.interrupt_assert = ppc_irq_interrupt_assert; |
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template.interrupt_deassert = ppc_irq_interrupt_deassert; |
238 |
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interrupt_handler_register(&template); |
239 |
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} |
240 |
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if (native_code_translation_enabled) |
242 |
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cpu->sampling_timer = timer_add(CPU_SAMPLE_TIMER_HZ, |
243 |
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ppc_timer_sample_tick, cpu); |
244 |
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245 |
return 1; |
return 1; |
246 |
} |
} |
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*valuep = cpu->cd.ppc.msr; |
*valuep = cpu->cd.ppc.msr; |
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348 |
if (check_for_interrupts && cpu->cd.ppc.msr & PPC_MSR_EE) { |
if (check_for_interrupts && cpu->cd.ppc.msr & PPC_MSR_EE) { |
349 |
if (cpu->cd.ppc.dec_intr_pending) { |
if (cpu->cd.ppc.dec_intr_pending && |
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!(cpu->cd.ppc.cpu_type.flags & PPC_NO_DEC)) { |
351 |
ppc_exception(cpu, PPC_EXCEPTION_DEC); |
ppc_exception(cpu, PPC_EXCEPTION_DEC); |
352 |
cpu->cd.ppc.dec_intr_pending = 0; |
cpu->cd.ppc.dec_intr_pending = 0; |
353 |
} else if (cpu->cd.ppc.irq_asserted) |
} else if (cpu->cd.ppc.irq_asserted) |
554 |
for (i=0; i<16; i++) { |
for (i=0; i<16; i++) { |
555 |
uint32_t s = cpu->cd.ppc.sr[i]; |
uint32_t s = cpu->cd.ppc.sr[i]; |
556 |
debug("cpu%i:", x); |
debug("cpu%i:", x); |
557 |
debug(" sr%2i = 0x%08x", i, (int)s); |
debug(" sr%-2i = 0x%08x", i, (int)s); |
558 |
s &= (SR_TYPE | SR_SUKEY | SR_PRKEY | SR_NOEXEC); |
s &= (SR_TYPE | SR_SUKEY | SR_PRKEY | SR_NOEXEC); |
559 |
if (s != 0) { |
if (s != 0) { |
560 |
debug(" ("); |
debug(" ("); |
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/* |
/* |
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* ppc_cpu_register_match(): |
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*/ |
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void ppc_cpu_register_match(struct machine *m, char *name, |
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int writeflag, uint64_t *valuep, int *match_register) |
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{ |
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int cpunr = 0; |
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/* CPU number: */ |
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/* TODO */ |
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/* Register name: */ |
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if (strcasecmp(name, "pc") == 0) { |
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if (writeflag) { |
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m->cpus[cpunr]->pc = *valuep; |
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} else |
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*valuep = m->cpus[cpunr]->pc; |
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*match_register = 1; |
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} else if (strcasecmp(name, "msr") == 0) { |
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if (writeflag) |
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m->cpus[cpunr]->cd.ppc.msr = *valuep; |
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else |
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*valuep = m->cpus[cpunr]->cd.ppc.msr; |
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*match_register = 1; |
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} else if (strcasecmp(name, "lr") == 0) { |
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if (writeflag) |
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m->cpus[cpunr]->cd.ppc.spr[SPR_LR] = *valuep; |
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else |
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*valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_LR]; |
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*match_register = 1; |
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} else if (strcasecmp(name, "cr") == 0) { |
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if (writeflag) |
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m->cpus[cpunr]->cd.ppc.cr = *valuep; |
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else |
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*valuep = m->cpus[cpunr]->cd.ppc.cr; |
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*match_register = 1; |
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} else if (strcasecmp(name, "dec") == 0) { |
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if (writeflag) |
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m->cpus[cpunr]->cd.ppc.spr[SPR_DEC] = *valuep; |
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else |
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*valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_DEC]; |
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*match_register = 1; |
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} else if (strcasecmp(name, "hdec") == 0) { |
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if (writeflag) |
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m->cpus[cpunr]->cd.ppc.spr[SPR_HDEC] = *valuep; |
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else |
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*valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_HDEC]; |
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*match_register = 1; |
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} else if (strcasecmp(name, "ctr") == 0) { |
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if (writeflag) |
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m->cpus[cpunr]->cd.ppc.spr[SPR_CTR] = *valuep; |
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else |
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*valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_CTR]; |
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*match_register = 1; |
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} else if (name[0] == 'r' && isdigit((int)name[1])) { |
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int nr = atoi(name + 1); |
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if (nr >= 0 && nr < PPC_NGPRS) { |
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if (writeflag) { |
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m->cpus[cpunr]->cd.ppc.gpr[nr] = *valuep; |
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} else |
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*valuep = m->cpus[cpunr]->cd.ppc.gpr[nr]; |
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*match_register = 1; |
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} |
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} else if (strcasecmp(name, "xer") == 0) { |
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if (writeflag) |
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m->cpus[cpunr]->cd.ppc.spr[SPR_XER] = *valuep; |
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else |
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*valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_XER]; |
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*match_register = 1; |
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} else if (strcasecmp(name, "fpscr") == 0) { |
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if (writeflag) |
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m->cpus[cpunr]->cd.ppc.fpscr = *valuep; |
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else |
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*valuep = m->cpus[cpunr]->cd.ppc.fpscr; |
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*match_register = 1; |
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} else if (name[0] == 'f' && isdigit((int)name[1])) { |
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int nr = atoi(name + 1); |
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if (nr >= 0 && nr < PPC_NFPRS) { |
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if (writeflag) { |
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m->cpus[cpunr]->cd.ppc.fpr[nr] = *valuep; |
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} else |
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*valuep = m->cpus[cpunr]->cd.ppc.fpr[nr]; |
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*match_register = 1; |
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} |
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} |
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} |
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/* |
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590 |
* ppc_cpu_tlbdump(): |
* ppc_cpu_tlbdump(): |
591 |
* |
* |
592 |
* Not currently used for PPC. |
* Not currently used for PPC. |
596 |
} |
} |
597 |
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598 |
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static void add_response_word(struct cpu *cpu, char *r, uint64_t value, |
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size_t maxlen, int len) |
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{ |
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char *format = (len == 4)? "%08"PRIx64 : "%016"PRIx64; |
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if (len == 4) |
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value &= 0xffffffffULL; |
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if (cpu->byte_order == EMUL_LITTLE_ENDIAN) { |
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if (len == 4) { |
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value = ((value & 0xff) << 24) + |
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((value & 0xff00) << 8) + |
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((value & 0xff0000) >> 8) + |
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((value & 0xff000000) >> 24); |
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} else { |
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value = ((value & 0xff) << 56) + |
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((value & 0xff00) << 40) + |
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((value & 0xff0000) << 24) + |
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((value & 0xff000000ULL) << 8) + |
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((value & 0xff00000000ULL) >> 8) + |
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((value & 0xff0000000000ULL) >> 24) + |
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((value & 0xff000000000000ULL) >> 40) + |
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((value & 0xff00000000000000ULL) >> 56); |
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} |
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} |
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snprintf(r + strlen(r), maxlen - strlen(r), format, (uint64_t)value); |
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} |
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/* |
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* ppc_cpu_gdb_stub(): |
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* |
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* Execute a "remote GDB" command. Returns a newly allocated response string |
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* on success, NULL on failure. |
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*/ |
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char *ppc_cpu_gdb_stub(struct cpu *cpu, char *cmd) |
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{ |
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if (strcmp(cmd, "g") == 0) { |
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int i; |
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char *r; |
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size_t wlen = cpu->is_32bit? |
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sizeof(uint32_t) : sizeof(uint64_t); |
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size_t len = 1 + 76 * wlen; |
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r = malloc(len); |
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if (r == NULL) { |
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fprintf(stderr, "out of memory\n"); |
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exit(1); |
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} |
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r[0] = '\0'; |
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for (i=0; i<128; i++) |
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add_response_word(cpu, r, i, len, wlen); |
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return r; |
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} |
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if (cmd[0] == 'p') { |
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int regnr = strtol(cmd + 1, NULL, 16); |
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size_t wlen = cpu->is_32bit? |
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sizeof(uint32_t) : sizeof(uint64_t); |
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size_t len = 2 * wlen + 1; |
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char *r = malloc(len); |
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r[0] = '\0'; |
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if (regnr >= 0 && regnr <= 31) { |
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add_response_word(cpu, r, |
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cpu->cd.ppc.gpr[regnr], len, wlen); |
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} else if (regnr == 0x40) { |
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add_response_word(cpu, r, cpu->pc, len, wlen); |
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} else if (regnr == 0x42) { |
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add_response_word(cpu, r, cpu->cd.ppc.cr, len, wlen); |
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} else if (regnr == 0x43) { |
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add_response_word(cpu, r, cpu->cd.ppc.spr[SPR_LR], |
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len, wlen); |
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} else if (regnr == 0x44) { |
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add_response_word(cpu, r, cpu->cd.ppc.spr[SPR_CTR], |
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len, wlen); |
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} else if (regnr == 0x45) { |
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add_response_word(cpu, r, cpu->cd.ppc.spr[SPR_XER], |
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len, wlen); |
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} else { |
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/* Unimplemented: */ |
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add_response_word(cpu, r, 0xcc000 + regnr, len, wlen); |
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} |
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return r; |
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} |
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fatal("ppc_cpu_gdb_stub(): TODO\n"); |
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return NULL; |
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} |
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599 |
/* |
/* |
600 |
* ppc_cpu_interrupt(): |
* ppc_irq_interrupt_assert(): |
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* |
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* 0..31 are used as BeBox interrupt numbers, 32..47 = ISA, |
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* 64 is used as a "re-assert" signal to cpu->machine->md_interrupt(). |
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* |
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* TODO: don't hardcode to BeBox! |
|
601 |
*/ |
*/ |
602 |
int ppc_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr) |
void ppc_irq_interrupt_assert(struct interrupt *interrupt) |
603 |
{ |
{ |
604 |
/* fatal("ppc_cpu_interrupt(): 0x%x\n", (int)irq_nr); */ |
struct cpu *cpu = (struct cpu *) interrupt->extra; |
605 |
if (irq_nr <= 64) { |
cpu->cd.ppc.irq_asserted = 1; |
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if (cpu->machine->md_interrupt != NULL) |
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cpu->machine->md_interrupt( |
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cpu->machine, cpu, irq_nr, 1); |
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else |
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fatal("ppc_cpu_interrupt(): md_interrupt == NULL\n"); |
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} else { |
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/* Assert PPC IRQ: */ |
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cpu->cd.ppc.irq_asserted = 1; |
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} |
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return 1; |
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606 |
} |
} |
607 |
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608 |
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609 |
/* |
/* |
610 |
* ppc_cpu_interrupt_ack(): |
* ppc_irq_interrupt_deassert(): |
611 |
*/ |
*/ |
612 |
int ppc_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr) |
void ppc_irq_interrupt_deassert(struct interrupt *interrupt) |
613 |
{ |
{ |
614 |
if (irq_nr <= 64) { |
struct cpu *cpu = (struct cpu *) interrupt->extra; |
615 |
if (cpu->machine->md_interrupt != NULL) |
cpu->cd.ppc.irq_asserted = 0; |
|
cpu->machine->md_interrupt(cpu->machine, |
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cpu, irq_nr, 0); |
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} else { |
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/* De-assert PPC IRQ: */ |
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cpu->cd.ppc.irq_asserted = 0; |
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} |
|
|
return 1; |
|
616 |
} |
} |
617 |
|
|
618 |
|
|