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/* |
/* |
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* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: cpu_ppc.c,v 1.59 2006/06/24 21:47:23 debug Exp $ |
* $Id: cpu_ppc.c,v 1.67 2006/12/30 13:30:54 debug Exp $ |
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* |
* |
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* PowerPC/POWER CPU emulation. |
* PowerPC/POWER CPU emulation. |
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*/ |
*/ |
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#include "cpu.h" |
#include "cpu.h" |
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#include "devices.h" |
#include "devices.h" |
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#include "interrupt.h" |
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#include "machine.h" |
#include "machine.h" |
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#include "memory.h" |
#include "memory.h" |
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#include "misc.h" |
#include "misc.h" |
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#include "ppc_pte.h" |
#include "ppc_pte.h" |
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#include "ppc_spr.h" |
#include "ppc_spr.h" |
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#include "ppc_spr_strings.h" |
#include "ppc_spr_strings.h" |
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#include "settings.h" |
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#include "symbol.h" |
#include "symbol.h" |
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#define DYNTRANS_DUALMODE_32 |
#define DYNTRANS_DUALMODE_32 |
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void ppc_pc_to_pointers(struct cpu *); |
void ppc_pc_to_pointers(struct cpu *); |
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void ppc32_pc_to_pointers(struct cpu *); |
void ppc32_pc_to_pointers(struct cpu *); |
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void ppc_irq_interrupt_assert(struct interrupt *interrupt); |
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void ppc_irq_interrupt_deassert(struct interrupt *interrupt); |
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/* |
/* |
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* ppc_cpu_new(): |
* ppc_cpu_new(): |
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cpu->memory_rw = ppc_memory_rw; |
cpu->memory_rw = ppc_memory_rw; |
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cpu->cd.ppc.cpu_type = cpu_type_defs[found]; |
cpu->cd.ppc.cpu_type = cpu_type_defs[found]; |
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cpu->name = cpu->cd.ppc.cpu_type.name; |
cpu->name = cpu->cd.ppc.cpu_type.name; |
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cpu->byte_order = EMUL_BIG_ENDIAN; |
cpu->byte_order = EMUL_BIG_ENDIAN; |
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cpu->cd.ppc.mode = MODE_PPC; /* TODO */ |
cpu->cd.ppc.mode = MODE_PPC; /* TODO */ |
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/* Current operating mode: */ |
/* Current operating mode: */ |
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cpu->cd.ppc.bits = cpu->cd.ppc.cpu_type.bits; |
cpu->cd.ppc.bits = cpu->cd.ppc.cpu_type.bits; |
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cpu->is_32bit = (cpu->cd.ppc.bits == 32)? 1 : 0; |
cpu->is_32bit = (cpu->cd.ppc.bits == 32)? 1 : 0; |
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if (cpu->is_32bit) { |
if (cpu->is_32bit) { |
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cpu->run_instr = ppc32_run_instr; |
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cpu->update_translation_table = ppc32_update_translation_table; |
cpu->update_translation_table = ppc32_update_translation_table; |
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cpu->invalidate_translation_caches = |
cpu->invalidate_translation_caches = |
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ppc32_invalidate_translation_caches; |
ppc32_invalidate_translation_caches; |
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cpu->invalidate_code_translation = |
cpu->invalidate_code_translation = |
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ppc32_invalidate_code_translation; |
ppc32_invalidate_code_translation; |
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} else { |
} else { |
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cpu->run_instr = ppc_run_instr; |
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cpu->update_translation_table = ppc_update_translation_table; |
cpu->update_translation_table = ppc_update_translation_table; |
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cpu->invalidate_translation_caches = |
cpu->invalidate_translation_caches = |
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ppc_invalidate_translation_caches; |
ppc_invalidate_translation_caches; |
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if (cpu->machine->prom_emulation) |
if (cpu->machine->prom_emulation) |
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cpu->cd.ppc.of_emul_addr = 0xfff00000; |
cpu->cd.ppc.of_emul_addr = 0xfff00000; |
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/* Add all register names to the settings: */ |
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CPU_SETTINGS_ADD_REGISTER64("pc", cpu->pc); |
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CPU_SETTINGS_ADD_REGISTER64("msr", cpu->cd.ppc.msr); |
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CPU_SETTINGS_ADD_REGISTER64("ctr", cpu->cd.ppc.spr[SPR_CTR]); |
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CPU_SETTINGS_ADD_REGISTER64("xer", cpu->cd.ppc.spr[SPR_XER]); |
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CPU_SETTINGS_ADD_REGISTER64("dec", cpu->cd.ppc.spr[SPR_DEC]); |
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CPU_SETTINGS_ADD_REGISTER64("hdec", cpu->cd.ppc.spr[SPR_HDEC]); |
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CPU_SETTINGS_ADD_REGISTER64("srr0", cpu->cd.ppc.spr[SPR_SRR0]); |
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CPU_SETTINGS_ADD_REGISTER64("srr1", cpu->cd.ppc.spr[SPR_SRR1]); |
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CPU_SETTINGS_ADD_REGISTER64("sdr1", cpu->cd.ppc.spr[SPR_SDR1]); |
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CPU_SETTINGS_ADD_REGISTER64("ibat0u", cpu->cd.ppc.spr[SPR_IBAT0U]); |
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CPU_SETTINGS_ADD_REGISTER64("ibat0l", cpu->cd.ppc.spr[SPR_IBAT0L]); |
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CPU_SETTINGS_ADD_REGISTER64("ibat1u", cpu->cd.ppc.spr[SPR_IBAT1U]); |
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CPU_SETTINGS_ADD_REGISTER64("ibat1l", cpu->cd.ppc.spr[SPR_IBAT1L]); |
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CPU_SETTINGS_ADD_REGISTER64("ibat2u", cpu->cd.ppc.spr[SPR_IBAT2U]); |
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CPU_SETTINGS_ADD_REGISTER64("ibat2l", cpu->cd.ppc.spr[SPR_IBAT2L]); |
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CPU_SETTINGS_ADD_REGISTER64("ibat3u", cpu->cd.ppc.spr[SPR_IBAT3U]); |
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CPU_SETTINGS_ADD_REGISTER64("ibat3l", cpu->cd.ppc.spr[SPR_IBAT3L]); |
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CPU_SETTINGS_ADD_REGISTER64("dbat0u", cpu->cd.ppc.spr[SPR_DBAT0U]); |
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CPU_SETTINGS_ADD_REGISTER64("dbat0l", cpu->cd.ppc.spr[SPR_DBAT0L]); |
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CPU_SETTINGS_ADD_REGISTER64("dbat1u", cpu->cd.ppc.spr[SPR_DBAT1U]); |
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CPU_SETTINGS_ADD_REGISTER64("dbat1l", cpu->cd.ppc.spr[SPR_DBAT1L]); |
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CPU_SETTINGS_ADD_REGISTER64("dbat2u", cpu->cd.ppc.spr[SPR_DBAT2U]); |
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CPU_SETTINGS_ADD_REGISTER64("dbat2l", cpu->cd.ppc.spr[SPR_DBAT2L]); |
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CPU_SETTINGS_ADD_REGISTER64("dbat3u", cpu->cd.ppc.spr[SPR_DBAT3U]); |
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CPU_SETTINGS_ADD_REGISTER64("dbat3l", cpu->cd.ppc.spr[SPR_DBAT3L]); |
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CPU_SETTINGS_ADD_REGISTER64("lr", cpu->cd.ppc.spr[SPR_LR]); |
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CPU_SETTINGS_ADD_REGISTER32("cr", cpu->cd.ppc.cr); |
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CPU_SETTINGS_ADD_REGISTER32("fpscr", cpu->cd.ppc.fpscr); |
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/* Integer GPRs, floating point registers, and segment registers: */ |
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for (i=0; i<PPC_NGPRS; i++) { |
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char tmpstr[5]; |
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snprintf(tmpstr, sizeof(tmpstr), "r%i", i); |
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CPU_SETTINGS_ADD_REGISTER64(tmpstr, cpu->cd.ppc.gpr[i]); |
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} |
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for (i=0; i<PPC_NFPRS; i++) { |
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char tmpstr[5]; |
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snprintf(tmpstr, sizeof(tmpstr), "f%i", i); |
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CPU_SETTINGS_ADD_REGISTER64(tmpstr, cpu->cd.ppc.fpr[i]); |
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} |
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for (i=0; i<16; i++) { |
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char tmpstr[5]; |
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snprintf(tmpstr, sizeof(tmpstr), "sr%i", i); |
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CPU_SETTINGS_ADD_REGISTER32(tmpstr, cpu->cd.ppc.sr[i]); |
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} |
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/* Register the CPU as an interrupt handler: */ |
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{ |
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struct interrupt template; |
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char name[150]; |
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snprintf(name, sizeof(name), "%s", cpu->path); |
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memset(&template, 0, sizeof(template)); |
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template.line = 0; |
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template.name = name; |
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template.extra = cpu; |
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template.interrupt_assert = ppc_irq_interrupt_assert; |
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template.interrupt_deassert = ppc_irq_interrupt_deassert; |
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interrupt_handler_register(&template); |
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} |
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return 1; |
return 1; |
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} |
} |
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*valuep = cpu->cd.ppc.msr; |
*valuep = cpu->cd.ppc.msr; |
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if (check_for_interrupts && cpu->cd.ppc.msr & PPC_MSR_EE) { |
if (check_for_interrupts && cpu->cd.ppc.msr & PPC_MSR_EE) { |
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if (cpu->cd.ppc.dec_intr_pending) { |
if (cpu->cd.ppc.dec_intr_pending && |
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!(cpu->cd.ppc.cpu_type.flags & PPC_NO_DEC)) { |
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ppc_exception(cpu, PPC_EXCEPTION_DEC); |
ppc_exception(cpu, PPC_EXCEPTION_DEC); |
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cpu->cd.ppc.dec_intr_pending = 0; |
cpu->cd.ppc.dec_intr_pending = 0; |
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} else if (cpu->cd.ppc.irq_asserted) |
} else if (cpu->cd.ppc.irq_asserted) |
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for (i=0; i<16; i++) { |
for (i=0; i<16; i++) { |
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uint32_t s = cpu->cd.ppc.sr[i]; |
uint32_t s = cpu->cd.ppc.sr[i]; |
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debug("cpu%i:", x); |
debug("cpu%i:", x); |
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debug(" sr%2i = 0x%08x", i, (int)s); |
debug(" sr%-2i = 0x%08x", i, (int)s); |
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s &= (SR_TYPE | SR_SUKEY | SR_PRKEY | SR_NOEXEC); |
s &= (SR_TYPE | SR_SUKEY | SR_PRKEY | SR_NOEXEC); |
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if (s != 0) { |
if (s != 0) { |
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debug(" ("); |
debug(" ("); |
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/* |
/* |
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* ppc_cpu_register_match(): |
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*/ |
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void ppc_cpu_register_match(struct machine *m, char *name, |
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int writeflag, uint64_t *valuep, int *match_register) |
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{ |
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int cpunr = 0; |
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/* CPU number: */ |
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/* TODO */ |
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/* Register name: */ |
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if (strcasecmp(name, "pc") == 0) { |
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if (writeflag) { |
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m->cpus[cpunr]->pc = *valuep; |
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} else |
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*valuep = m->cpus[cpunr]->pc; |
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*match_register = 1; |
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} else if (strcasecmp(name, "msr") == 0) { |
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if (writeflag) |
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m->cpus[cpunr]->cd.ppc.msr = *valuep; |
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else |
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*valuep = m->cpus[cpunr]->cd.ppc.msr; |
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*match_register = 1; |
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} else if (strcasecmp(name, "lr") == 0) { |
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if (writeflag) |
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m->cpus[cpunr]->cd.ppc.spr[SPR_LR] = *valuep; |
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else |
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*valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_LR]; |
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*match_register = 1; |
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} else if (strcasecmp(name, "cr") == 0) { |
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if (writeflag) |
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m->cpus[cpunr]->cd.ppc.cr = *valuep; |
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else |
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*valuep = m->cpus[cpunr]->cd.ppc.cr; |
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*match_register = 1; |
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} else if (strcasecmp(name, "dec") == 0) { |
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if (writeflag) |
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m->cpus[cpunr]->cd.ppc.spr[SPR_DEC] = *valuep; |
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else |
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*valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_DEC]; |
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*match_register = 1; |
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} else if (strcasecmp(name, "hdec") == 0) { |
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if (writeflag) |
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m->cpus[cpunr]->cd.ppc.spr[SPR_HDEC] = *valuep; |
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else |
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*valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_HDEC]; |
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*match_register = 1; |
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} else if (strcasecmp(name, "ctr") == 0) { |
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if (writeflag) |
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m->cpus[cpunr]->cd.ppc.spr[SPR_CTR] = *valuep; |
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else |
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*valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_CTR]; |
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*match_register = 1; |
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} else if (name[0] == 'r' && isdigit((int)name[1])) { |
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int nr = atoi(name + 1); |
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if (nr >= 0 && nr < PPC_NGPRS) { |
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if (writeflag) { |
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m->cpus[cpunr]->cd.ppc.gpr[nr] = *valuep; |
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} else |
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*valuep = m->cpus[cpunr]->cd.ppc.gpr[nr]; |
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*match_register = 1; |
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} |
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} else if (strcasecmp(name, "xer") == 0) { |
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if (writeflag) |
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m->cpus[cpunr]->cd.ppc.spr[SPR_XER] = *valuep; |
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else |
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*valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_XER]; |
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*match_register = 1; |
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} else if (strcasecmp(name, "fpscr") == 0) { |
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if (writeflag) |
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m->cpus[cpunr]->cd.ppc.fpscr = *valuep; |
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else |
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*valuep = m->cpus[cpunr]->cd.ppc.fpscr; |
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*match_register = 1; |
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} else if (name[0] == 'f' && isdigit((int)name[1])) { |
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int nr = atoi(name + 1); |
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if (nr >= 0 && nr < PPC_NFPRS) { |
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if (writeflag) { |
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m->cpus[cpunr]->cd.ppc.fpr[nr] = *valuep; |
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} else |
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*valuep = m->cpus[cpunr]->cd.ppc.fpr[nr]; |
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*match_register = 1; |
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} |
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} |
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} |
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/* |
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* ppc_cpu_tlbdump(): |
* ppc_cpu_tlbdump(): |
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* |
* |
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* Not currently used for PPC. |
* Not currently used for PPC. |
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/* |
/* |
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* ppc_cpu_interrupt(): |
* ppc_irq_interrupt_assert(): |
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* |
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* 0..31 are used as BeBox interrupt numbers, 32..47 = ISA, |
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* 64 is used as a "re-assert" signal to cpu->machine->md_interrupt(). |
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* |
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* TODO: don't hardcode to BeBox! |
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*/ |
*/ |
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int ppc_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr) |
void ppc_irq_interrupt_assert(struct interrupt *interrupt) |
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{ |
{ |
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/* fatal("ppc_cpu_interrupt(): 0x%x\n", (int)irq_nr); */ |
struct cpu *cpu = (struct cpu *) interrupt->extra; |
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if (irq_nr <= 64) { |
cpu->cd.ppc.irq_asserted = 1; |
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if (cpu->machine->md_interrupt != NULL) |
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cpu->machine->md_interrupt( |
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cpu->machine, cpu, irq_nr, 1); |
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else |
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fatal("ppc_cpu_interrupt(): md_interrupt == NULL\n"); |
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} else { |
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/* Assert PPC IRQ: */ |
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cpu->cd.ppc.irq_asserted = 1; |
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} |
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return 1; |
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} |
} |
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/* |
/* |
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* ppc_cpu_interrupt_ack(): |
* ppc_irq_interrupt_deassert(): |
689 |
*/ |
*/ |
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int ppc_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr) |
void ppc_irq_interrupt_deassert(struct interrupt *interrupt) |
691 |
{ |
{ |
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if (irq_nr <= 64) { |
struct cpu *cpu = (struct cpu *) interrupt->extra; |
693 |
if (cpu->machine->md_interrupt != NULL) |
cpu->cd.ppc.irq_asserted = 0; |
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cpu->machine->md_interrupt(cpu->machine, |
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cpu, irq_nr, 0); |
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} else { |
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/* De-assert PPC IRQ: */ |
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cpu->cd.ppc.irq_asserted = 0; |
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} |
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return 1; |
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} |
} |
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