--- trunk/src/cpus/cpu_ppc.c 2007/10/08 16:19:37 22 +++ trunk/src/cpus/cpu_ppc.c 2007/10/08 16:21:17 34 @@ -1,5 +1,5 @@ /* - * Copyright (C) 2005-2006 Anders Gavare. All rights reserved. + * Copyright (C) 2005-2007 Anders Gavare. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -25,7 +25,7 @@ * SUCH DAMAGE. * * - * $Id: cpu_ppc.c,v 1.45 2006/01/24 21:26:01 debug Exp $ + * $Id: cpu_ppc.c,v 1.67 2006/12/30 13:30:54 debug Exp $ * * PowerPC/POWER CPU emulation. */ @@ -37,6 +37,7 @@ #include "cpu.h" #include "devices.h" +#include "interrupt.h" #include "machine.h" #include "memory.h" #include "misc.h" @@ -46,6 +47,7 @@ #include "ppc_pte.h" #include "ppc_spr.h" #include "ppc_spr_strings.h" +#include "settings.h" #include "symbol.h" #define DYNTRANS_DUALMODE_32 @@ -55,6 +57,9 @@ void ppc_pc_to_pointers(struct cpu *); void ppc32_pc_to_pointers(struct cpu *); +void ppc_irq_interrupt_assert(struct interrupt *interrupt); +void ppc_irq_interrupt_deassert(struct interrupt *interrupt); + /* * ppc_cpu_new(): @@ -86,15 +91,18 @@ cpu->memory_rw = ppc_memory_rw; - cpu->cd.ppc.cpu_type = cpu_type_defs[found]; - cpu->name = cpu->cd.ppc.cpu_type.name; - cpu->byte_order = EMUL_BIG_ENDIAN; - cpu->cd.ppc.mode = MODE_PPC; /* TODO */ + cpu->cd.ppc.cpu_type = cpu_type_defs[found]; + cpu->name = cpu->cd.ppc.cpu_type.name; + cpu->byte_order = EMUL_BIG_ENDIAN; + cpu->cd.ppc.mode = MODE_PPC; /* TODO */ /* Current operating mode: */ cpu->cd.ppc.bits = cpu->cd.ppc.cpu_type.bits; cpu->cd.ppc.spr[SPR_PVR] = cpu->cd.ppc.cpu_type.pvr; + /* cpu->cd.ppc.msr = PPC_MSR_IR | PPC_MSR_DR | + PPC_MSR_SF | PPC_MSR_FP; */ + cpu->cd.ppc.spr[SPR_IBAT0U] = 0x00001ffc | BAT_Vs; cpu->cd.ppc.spr[SPR_IBAT0L] = 0x00000000 | BAT_PP_RW; cpu->cd.ppc.spr[SPR_IBAT1U] = 0xc0001ffc | BAT_Vs; @@ -113,12 +121,14 @@ cpu->is_32bit = (cpu->cd.ppc.bits == 32)? 1 : 0; if (cpu->is_32bit) { + cpu->run_instr = ppc32_run_instr; cpu->update_translation_table = ppc32_update_translation_table; cpu->invalidate_translation_caches = ppc32_invalidate_translation_caches; cpu->invalidate_code_translation = ppc32_invalidate_code_translation; } else { + cpu->run_instr = ppc_run_instr; cpu->update_translation_table = ppc_update_translation_table; cpu->invalidate_translation_caches = ppc_invalidate_translation_caches; @@ -126,7 +136,7 @@ ppc_invalidate_code_translation; } - cpu->translate_address = ppc_translate_address; + cpu->translate_v2p = ppc_translate_v2p; /* Only show name and caches etc for CPU nr 0 (in SMP machines): */ if (cpu_id == 0) { @@ -163,6 +173,66 @@ if (cpu->machine->prom_emulation) cpu->cd.ppc.of_emul_addr = 0xfff00000; + /* Add all register names to the settings: */ + CPU_SETTINGS_ADD_REGISTER64("pc", cpu->pc); + CPU_SETTINGS_ADD_REGISTER64("msr", cpu->cd.ppc.msr); + CPU_SETTINGS_ADD_REGISTER64("ctr", cpu->cd.ppc.spr[SPR_CTR]); + CPU_SETTINGS_ADD_REGISTER64("xer", cpu->cd.ppc.spr[SPR_XER]); + CPU_SETTINGS_ADD_REGISTER64("dec", cpu->cd.ppc.spr[SPR_DEC]); + CPU_SETTINGS_ADD_REGISTER64("hdec", cpu->cd.ppc.spr[SPR_HDEC]); + CPU_SETTINGS_ADD_REGISTER64("srr0", cpu->cd.ppc.spr[SPR_SRR0]); + CPU_SETTINGS_ADD_REGISTER64("srr1", cpu->cd.ppc.spr[SPR_SRR1]); + CPU_SETTINGS_ADD_REGISTER64("sdr1", cpu->cd.ppc.spr[SPR_SDR1]); + CPU_SETTINGS_ADD_REGISTER64("ibat0u", cpu->cd.ppc.spr[SPR_IBAT0U]); + CPU_SETTINGS_ADD_REGISTER64("ibat0l", cpu->cd.ppc.spr[SPR_IBAT0L]); + CPU_SETTINGS_ADD_REGISTER64("ibat1u", cpu->cd.ppc.spr[SPR_IBAT1U]); + CPU_SETTINGS_ADD_REGISTER64("ibat1l", cpu->cd.ppc.spr[SPR_IBAT1L]); + CPU_SETTINGS_ADD_REGISTER64("ibat2u", cpu->cd.ppc.spr[SPR_IBAT2U]); + CPU_SETTINGS_ADD_REGISTER64("ibat2l", cpu->cd.ppc.spr[SPR_IBAT2L]); + CPU_SETTINGS_ADD_REGISTER64("ibat3u", cpu->cd.ppc.spr[SPR_IBAT3U]); + CPU_SETTINGS_ADD_REGISTER64("ibat3l", cpu->cd.ppc.spr[SPR_IBAT3L]); + CPU_SETTINGS_ADD_REGISTER64("dbat0u", cpu->cd.ppc.spr[SPR_DBAT0U]); + CPU_SETTINGS_ADD_REGISTER64("dbat0l", cpu->cd.ppc.spr[SPR_DBAT0L]); + CPU_SETTINGS_ADD_REGISTER64("dbat1u", cpu->cd.ppc.spr[SPR_DBAT1U]); + CPU_SETTINGS_ADD_REGISTER64("dbat1l", cpu->cd.ppc.spr[SPR_DBAT1L]); + CPU_SETTINGS_ADD_REGISTER64("dbat2u", cpu->cd.ppc.spr[SPR_DBAT2U]); + CPU_SETTINGS_ADD_REGISTER64("dbat2l", cpu->cd.ppc.spr[SPR_DBAT2L]); + CPU_SETTINGS_ADD_REGISTER64("dbat3u", cpu->cd.ppc.spr[SPR_DBAT3U]); + CPU_SETTINGS_ADD_REGISTER64("dbat3l", cpu->cd.ppc.spr[SPR_DBAT3L]); + CPU_SETTINGS_ADD_REGISTER64("lr", cpu->cd.ppc.spr[SPR_LR]); + CPU_SETTINGS_ADD_REGISTER32("cr", cpu->cd.ppc.cr); + CPU_SETTINGS_ADD_REGISTER32("fpscr", cpu->cd.ppc.fpscr); + /* Integer GPRs, floating point registers, and segment registers: */ + for (i=0; icd.ppc.gpr[i]); + } + for (i=0; icd.ppc.fpr[i]); + } + for (i=0; i<16; i++) { + char tmpstr[5]; + snprintf(tmpstr, sizeof(tmpstr), "sr%i", i); + CPU_SETTINGS_ADD_REGISTER32(tmpstr, cpu->cd.ppc.sr[i]); + } + + /* Register the CPU as an interrupt handler: */ + { + struct interrupt template; + char name[150]; + snprintf(name, sizeof(name), "%s", cpu->path); + memset(&template, 0, sizeof(template)); + template.line = 0; + template.name = name; + template.extra = cpu; + template.interrupt_assert = ppc_irq_interrupt_assert; + template.interrupt_deassert = ppc_irq_interrupt_deassert; + interrupt_handler_register(&template); + } + return 1; } @@ -267,7 +337,8 @@ *valuep = cpu->cd.ppc.msr; if (check_for_interrupts && cpu->cd.ppc.msr & PPC_MSR_EE) { - if (cpu->cd.ppc.dec_intr_pending) { + if (cpu->cd.ppc.dec_intr_pending && + !(cpu->cd.ppc.cpu_type.flags & PPC_NO_DEC)) { ppc_exception(cpu, PPC_EXCEPTION_DEC); cpu->cd.ppc.dec_intr_pending = 0; } else if (cpu->cd.ppc.irq_asserted) @@ -291,7 +362,7 @@ cpu->cd.ppc.spr[SPR_SRR1] = (cpu->cd.ppc.msr & 0x87c0ffff); if (!quiet_mode) - fatal("[ PPC Exception 0x%x; pc=0x%llx ]\n", exception_nr, + fatal("[ PPC Exception 0x%x; pc=0x%"PRIx64" ]\n", exception_nr, (long long)cpu->pc); /* Disable External Interrupts, Recoverable Interrupt Mode, @@ -331,17 +402,17 @@ debug("cpu%i: pc = 0x", x); if (bits32) - debug("%08x", (int)cpu->pc); + debug("%08"PRIx32, (uint32_t)cpu->pc); else - debug("%016llx", (long long)cpu->pc); + debug("%016"PRIx64, (uint64_t)cpu->pc); debug(" <%s>\n", symbol != NULL? symbol : " no symbol "); debug("cpu%i: lr = 0x", x); if (bits32) - debug("%08x", (int)cpu->cd.ppc.spr[SPR_LR]); + debug("%08"PRIx32, (uint32_t)cpu->cd.ppc.spr[SPR_LR]); else - debug("%016llx", (long long)cpu->cd.ppc.spr[SPR_LR]); - debug(" cr = 0x%08x", (int)cpu->cd.ppc.cr); + debug("%016"PRIx64, (uint64_t)cpu->cd.ppc.spr[SPR_LR]); + debug(" cr = 0x%08"PRIx32, (uint32_t)cpu->cd.ppc.cr); if (bits32) debug(" "); @@ -349,15 +420,17 @@ debug("\ncpu%i: ", x); debug("ctr = 0x", x); if (bits32) - debug("%08x", (int)cpu->cd.ppc.spr[SPR_CTR]); + debug("%08"PRIx32, (uint32_t)cpu->cd.ppc.spr[SPR_CTR]); else - debug("%016llx", (long long)cpu->cd.ppc.spr[SPR_CTR]); + debug("%016"PRIx64, (uint64_t)cpu->cd.ppc.spr[SPR_CTR]); debug(" xer = 0x", x); if (bits32) - debug("%08x\n", (int)cpu->cd.ppc.spr[SPR_XER]); + debug("%08"PRIx32, (uint32_t)cpu->cd.ppc.spr[SPR_XER]); else - debug("%016llx\n", (long long)cpu->cd.ppc.spr[SPR_XER]); + debug("%016"PRIx64, (uint64_t)cpu->cd.ppc.spr[SPR_XER]); + + debug("\n"); if (bits32) { /* 32-bit: */ @@ -472,7 +545,7 @@ for (i=0; i<16; i++) { uint32_t s = cpu->cd.ppc.sr[i]; debug("cpu%i:", x); - debug(" sr%2i = 0x%08x", i, (int)s); + debug(" sr%-2i = 0x%08x", i, (int)s); s &= (SR_TYPE | SR_SUKEY | SR_PRKEY | SR_NOEXEC); if (s != 0) { debug(" ("); @@ -505,133 +578,119 @@ /* - * ppc_cpu_register_match(): + * ppc_cpu_tlbdump(): + * + * Not currently used for PPC. */ -void ppc_cpu_register_match(struct machine *m, char *name, - int writeflag, uint64_t *valuep, int *match_register) +void ppc_cpu_tlbdump(struct machine *m, int x, int rawflag) { - int cpunr = 0; - - /* CPU number: */ +} - /* TODO */ - /* Register name: */ - if (strcasecmp(name, "pc") == 0) { - if (writeflag) { - m->cpus[cpunr]->pc = *valuep; - } else - *valuep = m->cpus[cpunr]->pc; - *match_register = 1; - } else if (strcasecmp(name, "msr") == 0) { - if (writeflag) - m->cpus[cpunr]->cd.ppc.msr = *valuep; - else - *valuep = m->cpus[cpunr]->cd.ppc.msr; - *match_register = 1; - } else if (strcasecmp(name, "lr") == 0) { - if (writeflag) - m->cpus[cpunr]->cd.ppc.spr[SPR_LR] = *valuep; - else - *valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_LR]; - *match_register = 1; - } else if (strcasecmp(name, "cr") == 0) { - if (writeflag) - m->cpus[cpunr]->cd.ppc.cr = *valuep; - else - *valuep = m->cpus[cpunr]->cd.ppc.cr; - *match_register = 1; - } else if (strcasecmp(name, "dec") == 0) { - if (writeflag) - m->cpus[cpunr]->cd.ppc.spr[SPR_DEC] = *valuep; - else - *valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_DEC]; - *match_register = 1; - } else if (strcasecmp(name, "hdec") == 0) { - if (writeflag) - m->cpus[cpunr]->cd.ppc.spr[SPR_HDEC] = *valuep; - else - *valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_HDEC]; - *match_register = 1; - } else if (strcasecmp(name, "ctr") == 0) { - if (writeflag) - m->cpus[cpunr]->cd.ppc.spr[SPR_CTR] = *valuep; - else - *valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_CTR]; - *match_register = 1; - } else if (name[0] == 'r' && isdigit((int)name[1])) { - int nr = atoi(name + 1); - if (nr >= 0 && nr < PPC_NGPRS) { - if (writeflag) { - m->cpus[cpunr]->cd.ppc.gpr[nr] = *valuep; - } else - *valuep = m->cpus[cpunr]->cd.ppc.gpr[nr]; - *match_register = 1; - } - } else if (strcasecmp(name, "xer") == 0) { - if (writeflag) - m->cpus[cpunr]->cd.ppc.spr[SPR_XER] = *valuep; - else - *valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_XER]; - *match_register = 1; - } else if (strcasecmp(name, "fpscr") == 0) { - if (writeflag) - m->cpus[cpunr]->cd.ppc.fpscr = *valuep; - else - *valuep = m->cpus[cpunr]->cd.ppc.fpscr; - *match_register = 1; - } else if (name[0] == 'f' && isdigit((int)name[1])) { - int nr = atoi(name + 1); - if (nr >= 0 && nr < PPC_NFPRS) { - if (writeflag) { - m->cpus[cpunr]->cd.ppc.fpr[nr] = *valuep; - } else - *valuep = m->cpus[cpunr]->cd.ppc.fpr[nr]; - *match_register = 1; +static void add_response_word(struct cpu *cpu, char *r, uint64_t value, + size_t maxlen, int len) +{ + char *format = (len == 4)? "%08"PRIx64 : "%016"PRIx64; + if (len == 4) + value &= 0xffffffffULL; + if (cpu->byte_order == EMUL_LITTLE_ENDIAN) { + if (len == 4) { + value = ((value & 0xff) << 24) + + ((value & 0xff00) << 8) + + ((value & 0xff0000) >> 8) + + ((value & 0xff000000) >> 24); + } else { + value = ((value & 0xff) << 56) + + ((value & 0xff00) << 40) + + ((value & 0xff0000) << 24) + + ((value & 0xff000000ULL) << 8) + + ((value & 0xff00000000ULL) >> 8) + + ((value & 0xff0000000000ULL) >> 24) + + ((value & 0xff000000000000ULL) >> 40) + + ((value & 0xff00000000000000ULL) >> 56); } } + snprintf(r + strlen(r), maxlen - strlen(r), format, (uint64_t)value); } /* - * ppc_cpu_interrupt(): - * - * 0..31 are used as BeBox interrupt numbers, 32..47 = ISA, - * 64 is used as a "re-assert" signal to cpu->machine->md_interrupt(). + * ppc_cpu_gdb_stub(): * - * TODO: don't hardcode to BeBox! + * Execute a "remote GDB" command. Returns a newly allocated response string + * on success, NULL on failure. */ -int ppc_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr) +char *ppc_cpu_gdb_stub(struct cpu *cpu, char *cmd) { - /* fatal("ppc_cpu_interrupt(): 0x%x\n", (int)irq_nr); */ - if (irq_nr <= 64) { - if (cpu->machine->md_interrupt != NULL) - cpu->machine->md_interrupt( - cpu->machine, cpu, irq_nr, 1); - else - fatal("ppc_cpu_interrupt(): md_interrupt == NULL\n"); - } else { - /* Assert PPC IRQ: */ - cpu->cd.ppc.irq_asserted = 1; + if (strcmp(cmd, "g") == 0) { + int i; + char *r; + size_t wlen = cpu->is_32bit? + sizeof(uint32_t) : sizeof(uint64_t); + size_t len = 1 + 76 * wlen; + r = malloc(len); + if (r == NULL) { + fprintf(stderr, "out of memory\n"); + exit(1); + } + r[0] = '\0'; + for (i=0; i<128; i++) + add_response_word(cpu, r, i, len, wlen); + return r; } - return 1; + + if (cmd[0] == 'p') { + int regnr = strtol(cmd + 1, NULL, 16); + size_t wlen = cpu->is_32bit? + sizeof(uint32_t) : sizeof(uint64_t); + size_t len = 2 * wlen + 1; + char *r = malloc(len); + r[0] = '\0'; + if (regnr >= 0 && regnr <= 31) { + add_response_word(cpu, r, + cpu->cd.ppc.gpr[regnr], len, wlen); + } else if (regnr == 0x40) { + add_response_word(cpu, r, cpu->pc, len, wlen); + } else if (regnr == 0x42) { + add_response_word(cpu, r, cpu->cd.ppc.cr, len, wlen); + } else if (regnr == 0x43) { + add_response_word(cpu, r, cpu->cd.ppc.spr[SPR_LR], + len, wlen); + } else if (regnr == 0x44) { + add_response_word(cpu, r, cpu->cd.ppc.spr[SPR_CTR], + len, wlen); + } else if (regnr == 0x45) { + add_response_word(cpu, r, cpu->cd.ppc.spr[SPR_XER], + len, wlen); + } else { + /* Unimplemented: */ + add_response_word(cpu, r, 0xcc000 + regnr, len, wlen); + } + return r; + } + + fatal("ppc_cpu_gdb_stub(): TODO\n"); + return NULL; } /* - * ppc_cpu_interrupt_ack(): + * ppc_irq_interrupt_assert(): */ -int ppc_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr) +void ppc_irq_interrupt_assert(struct interrupt *interrupt) { - if (irq_nr <= 64) { - if (cpu->machine->md_interrupt != NULL) - cpu->machine->md_interrupt(cpu->machine, - cpu, irq_nr, 0); - } else { - /* De-assert PPC IRQ: */ - cpu->cd.ppc.irq_asserted = 0; - } - return 1; + struct cpu *cpu = (struct cpu *) interrupt->extra; + cpu->cd.ppc.irq_asserted = 1; +} + + +/* + * ppc_irq_interrupt_deassert(): + */ +void ppc_irq_interrupt_deassert(struct interrupt *interrupt) +{ + struct cpu *cpu = (struct cpu *) interrupt->extra; + cpu->cd.ppc.irq_asserted = 0; } @@ -648,7 +707,7 @@ * cpu->pc for relative addresses. */ int ppc_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr, - int running, uint64_t dumpaddr, int bintrans) + int running, uint64_t dumpaddr) { int hi6, xo, lev, rt, rs, ra, rb, imm, sh, me, rc, l_bit, oe_bit; int spr, aa_bit, lk_bit, bf, bh, bi, bo, mb, nb, bt, ba, bb, fpreg; @@ -942,14 +1001,22 @@ case PPC_HI6_30: xo = (iword >> 2) & 7; switch (xo) { + case PPC_30_RLDICL: case PPC_30_RLDICR: + case PPC_30_RLDIMI: /* mb, not me */ + mnem = NULL; + switch (xo) { + case PPC_30_RLDICL: mnem = "rldicl"; break; + case PPC_30_RLDICR: mnem = "rldicr"; break; + case PPC_30_RLDIMI: mnem = "rldimi"; break; + } rs = (iword >> 21) & 31; ra = (iword >> 16) & 31; sh = ((iword >> 11) & 31) | ((iword & 2) << 4); me = ((iword >> 6) & 31) | (iword & 0x20); rc = iword & 1; - debug("rldicr%s\tr%i,r%i,%i,%i", - rc?".":"", ra, rs, sh, me); + debug("%s%s\tr%i,r%i,%i,%i", + mnem, rc?".":"", ra, rs, sh, me); break; default: debug("unimplemented hi6_30, xo = 0x%x", xo); @@ -1116,6 +1183,14 @@ case PPC_31_WRTEEI: debug("wrteei\t%i", iword & 0x8000? 1 : 0); break; + case PPC_31_MTMSRD: + /* TODO: Just a guess based on MTMSR */ + rs = (iword >> 21) & 31; + l_bit = (iword >> 16) & 1; + debug("mtmsrd\tr%i", rs); + if (l_bit) + debug(",%i", l_bit); + break; case PPC_31_ADDZE: case PPC_31_ADDZEO: rt = (iword >> 21) & 31; @@ -1336,11 +1411,13 @@ debug("%s\tr%i,r%i", mnem, ra, rb); break; case PPC_31_SLW: + case PPC_31_SLD: case PPC_31_SRAW: case PPC_31_SRW: case PPC_31_AND: case PPC_31_ANDC: case PPC_31_NOR: + case PPC_31_EQV: case PPC_31_OR: case PPC_31_ORC: case PPC_31_XOR: @@ -1355,6 +1432,7 @@ switch (xo) { case PPC_31_SLW: mnem = power? "sl" : "slw"; break; + case PPC_31_SLD: mnem = "sld"; break; case PPC_31_SRAW: mnem = power? "sra" : "sraw"; break; case PPC_31_SRW: mnem = @@ -1363,6 +1441,7 @@ case PPC_31_NAND: mnem = "nand"; break; case PPC_31_ANDC: mnem = "andc"; break; case PPC_31_NOR: mnem = "nor"; break; + case PPC_31_EQV: mnem = "eqv"; break; case PPC_31_OR: mnem = "or"; break; case PPC_31_ORC: mnem = "orc"; break; case PPC_31_XOR: mnem = "xor"; break; @@ -1447,6 +1526,9 @@ debug("%s%s\tr%i,r%i,%i", mnem, rc? "." : "", ra, rs, sh); break; + case PPC_31_DSSALL: + debug("dssall"); + break; case PPC_31_EIEIO: debug("%s", power? "eieio?" : "eieio"); break; @@ -1469,17 +1551,22 @@ } debug("%s%s\tr%i,r%i", mnem, rc? "." : "", ra, rs); break; - case 359: - debug("TODO: ALTIVEC 359"); - break; case PPC_31_LVX: - debug("lvx\tTODO: ALTIVEC"); - break; + case PPC_31_LVXL: case PPC_31_STVX: - debug("stvx\tTODO: ALTIVEC"); - break; case PPC_31_STVXL: - debug("stvxl\tTODO: ALTIVEC"); + rs = (iword >> 21) & 31; /* vs for stores, */ + ra = (iword >> 16) & 31; /* rs=vl for loads */ + rb = (iword >> 11) & 31; + rc = iword & 1; + switch (xo) { + case PPC_31_LVX: mnem = "lvx"; break; + case PPC_31_LVXL: mnem = "lvxl"; break; + case PPC_31_STVX: mnem = "stvx"; break; + case PPC_31_STVXL: mnem = "stvxl"; break; + } + debug("%s%s\tv%i,r%i,r%i", mnem, rc? "." : "", + rs, ra, rb); break; default: debug("unimplemented hi6_31, xo = 0x%x", xo); @@ -1852,3 +1939,4 @@ #include "tmp_ppc_tail.c" +