--- trunk/src/cpus/cpu_ppc.c 2007/10/08 16:19:23 20 +++ trunk/src/cpus/cpu_ppc.c 2007/10/08 16:20:40 30 @@ -1,5 +1,5 @@ /* - * Copyright (C) 2005 Anders Gavare. All rights reserved. + * Copyright (C) 2005-2006 Anders Gavare. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -25,7 +25,7 @@ * SUCH DAMAGE. * * - * $Id: cpu_ppc.c,v 1.35 2005/11/24 01:15:06 debug Exp $ + * $Id: cpu_ppc.c,v 1.61 2006/07/24 21:14:52 debug Exp $ * * PowerPC/POWER CPU emulation. */ @@ -40,6 +40,7 @@ #include "machine.h" #include "memory.h" #include "misc.h" +#include "of.h" #include "opcodes_ppc.h" #include "ppc_bat.h" #include "ppc_pte.h" @@ -94,15 +95,35 @@ cpu->cd.ppc.bits = cpu->cd.ppc.cpu_type.bits; cpu->cd.ppc.spr[SPR_PVR] = cpu->cd.ppc.cpu_type.pvr; + /* cpu->cd.ppc.msr = PPC_MSR_IR | PPC_MSR_DR | + PPC_MSR_SF | PPC_MSR_FP; */ + + cpu->cd.ppc.spr[SPR_IBAT0U] = 0x00001ffc | BAT_Vs; + cpu->cd.ppc.spr[SPR_IBAT0L] = 0x00000000 | BAT_PP_RW; + cpu->cd.ppc.spr[SPR_IBAT1U] = 0xc0001ffc | BAT_Vs; + cpu->cd.ppc.spr[SPR_IBAT1L] = 0x00000000 | BAT_PP_RW; + cpu->cd.ppc.spr[SPR_IBAT3U] = 0xf0001ffc | BAT_Vs; + cpu->cd.ppc.spr[SPR_IBAT3L] = 0xf0000000 | BAT_PP_RW; + cpu->cd.ppc.spr[SPR_DBAT0U] = 0x00001ffc | BAT_Vs; + cpu->cd.ppc.spr[SPR_DBAT0L] = 0x00000000 | BAT_PP_RW; + cpu->cd.ppc.spr[SPR_DBAT1U] = 0xc0001ffc | BAT_Vs; + cpu->cd.ppc.spr[SPR_DBAT1L] = 0x00000000 | BAT_PP_RW; + cpu->cd.ppc.spr[SPR_DBAT2U] = 0xe0001ffc | BAT_Vs; + cpu->cd.ppc.spr[SPR_DBAT2L] = 0xe0000000 | BAT_PP_RW; + cpu->cd.ppc.spr[SPR_DBAT3U] = 0xf0001ffc | BAT_Vs; + cpu->cd.ppc.spr[SPR_DBAT3L] = 0xf0000000 | BAT_PP_RW; + cpu->is_32bit = (cpu->cd.ppc.bits == 32)? 1 : 0; if (cpu->is_32bit) { + cpu->run_instr = ppc32_run_instr; cpu->update_translation_table = ppc32_update_translation_table; cpu->invalidate_translation_caches = ppc32_invalidate_translation_caches; cpu->invalidate_code_translation = ppc32_invalidate_code_translation; } else { + cpu->run_instr = ppc_run_instr; cpu->update_translation_table = ppc_update_translation_table; cpu->invalidate_translation_caches = ppc_invalidate_translation_caches; @@ -110,7 +131,7 @@ ppc_invalidate_code_translation; } - cpu->translate_address = ppc_translate_address; + cpu->translate_v2p = ppc_translate_v2p; /* Only show name and caches etc for CPU nr 0 (in SMP machines): */ if (cpu_id == 0) { @@ -251,7 +272,8 @@ *valuep = cpu->cd.ppc.msr; if (check_for_interrupts && cpu->cd.ppc.msr & PPC_MSR_EE) { - if (cpu->cd.ppc.dec_intr_pending) { + if (cpu->cd.ppc.dec_intr_pending && + !(cpu->cd.ppc.cpu_type.flags & PPC_NO_DEC)) { ppc_exception(cpu, PPC_EXCEPTION_DEC); cpu->cd.ppc.dec_intr_pending = 0; } else if (cpu->cd.ppc.irq_asserted) @@ -275,7 +297,7 @@ cpu->cd.ppc.spr[SPR_SRR1] = (cpu->cd.ppc.msr & 0x87c0ffff); if (!quiet_mode) - fatal("[ PPC Exception 0x%x; pc=0x%llx ]\n", exception_nr, + fatal("[ PPC Exception 0x%x; pc=0x%"PRIx64" ]\n", exception_nr, (long long)cpu->pc); /* Disable External Interrupts, Recoverable Interrupt Mode, @@ -284,7 +306,7 @@ cpu->pc = exception_nr * 0x100; if (cpu->cd.ppc.msr & PPC_MSR_IP) - cpu->pc += 0xfff00000; + cpu->pc += 0xfff00000ULL; if (cpu->is_32bit) ppc32_pc_to_pointers(cpu); @@ -315,29 +337,35 @@ debug("cpu%i: pc = 0x", x); if (bits32) - debug("%08x", (int)cpu->pc); + debug("%08"PRIx32, (uint32_t)cpu->pc); else - debug("%016llx", (long long)cpu->pc); + debug("%016"PRIx64, (uint64_t)cpu->pc); debug(" <%s>\n", symbol != NULL? symbol : " no symbol "); debug("cpu%i: lr = 0x", x); if (bits32) - debug("%08x", (int)cpu->cd.ppc.spr[SPR_LR]); + debug("%08"PRIx32, (uint32_t)cpu->cd.ppc.spr[SPR_LR]); else - debug("%016llx", (long long)cpu->cd.ppc.spr[SPR_LR]); - debug(" cr = 0x%08x\n", (int)cpu->cd.ppc.cr); + debug("%016"PRIx64, (uint64_t)cpu->cd.ppc.spr[SPR_LR]); + debug(" cr = 0x%08"PRIx32, (uint32_t)cpu->cd.ppc.cr); - debug("cpu%i: ctr = 0x", x); if (bits32) - debug("%08x", (int)cpu->cd.ppc.spr[SPR_CTR]); + debug(" "); + else + debug("\ncpu%i: ", x); + debug("ctr = 0x", x); + if (bits32) + debug("%08"PRIx32, (uint32_t)cpu->cd.ppc.spr[SPR_CTR]); else - debug("%016llx", (long long)cpu->cd.ppc.spr[SPR_CTR]); + debug("%016"PRIx64, (uint64_t)cpu->cd.ppc.spr[SPR_CTR]); debug(" xer = 0x", x); if (bits32) - debug("%08x\n", (int)cpu->cd.ppc.spr[SPR_XER]); + debug("%08"PRIx32, (uint32_t)cpu->cd.ppc.spr[SPR_XER]); else - debug("%016llx\n", (long long)cpu->cd.ppc.spr[SPR_XER]); + debug("%016"PRIx64, (uint64_t)cpu->cd.ppc.spr[SPR_XER]); + + debug("\n"); if (bits32) { /* 32-bit: */ @@ -363,16 +391,28 @@ } /* Other special registers: */ - debug("cpu%i: srr0 = 0x%016llx srr1 = 0x%016llx\n", x, - (long long)cpu->cd.ppc.spr[SPR_SRR0], - (long long)cpu->cd.ppc.spr[SPR_SRR1]); + if (bits32) { + debug("cpu%i: srr0 = 0x%08x srr1 = 0x%08x\n", x, + (int)cpu->cd.ppc.spr[SPR_SRR0], + (int)cpu->cd.ppc.spr[SPR_SRR1]); + } else { + debug("cpu%i: srr0 = 0x%016llx srr1 = 0x%016llx\n", x, + (long long)cpu->cd.ppc.spr[SPR_SRR0], + (long long)cpu->cd.ppc.spr[SPR_SRR1]); + } + debug("cpu%i: msr = ", x); reg_access_msr(cpu, &tmp, 0, 0); - debug("cpu%i: msr = 0x%016llx ", x, (long long)tmp); + if (bits32) + debug("0x%08x ", (int)tmp); + else + debug("0x%016llx ", (long long)tmp); debug("tb = 0x%08x%08x\n", (int)cpu->cd.ppc.spr[SPR_TBU], (int)cpu->cd.ppc.spr[SPR_TBL]); - debug("cpu%i: dec = 0x%08x hdec = 0x%08x\n", - x, (int)cpu->cd.ppc.spr[SPR_DEC], - (int)cpu->cd.ppc.spr[SPR_HDEC]); + debug("cpu%i: dec = 0x%08x", x, (int)cpu->cd.ppc.spr[SPR_DEC]); + if (!bits32) + debug(" hdec = 0x%08x\n", + (int)cpu->cd.ppc.spr[SPR_HDEC]); + debug("\n"); } if (coprocs & 1) { @@ -562,6 +602,103 @@ /* + * ppc_cpu_tlbdump(): + * + * Not currently used for PPC. + */ +void ppc_cpu_tlbdump(struct machine *m, int x, int rawflag) +{ +} + + +static void add_response_word(struct cpu *cpu, char *r, uint64_t value, + size_t maxlen, int len) +{ + char *format = (len == 4)? "%08"PRIx64 : "%016"PRIx64; + if (len == 4) + value &= 0xffffffffULL; + if (cpu->byte_order == EMUL_LITTLE_ENDIAN) { + if (len == 4) { + value = ((value & 0xff) << 24) + + ((value & 0xff00) << 8) + + ((value & 0xff0000) >> 8) + + ((value & 0xff000000) >> 24); + } else { + value = ((value & 0xff) << 56) + + ((value & 0xff00) << 40) + + ((value & 0xff0000) << 24) + + ((value & 0xff000000ULL) << 8) + + ((value & 0xff00000000ULL) >> 8) + + ((value & 0xff0000000000ULL) >> 24) + + ((value & 0xff000000000000ULL) >> 40) + + ((value & 0xff00000000000000ULL) >> 56); + } + } + snprintf(r + strlen(r), maxlen - strlen(r), format, (uint64_t)value); +} + + +/* + * ppc_cpu_gdb_stub(): + * + * Execute a "remote GDB" command. Returns a newly allocated response string + * on success, NULL on failure. + */ +char *ppc_cpu_gdb_stub(struct cpu *cpu, char *cmd) +{ + if (strcmp(cmd, "g") == 0) { + int i; + char *r; + size_t wlen = cpu->is_32bit? + sizeof(uint32_t) : sizeof(uint64_t); + size_t len = 1 + 76 * wlen; + r = malloc(len); + if (r == NULL) { + fprintf(stderr, "out of memory\n"); + exit(1); + } + r[0] = '\0'; + for (i=0; i<128; i++) + add_response_word(cpu, r, i, len, wlen); + return r; + } + + if (cmd[0] == 'p') { + int regnr = strtol(cmd + 1, NULL, 16); + size_t wlen = cpu->is_32bit? + sizeof(uint32_t) : sizeof(uint64_t); + size_t len = 2 * wlen + 1; + char *r = malloc(len); + r[0] = '\0'; + if (regnr >= 0 && regnr <= 31) { + add_response_word(cpu, r, + cpu->cd.ppc.gpr[regnr], len, wlen); + } else if (regnr == 0x40) { + add_response_word(cpu, r, cpu->pc, len, wlen); + } else if (regnr == 0x42) { + add_response_word(cpu, r, cpu->cd.ppc.cr, len, wlen); + } else if (regnr == 0x43) { + add_response_word(cpu, r, cpu->cd.ppc.spr[SPR_LR], + len, wlen); + } else if (regnr == 0x44) { + add_response_word(cpu, r, cpu->cd.ppc.spr[SPR_CTR], + len, wlen); + } else if (regnr == 0x45) { + add_response_word(cpu, r, cpu->cd.ppc.spr[SPR_XER], + len, wlen); + } else { + /* Unimplemented: */ + add_response_word(cpu, r, 0xcc000 + regnr, len, wlen); + } + return r; + } + + fatal("ppc_cpu_gdb_stub(): TODO\n"); + return NULL; +} + + +/* * ppc_cpu_interrupt(): * * 0..31 are used as BeBox interrupt numbers, 32..47 = ISA, @@ -616,7 +753,7 @@ * cpu->pc for relative addresses. */ int ppc_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr, - int running, uint64_t dumpaddr, int bintrans) + int running, uint64_t dumpaddr) { int hi6, xo, lev, rt, rs, ra, rb, imm, sh, me, rc, l_bit, oe_bit; int spr, aa_bit, lk_bit, bf, bh, bi, bo, mb, nb, bt, ba, bb, fpreg; @@ -655,6 +792,10 @@ hi6 = iword >> 26; switch (hi6) { + case 0x4: + debug("ALTIVEC TODO"); + /* vxor etc */ + break; case PPC_HI6_MULLI: case PPC_HI6_SUBFIC: rt = (iword >> 21) & 31; @@ -906,14 +1047,22 @@ case PPC_HI6_30: xo = (iword >> 2) & 7; switch (xo) { + case PPC_30_RLDICL: case PPC_30_RLDICR: + case PPC_30_RLDIMI: /* mb, not me */ + mnem = NULL; + switch (xo) { + case PPC_30_RLDICL: mnem = "rldicl"; break; + case PPC_30_RLDICR: mnem = "rldicr"; break; + case PPC_30_RLDIMI: mnem = "rldimi"; break; + } rs = (iword >> 21) & 31; ra = (iword >> 16) & 31; sh = ((iword >> 11) & 31) | ((iword & 2) << 4); me = ((iword >> 6) & 31) | (iword & 0x20); rc = iword & 1; - debug("rldicr%s\tr%i,r%i,%i,%i", - rc?".":"", ra, rs, sh, me); + debug("%s%s\tr%i,r%i,%i,%i", + mnem, rc?".":"", ra, rs, sh, me); break; default: debug("unimplemented hi6_30, xo = 0x%x", xo); @@ -1077,6 +1226,17 @@ } debug("%s%s\tr%i,r%i", mnem, rc? "." : "", rt, ra); break; + case PPC_31_WRTEEI: + debug("wrteei\t%i", iword & 0x8000? 1 : 0); + break; + case PPC_31_MTMSRD: + /* TODO: Just a guess based on MTMSR */ + rs = (iword >> 21) & 31; + l_bit = (iword >> 16) & 1; + debug("mtmsrd\tr%i", rs); + if (l_bit) + debug(",%i", l_bit); + break; case PPC_31_ADDZE: case PPC_31_ADDZEO: rt = (iword >> 21) & 31; @@ -1247,6 +1407,12 @@ else debug("tlbie\tr%i", rb); break; + case PPC_31_TLBSX_DOT: + rs = (iword >> 21) & 31; + ra = (iword >> 16) & 31; + rb = (iword >> 11) & 31; + debug("tlbsx.\tr%i,r%i,r%i", rs, ra, rb); + break; case PPC_31_TLBSYNC: debug("tlbsync"); break; @@ -1291,11 +1457,13 @@ debug("%s\tr%i,r%i", mnem, ra, rb); break; case PPC_31_SLW: + case PPC_31_SLD: case PPC_31_SRAW: case PPC_31_SRW: case PPC_31_AND: case PPC_31_ANDC: case PPC_31_NOR: + case PPC_31_EQV: case PPC_31_OR: case PPC_31_ORC: case PPC_31_XOR: @@ -1310,6 +1478,7 @@ switch (xo) { case PPC_31_SLW: mnem = power? "sl" : "slw"; break; + case PPC_31_SLD: mnem = "sld"; break; case PPC_31_SRAW: mnem = power? "sra" : "sraw"; break; case PPC_31_SRW: mnem = @@ -1318,6 +1487,7 @@ case PPC_31_NAND: mnem = "nand"; break; case PPC_31_ANDC: mnem = "andc"; break; case PPC_31_NOR: mnem = "nor"; break; + case PPC_31_EQV: mnem = "eqv"; break; case PPC_31_OR: mnem = "or"; break; case PPC_31_ORC: mnem = "orc"; break; case PPC_31_XOR: mnem = "xor"; break; @@ -1402,6 +1572,9 @@ debug("%s%s\tr%i,r%i,%i", mnem, rc? "." : "", ra, rs, sh); break; + case PPC_31_DSSALL: + debug("dssall"); + break; case PPC_31_EIEIO: debug("%s", power? "eieio?" : "eieio"); break; @@ -1424,6 +1597,23 @@ } debug("%s%s\tr%i,r%i", mnem, rc? "." : "", ra, rs); break; + case PPC_31_LVX: + case PPC_31_LVXL: + case PPC_31_STVX: + case PPC_31_STVXL: + rs = (iword >> 21) & 31; /* vs for stores, */ + ra = (iword >> 16) & 31; /* rs=vl for loads */ + rb = (iword >> 11) & 31; + rc = iword & 1; + switch (xo) { + case PPC_31_LVX: mnem = "lvx"; break; + case PPC_31_LVXL: mnem = "lvxl"; break; + case PPC_31_STVX: mnem = "stvx"; break; + case PPC_31_STVXL: mnem = "stvxl"; break; + } + debug("%s%s\tv%i,r%i,r%i", mnem, rc? "." : "", + rs, ra, rb); + break; default: debug("unimplemented hi6_31, xo = 0x%x", xo); } @@ -1795,3 +1985,4 @@ #include "tmp_ppc_tail.c" +