1 |
/* |
/* |
2 |
* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
3 |
* |
* |
4 |
* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
5 |
* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: cpu_ppc.c,v 1.45 2006/01/24 21:26:01 debug Exp $ |
* $Id: cpu_ppc.c,v 1.70 2007/06/15 00:41:21 debug Exp $ |
29 |
* |
* |
30 |
* PowerPC/POWER CPU emulation. |
* PowerPC/POWER CPU emulation. |
31 |
*/ |
*/ |
37 |
|
|
38 |
#include "cpu.h" |
#include "cpu.h" |
39 |
#include "devices.h" |
#include "devices.h" |
40 |
|
#include "interrupt.h" |
41 |
#include "machine.h" |
#include "machine.h" |
42 |
#include "memory.h" |
#include "memory.h" |
43 |
#include "misc.h" |
#include "misc.h" |
47 |
#include "ppc_pte.h" |
#include "ppc_pte.h" |
48 |
#include "ppc_spr.h" |
#include "ppc_spr.h" |
49 |
#include "ppc_spr_strings.h" |
#include "ppc_spr_strings.h" |
50 |
|
#include "settings.h" |
51 |
#include "symbol.h" |
#include "symbol.h" |
52 |
|
#include "timer.h" |
53 |
|
#include "useremul.h" |
54 |
|
|
55 |
|
|
56 |
#define DYNTRANS_DUALMODE_32 |
#define DYNTRANS_DUALMODE_32 |
57 |
#include "tmp_ppc_head.c" |
#include "tmp_ppc_head.c" |
58 |
|
|
59 |
|
|
60 |
|
extern int native_code_translation_enabled; |
61 |
|
|
62 |
void ppc_pc_to_pointers(struct cpu *); |
void ppc_pc_to_pointers(struct cpu *); |
63 |
void ppc32_pc_to_pointers(struct cpu *); |
void ppc32_pc_to_pointers(struct cpu *); |
64 |
|
|
65 |
|
void ppc_irq_interrupt_assert(struct interrupt *interrupt); |
66 |
|
void ppc_irq_interrupt_deassert(struct interrupt *interrupt); |
67 |
|
|
68 |
|
|
69 |
/* |
/* |
70 |
* ppc_cpu_new(): |
* ppc_cpu_new(): |
96 |
|
|
97 |
cpu->memory_rw = ppc_memory_rw; |
cpu->memory_rw = ppc_memory_rw; |
98 |
|
|
99 |
cpu->cd.ppc.cpu_type = cpu_type_defs[found]; |
cpu->cd.ppc.cpu_type = cpu_type_defs[found]; |
100 |
cpu->name = cpu->cd.ppc.cpu_type.name; |
cpu->name = cpu->cd.ppc.cpu_type.name; |
101 |
cpu->byte_order = EMUL_BIG_ENDIAN; |
cpu->byte_order = EMUL_BIG_ENDIAN; |
102 |
cpu->cd.ppc.mode = MODE_PPC; /* TODO */ |
cpu->cd.ppc.mode = MODE_PPC; /* TODO */ |
103 |
|
|
104 |
/* Current operating mode: */ |
/* Current operating mode: */ |
105 |
cpu->cd.ppc.bits = cpu->cd.ppc.cpu_type.bits; |
cpu->cd.ppc.bits = cpu->cd.ppc.cpu_type.bits; |
106 |
cpu->cd.ppc.spr[SPR_PVR] = cpu->cd.ppc.cpu_type.pvr; |
cpu->cd.ppc.spr[SPR_PVR] = cpu->cd.ppc.cpu_type.pvr; |
107 |
|
|
108 |
|
/* cpu->cd.ppc.msr = PPC_MSR_IR | PPC_MSR_DR | |
109 |
|
PPC_MSR_SF | PPC_MSR_FP; */ |
110 |
|
|
111 |
cpu->cd.ppc.spr[SPR_IBAT0U] = 0x00001ffc | BAT_Vs; |
cpu->cd.ppc.spr[SPR_IBAT0U] = 0x00001ffc | BAT_Vs; |
112 |
cpu->cd.ppc.spr[SPR_IBAT0L] = 0x00000000 | BAT_PP_RW; |
cpu->cd.ppc.spr[SPR_IBAT0L] = 0x00000000 | BAT_PP_RW; |
113 |
cpu->cd.ppc.spr[SPR_IBAT1U] = 0xc0001ffc | BAT_Vs; |
cpu->cd.ppc.spr[SPR_IBAT1U] = 0xc0001ffc | BAT_Vs; |
126 |
cpu->is_32bit = (cpu->cd.ppc.bits == 32)? 1 : 0; |
cpu->is_32bit = (cpu->cd.ppc.bits == 32)? 1 : 0; |
127 |
|
|
128 |
if (cpu->is_32bit) { |
if (cpu->is_32bit) { |
129 |
|
cpu->run_instr = ppc32_run_instr; |
130 |
cpu->update_translation_table = ppc32_update_translation_table; |
cpu->update_translation_table = ppc32_update_translation_table; |
131 |
cpu->invalidate_translation_caches = |
cpu->invalidate_translation_caches = |
132 |
ppc32_invalidate_translation_caches; |
ppc32_invalidate_translation_caches; |
133 |
cpu->invalidate_code_translation = |
cpu->invalidate_code_translation = |
134 |
ppc32_invalidate_code_translation; |
ppc32_invalidate_code_translation; |
135 |
} else { |
} else { |
136 |
|
cpu->run_instr = ppc_run_instr; |
137 |
cpu->update_translation_table = ppc_update_translation_table; |
cpu->update_translation_table = ppc_update_translation_table; |
138 |
cpu->invalidate_translation_caches = |
cpu->invalidate_translation_caches = |
139 |
ppc_invalidate_translation_caches; |
ppc_invalidate_translation_caches; |
141 |
ppc_invalidate_code_translation; |
ppc_invalidate_code_translation; |
142 |
} |
} |
143 |
|
|
144 |
cpu->translate_address = ppc_translate_address; |
cpu->translate_v2p = ppc_translate_v2p; |
145 |
|
|
146 |
/* Only show name and caches etc for CPU nr 0 (in SMP machines): */ |
/* Only show name and caches etc for CPU nr 0 (in SMP machines): */ |
147 |
if (cpu_id == 0) { |
if (cpu_id == 0) { |
178 |
if (cpu->machine->prom_emulation) |
if (cpu->machine->prom_emulation) |
179 |
cpu->cd.ppc.of_emul_addr = 0xfff00000; |
cpu->cd.ppc.of_emul_addr = 0xfff00000; |
180 |
|
|
181 |
|
/* Add all register names to the settings: */ |
182 |
|
CPU_SETTINGS_ADD_REGISTER64("pc", cpu->pc); |
183 |
|
CPU_SETTINGS_ADD_REGISTER64("msr", cpu->cd.ppc.msr); |
184 |
|
CPU_SETTINGS_ADD_REGISTER64("ctr", cpu->cd.ppc.spr[SPR_CTR]); |
185 |
|
CPU_SETTINGS_ADD_REGISTER64("xer", cpu->cd.ppc.spr[SPR_XER]); |
186 |
|
CPU_SETTINGS_ADD_REGISTER64("dec", cpu->cd.ppc.spr[SPR_DEC]); |
187 |
|
CPU_SETTINGS_ADD_REGISTER64("hdec", cpu->cd.ppc.spr[SPR_HDEC]); |
188 |
|
CPU_SETTINGS_ADD_REGISTER64("srr0", cpu->cd.ppc.spr[SPR_SRR0]); |
189 |
|
CPU_SETTINGS_ADD_REGISTER64("srr1", cpu->cd.ppc.spr[SPR_SRR1]); |
190 |
|
CPU_SETTINGS_ADD_REGISTER64("sdr1", cpu->cd.ppc.spr[SPR_SDR1]); |
191 |
|
CPU_SETTINGS_ADD_REGISTER64("ibat0u", cpu->cd.ppc.spr[SPR_IBAT0U]); |
192 |
|
CPU_SETTINGS_ADD_REGISTER64("ibat0l", cpu->cd.ppc.spr[SPR_IBAT0L]); |
193 |
|
CPU_SETTINGS_ADD_REGISTER64("ibat1u", cpu->cd.ppc.spr[SPR_IBAT1U]); |
194 |
|
CPU_SETTINGS_ADD_REGISTER64("ibat1l", cpu->cd.ppc.spr[SPR_IBAT1L]); |
195 |
|
CPU_SETTINGS_ADD_REGISTER64("ibat2u", cpu->cd.ppc.spr[SPR_IBAT2U]); |
196 |
|
CPU_SETTINGS_ADD_REGISTER64("ibat2l", cpu->cd.ppc.spr[SPR_IBAT2L]); |
197 |
|
CPU_SETTINGS_ADD_REGISTER64("ibat3u", cpu->cd.ppc.spr[SPR_IBAT3U]); |
198 |
|
CPU_SETTINGS_ADD_REGISTER64("ibat3l", cpu->cd.ppc.spr[SPR_IBAT3L]); |
199 |
|
CPU_SETTINGS_ADD_REGISTER64("dbat0u", cpu->cd.ppc.spr[SPR_DBAT0U]); |
200 |
|
CPU_SETTINGS_ADD_REGISTER64("dbat0l", cpu->cd.ppc.spr[SPR_DBAT0L]); |
201 |
|
CPU_SETTINGS_ADD_REGISTER64("dbat1u", cpu->cd.ppc.spr[SPR_DBAT1U]); |
202 |
|
CPU_SETTINGS_ADD_REGISTER64("dbat1l", cpu->cd.ppc.spr[SPR_DBAT1L]); |
203 |
|
CPU_SETTINGS_ADD_REGISTER64("dbat2u", cpu->cd.ppc.spr[SPR_DBAT2U]); |
204 |
|
CPU_SETTINGS_ADD_REGISTER64("dbat2l", cpu->cd.ppc.spr[SPR_DBAT2L]); |
205 |
|
CPU_SETTINGS_ADD_REGISTER64("dbat3u", cpu->cd.ppc.spr[SPR_DBAT3U]); |
206 |
|
CPU_SETTINGS_ADD_REGISTER64("dbat3l", cpu->cd.ppc.spr[SPR_DBAT3L]); |
207 |
|
CPU_SETTINGS_ADD_REGISTER64("lr", cpu->cd.ppc.spr[SPR_LR]); |
208 |
|
CPU_SETTINGS_ADD_REGISTER32("cr", cpu->cd.ppc.cr); |
209 |
|
CPU_SETTINGS_ADD_REGISTER32("fpscr", cpu->cd.ppc.fpscr); |
210 |
|
/* Integer GPRs, floating point registers, and segment registers: */ |
211 |
|
for (i=0; i<PPC_NGPRS; i++) { |
212 |
|
char tmpstr[5]; |
213 |
|
snprintf(tmpstr, sizeof(tmpstr), "r%i", i); |
214 |
|
CPU_SETTINGS_ADD_REGISTER64(tmpstr, cpu->cd.ppc.gpr[i]); |
215 |
|
} |
216 |
|
for (i=0; i<PPC_NFPRS; i++) { |
217 |
|
char tmpstr[5]; |
218 |
|
snprintf(tmpstr, sizeof(tmpstr), "f%i", i); |
219 |
|
CPU_SETTINGS_ADD_REGISTER64(tmpstr, cpu->cd.ppc.fpr[i]); |
220 |
|
} |
221 |
|
for (i=0; i<16; i++) { |
222 |
|
char tmpstr[5]; |
223 |
|
snprintf(tmpstr, sizeof(tmpstr), "sr%i", i); |
224 |
|
CPU_SETTINGS_ADD_REGISTER32(tmpstr, cpu->cd.ppc.sr[i]); |
225 |
|
} |
226 |
|
|
227 |
|
/* Register the CPU as an interrupt handler: */ |
228 |
|
{ |
229 |
|
struct interrupt template; |
230 |
|
char name[150]; |
231 |
|
snprintf(name, sizeof(name), "%s", cpu->path); |
232 |
|
memset(&template, 0, sizeof(template)); |
233 |
|
template.line = 0; |
234 |
|
template.name = name; |
235 |
|
template.extra = cpu; |
236 |
|
template.interrupt_assert = ppc_irq_interrupt_assert; |
237 |
|
template.interrupt_deassert = ppc_irq_interrupt_deassert; |
238 |
|
interrupt_handler_register(&template); |
239 |
|
} |
240 |
|
|
241 |
|
if (native_code_translation_enabled) |
242 |
|
cpu->sampling_timer = timer_add(CPU_SAMPLE_TIMER_HZ, |
243 |
|
ppc_timer_sample_tick, cpu); |
244 |
|
|
245 |
return 1; |
return 1; |
246 |
} |
} |
247 |
|
|
346 |
*valuep = cpu->cd.ppc.msr; |
*valuep = cpu->cd.ppc.msr; |
347 |
|
|
348 |
if (check_for_interrupts && cpu->cd.ppc.msr & PPC_MSR_EE) { |
if (check_for_interrupts && cpu->cd.ppc.msr & PPC_MSR_EE) { |
349 |
if (cpu->cd.ppc.dec_intr_pending) { |
if (cpu->cd.ppc.dec_intr_pending && |
350 |
|
!(cpu->cd.ppc.cpu_type.flags & PPC_NO_DEC)) { |
351 |
ppc_exception(cpu, PPC_EXCEPTION_DEC); |
ppc_exception(cpu, PPC_EXCEPTION_DEC); |
352 |
cpu->cd.ppc.dec_intr_pending = 0; |
cpu->cd.ppc.dec_intr_pending = 0; |
353 |
} else if (cpu->cd.ppc.irq_asserted) |
} else if (cpu->cd.ppc.irq_asserted) |
371 |
cpu->cd.ppc.spr[SPR_SRR1] = (cpu->cd.ppc.msr & 0x87c0ffff); |
cpu->cd.ppc.spr[SPR_SRR1] = (cpu->cd.ppc.msr & 0x87c0ffff); |
372 |
|
|
373 |
if (!quiet_mode) |
if (!quiet_mode) |
374 |
fatal("[ PPC Exception 0x%x; pc=0x%llx ]\n", exception_nr, |
fatal("[ PPC Exception 0x%x; pc=0x%"PRIx64" ]\n", exception_nr, |
375 |
(long long)cpu->pc); |
(long long)cpu->pc); |
376 |
|
|
377 |
/* Disable External Interrupts, Recoverable Interrupt Mode, |
/* Disable External Interrupts, Recoverable Interrupt Mode, |
411 |
|
|
412 |
debug("cpu%i: pc = 0x", x); |
debug("cpu%i: pc = 0x", x); |
413 |
if (bits32) |
if (bits32) |
414 |
debug("%08x", (int)cpu->pc); |
debug("%08"PRIx32, (uint32_t)cpu->pc); |
415 |
else |
else |
416 |
debug("%016llx", (long long)cpu->pc); |
debug("%016"PRIx64, (uint64_t)cpu->pc); |
417 |
debug(" <%s>\n", symbol != NULL? symbol : " no symbol "); |
debug(" <%s>\n", symbol != NULL? symbol : " no symbol "); |
418 |
|
|
419 |
debug("cpu%i: lr = 0x", x); |
debug("cpu%i: lr = 0x", x); |
420 |
if (bits32) |
if (bits32) |
421 |
debug("%08x", (int)cpu->cd.ppc.spr[SPR_LR]); |
debug("%08"PRIx32, (uint32_t)cpu->cd.ppc.spr[SPR_LR]); |
422 |
else |
else |
423 |
debug("%016llx", (long long)cpu->cd.ppc.spr[SPR_LR]); |
debug("%016"PRIx64, (uint64_t)cpu->cd.ppc.spr[SPR_LR]); |
424 |
debug(" cr = 0x%08x", (int)cpu->cd.ppc.cr); |
debug(" cr = 0x%08"PRIx32, (uint32_t)cpu->cd.ppc.cr); |
425 |
|
|
426 |
if (bits32) |
if (bits32) |
427 |
debug(" "); |
debug(" "); |
429 |
debug("\ncpu%i: ", x); |
debug("\ncpu%i: ", x); |
430 |
debug("ctr = 0x", x); |
debug("ctr = 0x", x); |
431 |
if (bits32) |
if (bits32) |
432 |
debug("%08x", (int)cpu->cd.ppc.spr[SPR_CTR]); |
debug("%08"PRIx32, (uint32_t)cpu->cd.ppc.spr[SPR_CTR]); |
433 |
else |
else |
434 |
debug("%016llx", (long long)cpu->cd.ppc.spr[SPR_CTR]); |
debug("%016"PRIx64, (uint64_t)cpu->cd.ppc.spr[SPR_CTR]); |
435 |
|
|
436 |
debug(" xer = 0x", x); |
debug(" xer = 0x", x); |
437 |
if (bits32) |
if (bits32) |
438 |
debug("%08x\n", (int)cpu->cd.ppc.spr[SPR_XER]); |
debug("%08"PRIx32, (uint32_t)cpu->cd.ppc.spr[SPR_XER]); |
439 |
else |
else |
440 |
debug("%016llx\n", (long long)cpu->cd.ppc.spr[SPR_XER]); |
debug("%016"PRIx64, (uint64_t)cpu->cd.ppc.spr[SPR_XER]); |
441 |
|
|
442 |
|
debug("\n"); |
443 |
|
|
444 |
if (bits32) { |
if (bits32) { |
445 |
/* 32-bit: */ |
/* 32-bit: */ |
554 |
for (i=0; i<16; i++) { |
for (i=0; i<16; i++) { |
555 |
uint32_t s = cpu->cd.ppc.sr[i]; |
uint32_t s = cpu->cd.ppc.sr[i]; |
556 |
debug("cpu%i:", x); |
debug("cpu%i:", x); |
557 |
debug(" sr%2i = 0x%08x", i, (int)s); |
debug(" sr%-2i = 0x%08x", i, (int)s); |
558 |
s &= (SR_TYPE | SR_SUKEY | SR_PRKEY | SR_NOEXEC); |
s &= (SR_TYPE | SR_SUKEY | SR_PRKEY | SR_NOEXEC); |
559 |
if (s != 0) { |
if (s != 0) { |
560 |
debug(" ("); |
debug(" ("); |
587 |
|
|
588 |
|
|
589 |
/* |
/* |
590 |
* ppc_cpu_register_match(): |
* ppc_cpu_tlbdump(): |
591 |
|
* |
592 |
|
* Not currently used for PPC. |
593 |
*/ |
*/ |
594 |
void ppc_cpu_register_match(struct machine *m, char *name, |
void ppc_cpu_tlbdump(struct machine *m, int x, int rawflag) |
|
int writeflag, uint64_t *valuep, int *match_register) |
|
595 |
{ |
{ |
|
int cpunr = 0; |
|
|
|
|
|
/* CPU number: */ |
|
|
|
|
|
/* TODO */ |
|
|
|
|
|
/* Register name: */ |
|
|
if (strcasecmp(name, "pc") == 0) { |
|
|
if (writeflag) { |
|
|
m->cpus[cpunr]->pc = *valuep; |
|
|
} else |
|
|
*valuep = m->cpus[cpunr]->pc; |
|
|
*match_register = 1; |
|
|
} else if (strcasecmp(name, "msr") == 0) { |
|
|
if (writeflag) |
|
|
m->cpus[cpunr]->cd.ppc.msr = *valuep; |
|
|
else |
|
|
*valuep = m->cpus[cpunr]->cd.ppc.msr; |
|
|
*match_register = 1; |
|
|
} else if (strcasecmp(name, "lr") == 0) { |
|
|
if (writeflag) |
|
|
m->cpus[cpunr]->cd.ppc.spr[SPR_LR] = *valuep; |
|
|
else |
|
|
*valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_LR]; |
|
|
*match_register = 1; |
|
|
} else if (strcasecmp(name, "cr") == 0) { |
|
|
if (writeflag) |
|
|
m->cpus[cpunr]->cd.ppc.cr = *valuep; |
|
|
else |
|
|
*valuep = m->cpus[cpunr]->cd.ppc.cr; |
|
|
*match_register = 1; |
|
|
} else if (strcasecmp(name, "dec") == 0) { |
|
|
if (writeflag) |
|
|
m->cpus[cpunr]->cd.ppc.spr[SPR_DEC] = *valuep; |
|
|
else |
|
|
*valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_DEC]; |
|
|
*match_register = 1; |
|
|
} else if (strcasecmp(name, "hdec") == 0) { |
|
|
if (writeflag) |
|
|
m->cpus[cpunr]->cd.ppc.spr[SPR_HDEC] = *valuep; |
|
|
else |
|
|
*valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_HDEC]; |
|
|
*match_register = 1; |
|
|
} else if (strcasecmp(name, "ctr") == 0) { |
|
|
if (writeflag) |
|
|
m->cpus[cpunr]->cd.ppc.spr[SPR_CTR] = *valuep; |
|
|
else |
|
|
*valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_CTR]; |
|
|
*match_register = 1; |
|
|
} else if (name[0] == 'r' && isdigit((int)name[1])) { |
|
|
int nr = atoi(name + 1); |
|
|
if (nr >= 0 && nr < PPC_NGPRS) { |
|
|
if (writeflag) { |
|
|
m->cpus[cpunr]->cd.ppc.gpr[nr] = *valuep; |
|
|
} else |
|
|
*valuep = m->cpus[cpunr]->cd.ppc.gpr[nr]; |
|
|
*match_register = 1; |
|
|
} |
|
|
} else if (strcasecmp(name, "xer") == 0) { |
|
|
if (writeflag) |
|
|
m->cpus[cpunr]->cd.ppc.spr[SPR_XER] = *valuep; |
|
|
else |
|
|
*valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_XER]; |
|
|
*match_register = 1; |
|
|
} else if (strcasecmp(name, "fpscr") == 0) { |
|
|
if (writeflag) |
|
|
m->cpus[cpunr]->cd.ppc.fpscr = *valuep; |
|
|
else |
|
|
*valuep = m->cpus[cpunr]->cd.ppc.fpscr; |
|
|
*match_register = 1; |
|
|
} else if (name[0] == 'f' && isdigit((int)name[1])) { |
|
|
int nr = atoi(name + 1); |
|
|
if (nr >= 0 && nr < PPC_NFPRS) { |
|
|
if (writeflag) { |
|
|
m->cpus[cpunr]->cd.ppc.fpr[nr] = *valuep; |
|
|
} else |
|
|
*valuep = m->cpus[cpunr]->cd.ppc.fpr[nr]; |
|
|
*match_register = 1; |
|
|
} |
|
|
} |
|
596 |
} |
} |
597 |
|
|
598 |
|
|
599 |
/* |
/* |
600 |
* ppc_cpu_interrupt(): |
* ppc_irq_interrupt_assert(): |
|
* |
|
|
* 0..31 are used as BeBox interrupt numbers, 32..47 = ISA, |
|
|
* 64 is used as a "re-assert" signal to cpu->machine->md_interrupt(). |
|
|
* |
|
|
* TODO: don't hardcode to BeBox! |
|
601 |
*/ |
*/ |
602 |
int ppc_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr) |
void ppc_irq_interrupt_assert(struct interrupt *interrupt) |
603 |
{ |
{ |
604 |
/* fatal("ppc_cpu_interrupt(): 0x%x\n", (int)irq_nr); */ |
struct cpu *cpu = (struct cpu *) interrupt->extra; |
605 |
if (irq_nr <= 64) { |
cpu->cd.ppc.irq_asserted = 1; |
|
if (cpu->machine->md_interrupt != NULL) |
|
|
cpu->machine->md_interrupt( |
|
|
cpu->machine, cpu, irq_nr, 1); |
|
|
else |
|
|
fatal("ppc_cpu_interrupt(): md_interrupt == NULL\n"); |
|
|
} else { |
|
|
/* Assert PPC IRQ: */ |
|
|
cpu->cd.ppc.irq_asserted = 1; |
|
|
} |
|
|
return 1; |
|
606 |
} |
} |
607 |
|
|
608 |
|
|
609 |
/* |
/* |
610 |
* ppc_cpu_interrupt_ack(): |
* ppc_irq_interrupt_deassert(): |
611 |
*/ |
*/ |
612 |
int ppc_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr) |
void ppc_irq_interrupt_deassert(struct interrupt *interrupt) |
613 |
{ |
{ |
614 |
if (irq_nr <= 64) { |
struct cpu *cpu = (struct cpu *) interrupt->extra; |
615 |
if (cpu->machine->md_interrupt != NULL) |
cpu->cd.ppc.irq_asserted = 0; |
|
cpu->machine->md_interrupt(cpu->machine, |
|
|
cpu, irq_nr, 0); |
|
|
} else { |
|
|
/* De-assert PPC IRQ: */ |
|
|
cpu->cd.ppc.irq_asserted = 0; |
|
|
} |
|
|
return 1; |
|
616 |
} |
} |
617 |
|
|
618 |
|
|
629 |
* cpu->pc for relative addresses. |
* cpu->pc for relative addresses. |
630 |
*/ |
*/ |
631 |
int ppc_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr, |
int ppc_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr, |
632 |
int running, uint64_t dumpaddr, int bintrans) |
int running, uint64_t dumpaddr) |
633 |
{ |
{ |
634 |
int hi6, xo, lev, rt, rs, ra, rb, imm, sh, me, rc, l_bit, oe_bit; |
int hi6, xo, lev, rt, rs, ra, rb, imm, sh, me, rc, l_bit, oe_bit; |
635 |
int spr, aa_bit, lk_bit, bf, bh, bi, bo, mb, nb, bt, ba, bb, fpreg; |
int spr, aa_bit, lk_bit, bf, bh, bi, bo, mb, nb, bt, ba, bb, fpreg; |
923 |
case PPC_HI6_30: |
case PPC_HI6_30: |
924 |
xo = (iword >> 2) & 7; |
xo = (iword >> 2) & 7; |
925 |
switch (xo) { |
switch (xo) { |
926 |
|
case PPC_30_RLDICL: |
927 |
case PPC_30_RLDICR: |
case PPC_30_RLDICR: |
928 |
|
case PPC_30_RLDIMI: /* mb, not me */ |
929 |
|
mnem = NULL; |
930 |
|
switch (xo) { |
931 |
|
case PPC_30_RLDICL: mnem = "rldicl"; break; |
932 |
|
case PPC_30_RLDICR: mnem = "rldicr"; break; |
933 |
|
case PPC_30_RLDIMI: mnem = "rldimi"; break; |
934 |
|
} |
935 |
rs = (iword >> 21) & 31; |
rs = (iword >> 21) & 31; |
936 |
ra = (iword >> 16) & 31; |
ra = (iword >> 16) & 31; |
937 |
sh = ((iword >> 11) & 31) | ((iword & 2) << 4); |
sh = ((iword >> 11) & 31) | ((iword & 2) << 4); |
938 |
me = ((iword >> 6) & 31) | (iword & 0x20); |
me = ((iword >> 6) & 31) | (iword & 0x20); |
939 |
rc = iword & 1; |
rc = iword & 1; |
940 |
debug("rldicr%s\tr%i,r%i,%i,%i", |
debug("%s%s\tr%i,r%i,%i,%i", |
941 |
rc?".":"", ra, rs, sh, me); |
mnem, rc?".":"", ra, rs, sh, me); |
942 |
break; |
break; |
943 |
default: |
default: |
944 |
debug("unimplemented hi6_30, xo = 0x%x", xo); |
debug("unimplemented hi6_30, xo = 0x%x", xo); |
1105 |
case PPC_31_WRTEEI: |
case PPC_31_WRTEEI: |
1106 |
debug("wrteei\t%i", iword & 0x8000? 1 : 0); |
debug("wrteei\t%i", iword & 0x8000? 1 : 0); |
1107 |
break; |
break; |
1108 |
|
case PPC_31_MTMSRD: |
1109 |
|
/* TODO: Just a guess based on MTMSR */ |
1110 |
|
rs = (iword >> 21) & 31; |
1111 |
|
l_bit = (iword >> 16) & 1; |
1112 |
|
debug("mtmsrd\tr%i", rs); |
1113 |
|
if (l_bit) |
1114 |
|
debug(",%i", l_bit); |
1115 |
|
break; |
1116 |
case PPC_31_ADDZE: |
case PPC_31_ADDZE: |
1117 |
case PPC_31_ADDZEO: |
case PPC_31_ADDZEO: |
1118 |
rt = (iword >> 21) & 31; |
rt = (iword >> 21) & 31; |
1333 |
debug("%s\tr%i,r%i", mnem, ra, rb); |
debug("%s\tr%i,r%i", mnem, ra, rb); |
1334 |
break; |
break; |
1335 |
case PPC_31_SLW: |
case PPC_31_SLW: |
1336 |
|
case PPC_31_SLD: |
1337 |
case PPC_31_SRAW: |
case PPC_31_SRAW: |
1338 |
case PPC_31_SRW: |
case PPC_31_SRW: |
1339 |
case PPC_31_AND: |
case PPC_31_AND: |
1340 |
case PPC_31_ANDC: |
case PPC_31_ANDC: |
1341 |
case PPC_31_NOR: |
case PPC_31_NOR: |
1342 |
|
case PPC_31_EQV: |
1343 |
case PPC_31_OR: |
case PPC_31_OR: |
1344 |
case PPC_31_ORC: |
case PPC_31_ORC: |
1345 |
case PPC_31_XOR: |
case PPC_31_XOR: |
1354 |
switch (xo) { |
switch (xo) { |
1355 |
case PPC_31_SLW: mnem = |
case PPC_31_SLW: mnem = |
1356 |
power? "sl" : "slw"; break; |
power? "sl" : "slw"; break; |
1357 |
|
case PPC_31_SLD: mnem = "sld"; break; |
1358 |
case PPC_31_SRAW: mnem = |
case PPC_31_SRAW: mnem = |
1359 |
power? "sra" : "sraw"; break; |
power? "sra" : "sraw"; break; |
1360 |
case PPC_31_SRW: mnem = |
case PPC_31_SRW: mnem = |
1363 |
case PPC_31_NAND: mnem = "nand"; break; |
case PPC_31_NAND: mnem = "nand"; break; |
1364 |
case PPC_31_ANDC: mnem = "andc"; break; |
case PPC_31_ANDC: mnem = "andc"; break; |
1365 |
case PPC_31_NOR: mnem = "nor"; break; |
case PPC_31_NOR: mnem = "nor"; break; |
1366 |
|
case PPC_31_EQV: mnem = "eqv"; break; |
1367 |
case PPC_31_OR: mnem = "or"; break; |
case PPC_31_OR: mnem = "or"; break; |
1368 |
case PPC_31_ORC: mnem = "orc"; break; |
case PPC_31_ORC: mnem = "orc"; break; |
1369 |
case PPC_31_XOR: mnem = "xor"; break; |
case PPC_31_XOR: mnem = "xor"; break; |
1448 |
debug("%s%s\tr%i,r%i,%i", mnem, |
debug("%s%s\tr%i,r%i,%i", mnem, |
1449 |
rc? "." : "", ra, rs, sh); |
rc? "." : "", ra, rs, sh); |
1450 |
break; |
break; |
1451 |
|
case PPC_31_DSSALL: |
1452 |
|
debug("dssall"); |
1453 |
|
break; |
1454 |
case PPC_31_EIEIO: |
case PPC_31_EIEIO: |
1455 |
debug("%s", power? "eieio?" : "eieio"); |
debug("%s", power? "eieio?" : "eieio"); |
1456 |
break; |
break; |
1473 |
} |
} |
1474 |
debug("%s%s\tr%i,r%i", mnem, rc? "." : "", ra, rs); |
debug("%s%s\tr%i,r%i", mnem, rc? "." : "", ra, rs); |
1475 |
break; |
break; |
|
case 359: |
|
|
debug("TODO: ALTIVEC 359"); |
|
|
break; |
|
1476 |
case PPC_31_LVX: |
case PPC_31_LVX: |
1477 |
debug("lvx\tTODO: ALTIVEC"); |
case PPC_31_LVXL: |
|
break; |
|
1478 |
case PPC_31_STVX: |
case PPC_31_STVX: |
|
debug("stvx\tTODO: ALTIVEC"); |
|
|
break; |
|
1479 |
case PPC_31_STVXL: |
case PPC_31_STVXL: |
1480 |
debug("stvxl\tTODO: ALTIVEC"); |
rs = (iword >> 21) & 31; /* vs for stores, */ |
1481 |
|
ra = (iword >> 16) & 31; /* rs=vl for loads */ |
1482 |
|
rb = (iword >> 11) & 31; |
1483 |
|
rc = iword & 1; |
1484 |
|
switch (xo) { |
1485 |
|
case PPC_31_LVX: mnem = "lvx"; break; |
1486 |
|
case PPC_31_LVXL: mnem = "lvxl"; break; |
1487 |
|
case PPC_31_STVX: mnem = "stvx"; break; |
1488 |
|
case PPC_31_STVXL: mnem = "stvxl"; break; |
1489 |
|
} |
1490 |
|
debug("%s%s\tv%i,r%i,r%i", mnem, rc? "." : "", |
1491 |
|
rs, ra, rb); |
1492 |
break; |
break; |
1493 |
default: |
default: |
1494 |
debug("unimplemented hi6_31, xo = 0x%x", xo); |
debug("unimplemented hi6_31, xo = 0x%x", xo); |
1861 |
|
|
1862 |
#include "tmp_ppc_tail.c" |
#include "tmp_ppc_tail.c" |
1863 |
|
|
1864 |
|
|