1 |
/* |
/* |
2 |
* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
3 |
* |
* |
4 |
* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
5 |
* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: cpu_ppc.c,v 1.45 2006/01/24 21:26:01 debug Exp $ |
* $Id: cpu_ppc.c,v 1.68 2007/03/26 02:01:36 debug Exp $ |
29 |
* |
* |
30 |
* PowerPC/POWER CPU emulation. |
* PowerPC/POWER CPU emulation. |
31 |
*/ |
*/ |
37 |
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38 |
#include "cpu.h" |
#include "cpu.h" |
39 |
#include "devices.h" |
#include "devices.h" |
40 |
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#include "interrupt.h" |
41 |
#include "machine.h" |
#include "machine.h" |
42 |
#include "memory.h" |
#include "memory.h" |
43 |
#include "misc.h" |
#include "misc.h" |
47 |
#include "ppc_pte.h" |
#include "ppc_pte.h" |
48 |
#include "ppc_spr.h" |
#include "ppc_spr.h" |
49 |
#include "ppc_spr_strings.h" |
#include "ppc_spr_strings.h" |
50 |
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#include "settings.h" |
51 |
#include "symbol.h" |
#include "symbol.h" |
52 |
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53 |
#define DYNTRANS_DUALMODE_32 |
#define DYNTRANS_DUALMODE_32 |
57 |
void ppc_pc_to_pointers(struct cpu *); |
void ppc_pc_to_pointers(struct cpu *); |
58 |
void ppc32_pc_to_pointers(struct cpu *); |
void ppc32_pc_to_pointers(struct cpu *); |
59 |
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60 |
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void ppc_irq_interrupt_assert(struct interrupt *interrupt); |
61 |
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void ppc_irq_interrupt_deassert(struct interrupt *interrupt); |
62 |
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63 |
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64 |
/* |
/* |
65 |
* ppc_cpu_new(): |
* ppc_cpu_new(): |
91 |
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|
92 |
cpu->memory_rw = ppc_memory_rw; |
cpu->memory_rw = ppc_memory_rw; |
93 |
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94 |
cpu->cd.ppc.cpu_type = cpu_type_defs[found]; |
cpu->cd.ppc.cpu_type = cpu_type_defs[found]; |
95 |
cpu->name = cpu->cd.ppc.cpu_type.name; |
cpu->name = cpu->cd.ppc.cpu_type.name; |
96 |
cpu->byte_order = EMUL_BIG_ENDIAN; |
cpu->byte_order = EMUL_BIG_ENDIAN; |
97 |
cpu->cd.ppc.mode = MODE_PPC; /* TODO */ |
cpu->cd.ppc.mode = MODE_PPC; /* TODO */ |
98 |
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|
99 |
/* Current operating mode: */ |
/* Current operating mode: */ |
100 |
cpu->cd.ppc.bits = cpu->cd.ppc.cpu_type.bits; |
cpu->cd.ppc.bits = cpu->cd.ppc.cpu_type.bits; |
101 |
cpu->cd.ppc.spr[SPR_PVR] = cpu->cd.ppc.cpu_type.pvr; |
cpu->cd.ppc.spr[SPR_PVR] = cpu->cd.ppc.cpu_type.pvr; |
102 |
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103 |
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/* cpu->cd.ppc.msr = PPC_MSR_IR | PPC_MSR_DR | |
104 |
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PPC_MSR_SF | PPC_MSR_FP; */ |
105 |
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106 |
cpu->cd.ppc.spr[SPR_IBAT0U] = 0x00001ffc | BAT_Vs; |
cpu->cd.ppc.spr[SPR_IBAT0U] = 0x00001ffc | BAT_Vs; |
107 |
cpu->cd.ppc.spr[SPR_IBAT0L] = 0x00000000 | BAT_PP_RW; |
cpu->cd.ppc.spr[SPR_IBAT0L] = 0x00000000 | BAT_PP_RW; |
108 |
cpu->cd.ppc.spr[SPR_IBAT1U] = 0xc0001ffc | BAT_Vs; |
cpu->cd.ppc.spr[SPR_IBAT1U] = 0xc0001ffc | BAT_Vs; |
121 |
cpu->is_32bit = (cpu->cd.ppc.bits == 32)? 1 : 0; |
cpu->is_32bit = (cpu->cd.ppc.bits == 32)? 1 : 0; |
122 |
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|
123 |
if (cpu->is_32bit) { |
if (cpu->is_32bit) { |
124 |
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cpu->run_instr = ppc32_run_instr; |
125 |
cpu->update_translation_table = ppc32_update_translation_table; |
cpu->update_translation_table = ppc32_update_translation_table; |
126 |
cpu->invalidate_translation_caches = |
cpu->invalidate_translation_caches = |
127 |
ppc32_invalidate_translation_caches; |
ppc32_invalidate_translation_caches; |
128 |
cpu->invalidate_code_translation = |
cpu->invalidate_code_translation = |
129 |
ppc32_invalidate_code_translation; |
ppc32_invalidate_code_translation; |
130 |
} else { |
} else { |
131 |
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cpu->run_instr = ppc_run_instr; |
132 |
cpu->update_translation_table = ppc_update_translation_table; |
cpu->update_translation_table = ppc_update_translation_table; |
133 |
cpu->invalidate_translation_caches = |
cpu->invalidate_translation_caches = |
134 |
ppc_invalidate_translation_caches; |
ppc_invalidate_translation_caches; |
136 |
ppc_invalidate_code_translation; |
ppc_invalidate_code_translation; |
137 |
} |
} |
138 |
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139 |
cpu->translate_address = ppc_translate_address; |
cpu->translate_v2p = ppc_translate_v2p; |
140 |
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141 |
/* Only show name and caches etc for CPU nr 0 (in SMP machines): */ |
/* Only show name and caches etc for CPU nr 0 (in SMP machines): */ |
142 |
if (cpu_id == 0) { |
if (cpu_id == 0) { |
173 |
if (cpu->machine->prom_emulation) |
if (cpu->machine->prom_emulation) |
174 |
cpu->cd.ppc.of_emul_addr = 0xfff00000; |
cpu->cd.ppc.of_emul_addr = 0xfff00000; |
175 |
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176 |
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/* Add all register names to the settings: */ |
177 |
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CPU_SETTINGS_ADD_REGISTER64("pc", cpu->pc); |
178 |
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CPU_SETTINGS_ADD_REGISTER64("msr", cpu->cd.ppc.msr); |
179 |
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CPU_SETTINGS_ADD_REGISTER64("ctr", cpu->cd.ppc.spr[SPR_CTR]); |
180 |
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CPU_SETTINGS_ADD_REGISTER64("xer", cpu->cd.ppc.spr[SPR_XER]); |
181 |
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CPU_SETTINGS_ADD_REGISTER64("dec", cpu->cd.ppc.spr[SPR_DEC]); |
182 |
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CPU_SETTINGS_ADD_REGISTER64("hdec", cpu->cd.ppc.spr[SPR_HDEC]); |
183 |
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CPU_SETTINGS_ADD_REGISTER64("srr0", cpu->cd.ppc.spr[SPR_SRR0]); |
184 |
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CPU_SETTINGS_ADD_REGISTER64("srr1", cpu->cd.ppc.spr[SPR_SRR1]); |
185 |
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CPU_SETTINGS_ADD_REGISTER64("sdr1", cpu->cd.ppc.spr[SPR_SDR1]); |
186 |
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CPU_SETTINGS_ADD_REGISTER64("ibat0u", cpu->cd.ppc.spr[SPR_IBAT0U]); |
187 |
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CPU_SETTINGS_ADD_REGISTER64("ibat0l", cpu->cd.ppc.spr[SPR_IBAT0L]); |
188 |
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CPU_SETTINGS_ADD_REGISTER64("ibat1u", cpu->cd.ppc.spr[SPR_IBAT1U]); |
189 |
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CPU_SETTINGS_ADD_REGISTER64("ibat1l", cpu->cd.ppc.spr[SPR_IBAT1L]); |
190 |
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CPU_SETTINGS_ADD_REGISTER64("ibat2u", cpu->cd.ppc.spr[SPR_IBAT2U]); |
191 |
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CPU_SETTINGS_ADD_REGISTER64("ibat2l", cpu->cd.ppc.spr[SPR_IBAT2L]); |
192 |
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CPU_SETTINGS_ADD_REGISTER64("ibat3u", cpu->cd.ppc.spr[SPR_IBAT3U]); |
193 |
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CPU_SETTINGS_ADD_REGISTER64("ibat3l", cpu->cd.ppc.spr[SPR_IBAT3L]); |
194 |
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CPU_SETTINGS_ADD_REGISTER64("dbat0u", cpu->cd.ppc.spr[SPR_DBAT0U]); |
195 |
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CPU_SETTINGS_ADD_REGISTER64("dbat0l", cpu->cd.ppc.spr[SPR_DBAT0L]); |
196 |
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CPU_SETTINGS_ADD_REGISTER64("dbat1u", cpu->cd.ppc.spr[SPR_DBAT1U]); |
197 |
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CPU_SETTINGS_ADD_REGISTER64("dbat1l", cpu->cd.ppc.spr[SPR_DBAT1L]); |
198 |
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CPU_SETTINGS_ADD_REGISTER64("dbat2u", cpu->cd.ppc.spr[SPR_DBAT2U]); |
199 |
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CPU_SETTINGS_ADD_REGISTER64("dbat2l", cpu->cd.ppc.spr[SPR_DBAT2L]); |
200 |
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CPU_SETTINGS_ADD_REGISTER64("dbat3u", cpu->cd.ppc.spr[SPR_DBAT3U]); |
201 |
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CPU_SETTINGS_ADD_REGISTER64("dbat3l", cpu->cd.ppc.spr[SPR_DBAT3L]); |
202 |
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CPU_SETTINGS_ADD_REGISTER64("lr", cpu->cd.ppc.spr[SPR_LR]); |
203 |
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CPU_SETTINGS_ADD_REGISTER32("cr", cpu->cd.ppc.cr); |
204 |
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CPU_SETTINGS_ADD_REGISTER32("fpscr", cpu->cd.ppc.fpscr); |
205 |
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/* Integer GPRs, floating point registers, and segment registers: */ |
206 |
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for (i=0; i<PPC_NGPRS; i++) { |
207 |
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char tmpstr[5]; |
208 |
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snprintf(tmpstr, sizeof(tmpstr), "r%i", i); |
209 |
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CPU_SETTINGS_ADD_REGISTER64(tmpstr, cpu->cd.ppc.gpr[i]); |
210 |
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} |
211 |
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for (i=0; i<PPC_NFPRS; i++) { |
212 |
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char tmpstr[5]; |
213 |
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snprintf(tmpstr, sizeof(tmpstr), "f%i", i); |
214 |
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CPU_SETTINGS_ADD_REGISTER64(tmpstr, cpu->cd.ppc.fpr[i]); |
215 |
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} |
216 |
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for (i=0; i<16; i++) { |
217 |
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char tmpstr[5]; |
218 |
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snprintf(tmpstr, sizeof(tmpstr), "sr%i", i); |
219 |
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CPU_SETTINGS_ADD_REGISTER32(tmpstr, cpu->cd.ppc.sr[i]); |
220 |
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} |
221 |
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222 |
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/* Register the CPU as an interrupt handler: */ |
223 |
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{ |
224 |
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struct interrupt template; |
225 |
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char name[150]; |
226 |
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snprintf(name, sizeof(name), "%s", cpu->path); |
227 |
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memset(&template, 0, sizeof(template)); |
228 |
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template.line = 0; |
229 |
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template.name = name; |
230 |
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template.extra = cpu; |
231 |
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template.interrupt_assert = ppc_irq_interrupt_assert; |
232 |
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template.interrupt_deassert = ppc_irq_interrupt_deassert; |
233 |
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interrupt_handler_register(&template); |
234 |
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} |
235 |
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236 |
return 1; |
return 1; |
237 |
} |
} |
238 |
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337 |
*valuep = cpu->cd.ppc.msr; |
*valuep = cpu->cd.ppc.msr; |
338 |
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|
339 |
if (check_for_interrupts && cpu->cd.ppc.msr & PPC_MSR_EE) { |
if (check_for_interrupts && cpu->cd.ppc.msr & PPC_MSR_EE) { |
340 |
if (cpu->cd.ppc.dec_intr_pending) { |
if (cpu->cd.ppc.dec_intr_pending && |
341 |
|
!(cpu->cd.ppc.cpu_type.flags & PPC_NO_DEC)) { |
342 |
ppc_exception(cpu, PPC_EXCEPTION_DEC); |
ppc_exception(cpu, PPC_EXCEPTION_DEC); |
343 |
cpu->cd.ppc.dec_intr_pending = 0; |
cpu->cd.ppc.dec_intr_pending = 0; |
344 |
} else if (cpu->cd.ppc.irq_asserted) |
} else if (cpu->cd.ppc.irq_asserted) |
362 |
cpu->cd.ppc.spr[SPR_SRR1] = (cpu->cd.ppc.msr & 0x87c0ffff); |
cpu->cd.ppc.spr[SPR_SRR1] = (cpu->cd.ppc.msr & 0x87c0ffff); |
363 |
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364 |
if (!quiet_mode) |
if (!quiet_mode) |
365 |
fatal("[ PPC Exception 0x%x; pc=0x%llx ]\n", exception_nr, |
fatal("[ PPC Exception 0x%x; pc=0x%"PRIx64" ]\n", exception_nr, |
366 |
(long long)cpu->pc); |
(long long)cpu->pc); |
367 |
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368 |
/* Disable External Interrupts, Recoverable Interrupt Mode, |
/* Disable External Interrupts, Recoverable Interrupt Mode, |
402 |
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403 |
debug("cpu%i: pc = 0x", x); |
debug("cpu%i: pc = 0x", x); |
404 |
if (bits32) |
if (bits32) |
405 |
debug("%08x", (int)cpu->pc); |
debug("%08"PRIx32, (uint32_t)cpu->pc); |
406 |
else |
else |
407 |
debug("%016llx", (long long)cpu->pc); |
debug("%016"PRIx64, (uint64_t)cpu->pc); |
408 |
debug(" <%s>\n", symbol != NULL? symbol : " no symbol "); |
debug(" <%s>\n", symbol != NULL? symbol : " no symbol "); |
409 |
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|
410 |
debug("cpu%i: lr = 0x", x); |
debug("cpu%i: lr = 0x", x); |
411 |
if (bits32) |
if (bits32) |
412 |
debug("%08x", (int)cpu->cd.ppc.spr[SPR_LR]); |
debug("%08"PRIx32, (uint32_t)cpu->cd.ppc.spr[SPR_LR]); |
413 |
else |
else |
414 |
debug("%016llx", (long long)cpu->cd.ppc.spr[SPR_LR]); |
debug("%016"PRIx64, (uint64_t)cpu->cd.ppc.spr[SPR_LR]); |
415 |
debug(" cr = 0x%08x", (int)cpu->cd.ppc.cr); |
debug(" cr = 0x%08"PRIx32, (uint32_t)cpu->cd.ppc.cr); |
416 |
|
|
417 |
if (bits32) |
if (bits32) |
418 |
debug(" "); |
debug(" "); |
420 |
debug("\ncpu%i: ", x); |
debug("\ncpu%i: ", x); |
421 |
debug("ctr = 0x", x); |
debug("ctr = 0x", x); |
422 |
if (bits32) |
if (bits32) |
423 |
debug("%08x", (int)cpu->cd.ppc.spr[SPR_CTR]); |
debug("%08"PRIx32, (uint32_t)cpu->cd.ppc.spr[SPR_CTR]); |
424 |
else |
else |
425 |
debug("%016llx", (long long)cpu->cd.ppc.spr[SPR_CTR]); |
debug("%016"PRIx64, (uint64_t)cpu->cd.ppc.spr[SPR_CTR]); |
426 |
|
|
427 |
debug(" xer = 0x", x); |
debug(" xer = 0x", x); |
428 |
if (bits32) |
if (bits32) |
429 |
debug("%08x\n", (int)cpu->cd.ppc.spr[SPR_XER]); |
debug("%08"PRIx32, (uint32_t)cpu->cd.ppc.spr[SPR_XER]); |
430 |
else |
else |
431 |
debug("%016llx\n", (long long)cpu->cd.ppc.spr[SPR_XER]); |
debug("%016"PRIx64, (uint64_t)cpu->cd.ppc.spr[SPR_XER]); |
432 |
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433 |
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debug("\n"); |
434 |
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435 |
if (bits32) { |
if (bits32) { |
436 |
/* 32-bit: */ |
/* 32-bit: */ |
545 |
for (i=0; i<16; i++) { |
for (i=0; i<16; i++) { |
546 |
uint32_t s = cpu->cd.ppc.sr[i]; |
uint32_t s = cpu->cd.ppc.sr[i]; |
547 |
debug("cpu%i:", x); |
debug("cpu%i:", x); |
548 |
debug(" sr%2i = 0x%08x", i, (int)s); |
debug(" sr%-2i = 0x%08x", i, (int)s); |
549 |
s &= (SR_TYPE | SR_SUKEY | SR_PRKEY | SR_NOEXEC); |
s &= (SR_TYPE | SR_SUKEY | SR_PRKEY | SR_NOEXEC); |
550 |
if (s != 0) { |
if (s != 0) { |
551 |
debug(" ("); |
debug(" ("); |
578 |
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579 |
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580 |
/* |
/* |
581 |
* ppc_cpu_register_match(): |
* ppc_cpu_tlbdump(): |
582 |
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* |
583 |
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* Not currently used for PPC. |
584 |
*/ |
*/ |
585 |
void ppc_cpu_register_match(struct machine *m, char *name, |
void ppc_cpu_tlbdump(struct machine *m, int x, int rawflag) |
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int writeflag, uint64_t *valuep, int *match_register) |
|
586 |
{ |
{ |
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int cpunr = 0; |
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/* CPU number: */ |
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/* TODO */ |
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/* Register name: */ |
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if (strcasecmp(name, "pc") == 0) { |
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if (writeflag) { |
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m->cpus[cpunr]->pc = *valuep; |
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} else |
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*valuep = m->cpus[cpunr]->pc; |
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*match_register = 1; |
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} else if (strcasecmp(name, "msr") == 0) { |
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if (writeflag) |
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m->cpus[cpunr]->cd.ppc.msr = *valuep; |
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else |
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*valuep = m->cpus[cpunr]->cd.ppc.msr; |
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*match_register = 1; |
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} else if (strcasecmp(name, "lr") == 0) { |
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if (writeflag) |
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m->cpus[cpunr]->cd.ppc.spr[SPR_LR] = *valuep; |
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else |
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*valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_LR]; |
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*match_register = 1; |
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} else if (strcasecmp(name, "cr") == 0) { |
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if (writeflag) |
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m->cpus[cpunr]->cd.ppc.cr = *valuep; |
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else |
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*valuep = m->cpus[cpunr]->cd.ppc.cr; |
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*match_register = 1; |
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} else if (strcasecmp(name, "dec") == 0) { |
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if (writeflag) |
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m->cpus[cpunr]->cd.ppc.spr[SPR_DEC] = *valuep; |
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else |
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*valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_DEC]; |
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*match_register = 1; |
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} else if (strcasecmp(name, "hdec") == 0) { |
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if (writeflag) |
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m->cpus[cpunr]->cd.ppc.spr[SPR_HDEC] = *valuep; |
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else |
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*valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_HDEC]; |
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*match_register = 1; |
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} else if (strcasecmp(name, "ctr") == 0) { |
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if (writeflag) |
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m->cpus[cpunr]->cd.ppc.spr[SPR_CTR] = *valuep; |
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else |
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*valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_CTR]; |
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*match_register = 1; |
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} else if (name[0] == 'r' && isdigit((int)name[1])) { |
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int nr = atoi(name + 1); |
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if (nr >= 0 && nr < PPC_NGPRS) { |
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if (writeflag) { |
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m->cpus[cpunr]->cd.ppc.gpr[nr] = *valuep; |
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} else |
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*valuep = m->cpus[cpunr]->cd.ppc.gpr[nr]; |
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*match_register = 1; |
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} |
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} else if (strcasecmp(name, "xer") == 0) { |
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if (writeflag) |
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m->cpus[cpunr]->cd.ppc.spr[SPR_XER] = *valuep; |
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else |
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*valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_XER]; |
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*match_register = 1; |
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} else if (strcasecmp(name, "fpscr") == 0) { |
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if (writeflag) |
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m->cpus[cpunr]->cd.ppc.fpscr = *valuep; |
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else |
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*valuep = m->cpus[cpunr]->cd.ppc.fpscr; |
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*match_register = 1; |
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} else if (name[0] == 'f' && isdigit((int)name[1])) { |
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int nr = atoi(name + 1); |
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if (nr >= 0 && nr < PPC_NFPRS) { |
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if (writeflag) { |
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m->cpus[cpunr]->cd.ppc.fpr[nr] = *valuep; |
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} else |
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*valuep = m->cpus[cpunr]->cd.ppc.fpr[nr]; |
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*match_register = 1; |
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} |
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} |
|
587 |
} |
} |
588 |
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589 |
|
|
590 |
/* |
/* |
591 |
* ppc_cpu_interrupt(): |
* ppc_irq_interrupt_assert(): |
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* |
|
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* 0..31 are used as BeBox interrupt numbers, 32..47 = ISA, |
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* 64 is used as a "re-assert" signal to cpu->machine->md_interrupt(). |
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* |
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* TODO: don't hardcode to BeBox! |
|
592 |
*/ |
*/ |
593 |
int ppc_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr) |
void ppc_irq_interrupt_assert(struct interrupt *interrupt) |
594 |
{ |
{ |
595 |
/* fatal("ppc_cpu_interrupt(): 0x%x\n", (int)irq_nr); */ |
struct cpu *cpu = (struct cpu *) interrupt->extra; |
596 |
if (irq_nr <= 64) { |
cpu->cd.ppc.irq_asserted = 1; |
|
if (cpu->machine->md_interrupt != NULL) |
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cpu->machine->md_interrupt( |
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cpu->machine, cpu, irq_nr, 1); |
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else |
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fatal("ppc_cpu_interrupt(): md_interrupt == NULL\n"); |
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} else { |
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/* Assert PPC IRQ: */ |
|
|
cpu->cd.ppc.irq_asserted = 1; |
|
|
} |
|
|
return 1; |
|
597 |
} |
} |
598 |
|
|
599 |
|
|
600 |
/* |
/* |
601 |
* ppc_cpu_interrupt_ack(): |
* ppc_irq_interrupt_deassert(): |
602 |
*/ |
*/ |
603 |
int ppc_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr) |
void ppc_irq_interrupt_deassert(struct interrupt *interrupt) |
604 |
{ |
{ |
605 |
if (irq_nr <= 64) { |
struct cpu *cpu = (struct cpu *) interrupt->extra; |
606 |
if (cpu->machine->md_interrupt != NULL) |
cpu->cd.ppc.irq_asserted = 0; |
|
cpu->machine->md_interrupt(cpu->machine, |
|
|
cpu, irq_nr, 0); |
|
|
} else { |
|
|
/* De-assert PPC IRQ: */ |
|
|
cpu->cd.ppc.irq_asserted = 0; |
|
|
} |
|
|
return 1; |
|
607 |
} |
} |
608 |
|
|
609 |
|
|
620 |
* cpu->pc for relative addresses. |
* cpu->pc for relative addresses. |
621 |
*/ |
*/ |
622 |
int ppc_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr, |
int ppc_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr, |
623 |
int running, uint64_t dumpaddr, int bintrans) |
int running, uint64_t dumpaddr) |
624 |
{ |
{ |
625 |
int hi6, xo, lev, rt, rs, ra, rb, imm, sh, me, rc, l_bit, oe_bit; |
int hi6, xo, lev, rt, rs, ra, rb, imm, sh, me, rc, l_bit, oe_bit; |
626 |
int spr, aa_bit, lk_bit, bf, bh, bi, bo, mb, nb, bt, ba, bb, fpreg; |
int spr, aa_bit, lk_bit, bf, bh, bi, bo, mb, nb, bt, ba, bb, fpreg; |
914 |
case PPC_HI6_30: |
case PPC_HI6_30: |
915 |
xo = (iword >> 2) & 7; |
xo = (iword >> 2) & 7; |
916 |
switch (xo) { |
switch (xo) { |
917 |
|
case PPC_30_RLDICL: |
918 |
case PPC_30_RLDICR: |
case PPC_30_RLDICR: |
919 |
|
case PPC_30_RLDIMI: /* mb, not me */ |
920 |
|
mnem = NULL; |
921 |
|
switch (xo) { |
922 |
|
case PPC_30_RLDICL: mnem = "rldicl"; break; |
923 |
|
case PPC_30_RLDICR: mnem = "rldicr"; break; |
924 |
|
case PPC_30_RLDIMI: mnem = "rldimi"; break; |
925 |
|
} |
926 |
rs = (iword >> 21) & 31; |
rs = (iword >> 21) & 31; |
927 |
ra = (iword >> 16) & 31; |
ra = (iword >> 16) & 31; |
928 |
sh = ((iword >> 11) & 31) | ((iword & 2) << 4); |
sh = ((iword >> 11) & 31) | ((iword & 2) << 4); |
929 |
me = ((iword >> 6) & 31) | (iword & 0x20); |
me = ((iword >> 6) & 31) | (iword & 0x20); |
930 |
rc = iword & 1; |
rc = iword & 1; |
931 |
debug("rldicr%s\tr%i,r%i,%i,%i", |
debug("%s%s\tr%i,r%i,%i,%i", |
932 |
rc?".":"", ra, rs, sh, me); |
mnem, rc?".":"", ra, rs, sh, me); |
933 |
break; |
break; |
934 |
default: |
default: |
935 |
debug("unimplemented hi6_30, xo = 0x%x", xo); |
debug("unimplemented hi6_30, xo = 0x%x", xo); |
1096 |
case PPC_31_WRTEEI: |
case PPC_31_WRTEEI: |
1097 |
debug("wrteei\t%i", iword & 0x8000? 1 : 0); |
debug("wrteei\t%i", iword & 0x8000? 1 : 0); |
1098 |
break; |
break; |
1099 |
|
case PPC_31_MTMSRD: |
1100 |
|
/* TODO: Just a guess based on MTMSR */ |
1101 |
|
rs = (iword >> 21) & 31; |
1102 |
|
l_bit = (iword >> 16) & 1; |
1103 |
|
debug("mtmsrd\tr%i", rs); |
1104 |
|
if (l_bit) |
1105 |
|
debug(",%i", l_bit); |
1106 |
|
break; |
1107 |
case PPC_31_ADDZE: |
case PPC_31_ADDZE: |
1108 |
case PPC_31_ADDZEO: |
case PPC_31_ADDZEO: |
1109 |
rt = (iword >> 21) & 31; |
rt = (iword >> 21) & 31; |
1324 |
debug("%s\tr%i,r%i", mnem, ra, rb); |
debug("%s\tr%i,r%i", mnem, ra, rb); |
1325 |
break; |
break; |
1326 |
case PPC_31_SLW: |
case PPC_31_SLW: |
1327 |
|
case PPC_31_SLD: |
1328 |
case PPC_31_SRAW: |
case PPC_31_SRAW: |
1329 |
case PPC_31_SRW: |
case PPC_31_SRW: |
1330 |
case PPC_31_AND: |
case PPC_31_AND: |
1331 |
case PPC_31_ANDC: |
case PPC_31_ANDC: |
1332 |
case PPC_31_NOR: |
case PPC_31_NOR: |
1333 |
|
case PPC_31_EQV: |
1334 |
case PPC_31_OR: |
case PPC_31_OR: |
1335 |
case PPC_31_ORC: |
case PPC_31_ORC: |
1336 |
case PPC_31_XOR: |
case PPC_31_XOR: |
1345 |
switch (xo) { |
switch (xo) { |
1346 |
case PPC_31_SLW: mnem = |
case PPC_31_SLW: mnem = |
1347 |
power? "sl" : "slw"; break; |
power? "sl" : "slw"; break; |
1348 |
|
case PPC_31_SLD: mnem = "sld"; break; |
1349 |
case PPC_31_SRAW: mnem = |
case PPC_31_SRAW: mnem = |
1350 |
power? "sra" : "sraw"; break; |
power? "sra" : "sraw"; break; |
1351 |
case PPC_31_SRW: mnem = |
case PPC_31_SRW: mnem = |
1354 |
case PPC_31_NAND: mnem = "nand"; break; |
case PPC_31_NAND: mnem = "nand"; break; |
1355 |
case PPC_31_ANDC: mnem = "andc"; break; |
case PPC_31_ANDC: mnem = "andc"; break; |
1356 |
case PPC_31_NOR: mnem = "nor"; break; |
case PPC_31_NOR: mnem = "nor"; break; |
1357 |
|
case PPC_31_EQV: mnem = "eqv"; break; |
1358 |
case PPC_31_OR: mnem = "or"; break; |
case PPC_31_OR: mnem = "or"; break; |
1359 |
case PPC_31_ORC: mnem = "orc"; break; |
case PPC_31_ORC: mnem = "orc"; break; |
1360 |
case PPC_31_XOR: mnem = "xor"; break; |
case PPC_31_XOR: mnem = "xor"; break; |
1439 |
debug("%s%s\tr%i,r%i,%i", mnem, |
debug("%s%s\tr%i,r%i,%i", mnem, |
1440 |
rc? "." : "", ra, rs, sh); |
rc? "." : "", ra, rs, sh); |
1441 |
break; |
break; |
1442 |
|
case PPC_31_DSSALL: |
1443 |
|
debug("dssall"); |
1444 |
|
break; |
1445 |
case PPC_31_EIEIO: |
case PPC_31_EIEIO: |
1446 |
debug("%s", power? "eieio?" : "eieio"); |
debug("%s", power? "eieio?" : "eieio"); |
1447 |
break; |
break; |
1464 |
} |
} |
1465 |
debug("%s%s\tr%i,r%i", mnem, rc? "." : "", ra, rs); |
debug("%s%s\tr%i,r%i", mnem, rc? "." : "", ra, rs); |
1466 |
break; |
break; |
|
case 359: |
|
|
debug("TODO: ALTIVEC 359"); |
|
|
break; |
|
1467 |
case PPC_31_LVX: |
case PPC_31_LVX: |
1468 |
debug("lvx\tTODO: ALTIVEC"); |
case PPC_31_LVXL: |
|
break; |
|
1469 |
case PPC_31_STVX: |
case PPC_31_STVX: |
|
debug("stvx\tTODO: ALTIVEC"); |
|
|
break; |
|
1470 |
case PPC_31_STVXL: |
case PPC_31_STVXL: |
1471 |
debug("stvxl\tTODO: ALTIVEC"); |
rs = (iword >> 21) & 31; /* vs for stores, */ |
1472 |
|
ra = (iword >> 16) & 31; /* rs=vl for loads */ |
1473 |
|
rb = (iword >> 11) & 31; |
1474 |
|
rc = iword & 1; |
1475 |
|
switch (xo) { |
1476 |
|
case PPC_31_LVX: mnem = "lvx"; break; |
1477 |
|
case PPC_31_LVXL: mnem = "lvxl"; break; |
1478 |
|
case PPC_31_STVX: mnem = "stvx"; break; |
1479 |
|
case PPC_31_STVXL: mnem = "stvxl"; break; |
1480 |
|
} |
1481 |
|
debug("%s%s\tv%i,r%i,r%i", mnem, rc? "." : "", |
1482 |
|
rs, ra, rb); |
1483 |
break; |
break; |
1484 |
default: |
default: |
1485 |
debug("unimplemented hi6_31, xo = 0x%x", xo); |
debug("unimplemented hi6_31, xo = 0x%x", xo); |
1852 |
|
|
1853 |
#include "tmp_ppc_tail.c" |
#include "tmp_ppc_tail.c" |
1854 |
|
|
1855 |
|
|