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/* |
/* |
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* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: cpu_ppc.c,v 1.45 2006/01/24 21:26:01 debug Exp $ |
* $Id: cpu_ppc.c,v 1.72 2007/06/28 13:36:46 debug Exp $ |
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* |
* |
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* PowerPC/POWER CPU emulation. |
* PowerPC/POWER CPU emulation. |
31 |
*/ |
*/ |
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#include "cpu.h" |
#include "cpu.h" |
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#include "devices.h" |
#include "devices.h" |
40 |
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#include "interrupt.h" |
41 |
#include "machine.h" |
#include "machine.h" |
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#include "memory.h" |
#include "memory.h" |
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#include "misc.h" |
#include "misc.h" |
47 |
#include "ppc_pte.h" |
#include "ppc_pte.h" |
48 |
#include "ppc_spr.h" |
#include "ppc_spr.h" |
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#include "ppc_spr_strings.h" |
#include "ppc_spr_strings.h" |
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#include "settings.h" |
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#include "symbol.h" |
#include "symbol.h" |
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#include "useremul.h" |
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#define DYNTRANS_DUALMODE_32 |
#define DYNTRANS_DUALMODE_32 |
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#include "tmp_ppc_head.c" |
#include "tmp_ppc_head.c" |
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void ppc_pc_to_pointers(struct cpu *); |
void ppc_pc_to_pointers(struct cpu *); |
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void ppc32_pc_to_pointers(struct cpu *); |
void ppc32_pc_to_pointers(struct cpu *); |
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void ppc_irq_interrupt_assert(struct interrupt *interrupt); |
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void ppc_irq_interrupt_deassert(struct interrupt *interrupt); |
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/* |
/* |
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* ppc_cpu_new(): |
* ppc_cpu_new(): |
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|
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cpu->memory_rw = ppc_memory_rw; |
cpu->memory_rw = ppc_memory_rw; |
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|
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cpu->cd.ppc.cpu_type = cpu_type_defs[found]; |
cpu->cd.ppc.cpu_type = cpu_type_defs[found]; |
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cpu->name = cpu->cd.ppc.cpu_type.name; |
cpu->name = cpu->cd.ppc.cpu_type.name; |
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cpu->byte_order = EMUL_BIG_ENDIAN; |
cpu->byte_order = EMUL_BIG_ENDIAN; |
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cpu->cd.ppc.mode = MODE_PPC; /* TODO */ |
cpu->cd.ppc.mode = MODE_PPC; /* TODO */ |
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|
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/* Current operating mode: */ |
/* Current operating mode: */ |
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cpu->cd.ppc.bits = cpu->cd.ppc.cpu_type.bits; |
cpu->cd.ppc.bits = cpu->cd.ppc.cpu_type.bits; |
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cpu->cd.ppc.spr[SPR_PVR] = cpu->cd.ppc.cpu_type.pvr; |
cpu->cd.ppc.spr[SPR_PVR] = cpu->cd.ppc.cpu_type.pvr; |
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/* cpu->cd.ppc.msr = PPC_MSR_IR | PPC_MSR_DR | |
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PPC_MSR_SF | PPC_MSR_FP; */ |
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cpu->cd.ppc.spr[SPR_IBAT0U] = 0x00001ffc | BAT_Vs; |
cpu->cd.ppc.spr[SPR_IBAT0U] = 0x00001ffc | BAT_Vs; |
109 |
cpu->cd.ppc.spr[SPR_IBAT0L] = 0x00000000 | BAT_PP_RW; |
cpu->cd.ppc.spr[SPR_IBAT0L] = 0x00000000 | BAT_PP_RW; |
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cpu->cd.ppc.spr[SPR_IBAT1U] = 0xc0001ffc | BAT_Vs; |
cpu->cd.ppc.spr[SPR_IBAT1U] = 0xc0001ffc | BAT_Vs; |
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cpu->is_32bit = (cpu->cd.ppc.bits == 32)? 1 : 0; |
cpu->is_32bit = (cpu->cd.ppc.bits == 32)? 1 : 0; |
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|
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if (cpu->is_32bit) { |
if (cpu->is_32bit) { |
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cpu->run_instr = ppc32_run_instr; |
127 |
cpu->update_translation_table = ppc32_update_translation_table; |
cpu->update_translation_table = ppc32_update_translation_table; |
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cpu->invalidate_translation_caches = |
cpu->invalidate_translation_caches = |
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ppc32_invalidate_translation_caches; |
ppc32_invalidate_translation_caches; |
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cpu->invalidate_code_translation = |
cpu->invalidate_code_translation = |
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ppc32_invalidate_code_translation; |
ppc32_invalidate_code_translation; |
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} else { |
} else { |
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cpu->run_instr = ppc_run_instr; |
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cpu->update_translation_table = ppc_update_translation_table; |
cpu->update_translation_table = ppc_update_translation_table; |
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cpu->invalidate_translation_caches = |
cpu->invalidate_translation_caches = |
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ppc_invalidate_translation_caches; |
ppc_invalidate_translation_caches; |
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ppc_invalidate_code_translation; |
ppc_invalidate_code_translation; |
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} |
} |
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cpu->translate_address = ppc_translate_address; |
cpu->translate_v2p = ppc_translate_v2p; |
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/* Only show name and caches etc for CPU nr 0 (in SMP machines): */ |
/* Only show name and caches etc for CPU nr 0 (in SMP machines): */ |
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if (cpu_id == 0) { |
if (cpu_id == 0) { |
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if (cpu->machine->prom_emulation) |
if (cpu->machine->prom_emulation) |
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cpu->cd.ppc.of_emul_addr = 0xfff00000; |
cpu->cd.ppc.of_emul_addr = 0xfff00000; |
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/* Add all register names to the settings: */ |
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CPU_SETTINGS_ADD_REGISTER64("pc", cpu->pc); |
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CPU_SETTINGS_ADD_REGISTER64("msr", cpu->cd.ppc.msr); |
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CPU_SETTINGS_ADD_REGISTER64("ctr", cpu->cd.ppc.spr[SPR_CTR]); |
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CPU_SETTINGS_ADD_REGISTER64("xer", cpu->cd.ppc.spr[SPR_XER]); |
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CPU_SETTINGS_ADD_REGISTER64("dec", cpu->cd.ppc.spr[SPR_DEC]); |
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CPU_SETTINGS_ADD_REGISTER64("hdec", cpu->cd.ppc.spr[SPR_HDEC]); |
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CPU_SETTINGS_ADD_REGISTER64("srr0", cpu->cd.ppc.spr[SPR_SRR0]); |
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CPU_SETTINGS_ADD_REGISTER64("srr1", cpu->cd.ppc.spr[SPR_SRR1]); |
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CPU_SETTINGS_ADD_REGISTER64("sdr1", cpu->cd.ppc.spr[SPR_SDR1]); |
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CPU_SETTINGS_ADD_REGISTER64("ibat0u", cpu->cd.ppc.spr[SPR_IBAT0U]); |
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CPU_SETTINGS_ADD_REGISTER64("ibat0l", cpu->cd.ppc.spr[SPR_IBAT0L]); |
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CPU_SETTINGS_ADD_REGISTER64("ibat1u", cpu->cd.ppc.spr[SPR_IBAT1U]); |
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CPU_SETTINGS_ADD_REGISTER64("ibat1l", cpu->cd.ppc.spr[SPR_IBAT1L]); |
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CPU_SETTINGS_ADD_REGISTER64("ibat2u", cpu->cd.ppc.spr[SPR_IBAT2U]); |
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CPU_SETTINGS_ADD_REGISTER64("ibat2l", cpu->cd.ppc.spr[SPR_IBAT2L]); |
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CPU_SETTINGS_ADD_REGISTER64("ibat3u", cpu->cd.ppc.spr[SPR_IBAT3U]); |
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CPU_SETTINGS_ADD_REGISTER64("ibat3l", cpu->cd.ppc.spr[SPR_IBAT3L]); |
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CPU_SETTINGS_ADD_REGISTER64("dbat0u", cpu->cd.ppc.spr[SPR_DBAT0U]); |
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CPU_SETTINGS_ADD_REGISTER64("dbat0l", cpu->cd.ppc.spr[SPR_DBAT0L]); |
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CPU_SETTINGS_ADD_REGISTER64("dbat1u", cpu->cd.ppc.spr[SPR_DBAT1U]); |
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CPU_SETTINGS_ADD_REGISTER64("dbat1l", cpu->cd.ppc.spr[SPR_DBAT1L]); |
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CPU_SETTINGS_ADD_REGISTER64("dbat2u", cpu->cd.ppc.spr[SPR_DBAT2U]); |
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CPU_SETTINGS_ADD_REGISTER64("dbat2l", cpu->cd.ppc.spr[SPR_DBAT2L]); |
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CPU_SETTINGS_ADD_REGISTER64("dbat3u", cpu->cd.ppc.spr[SPR_DBAT3U]); |
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CPU_SETTINGS_ADD_REGISTER64("dbat3l", cpu->cd.ppc.spr[SPR_DBAT3L]); |
204 |
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CPU_SETTINGS_ADD_REGISTER64("lr", cpu->cd.ppc.spr[SPR_LR]); |
205 |
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CPU_SETTINGS_ADD_REGISTER32("cr", cpu->cd.ppc.cr); |
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CPU_SETTINGS_ADD_REGISTER32("fpscr", cpu->cd.ppc.fpscr); |
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/* Integer GPRs, floating point registers, and segment registers: */ |
208 |
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for (i=0; i<PPC_NGPRS; i++) { |
209 |
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char tmpstr[5]; |
210 |
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snprintf(tmpstr, sizeof(tmpstr), "r%i", i); |
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CPU_SETTINGS_ADD_REGISTER64(tmpstr, cpu->cd.ppc.gpr[i]); |
212 |
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} |
213 |
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for (i=0; i<PPC_NFPRS; i++) { |
214 |
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char tmpstr[5]; |
215 |
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snprintf(tmpstr, sizeof(tmpstr), "f%i", i); |
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CPU_SETTINGS_ADD_REGISTER64(tmpstr, cpu->cd.ppc.fpr[i]); |
217 |
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} |
218 |
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for (i=0; i<16; i++) { |
219 |
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char tmpstr[5]; |
220 |
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snprintf(tmpstr, sizeof(tmpstr), "sr%i", i); |
221 |
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CPU_SETTINGS_ADD_REGISTER32(tmpstr, cpu->cd.ppc.sr[i]); |
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} |
223 |
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/* Register the CPU as an interrupt handler: */ |
225 |
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{ |
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struct interrupt template; |
227 |
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char name[150]; |
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snprintf(name, sizeof(name), "%s", cpu->path); |
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memset(&template, 0, sizeof(template)); |
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template.line = 0; |
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template.name = name; |
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template.extra = cpu; |
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template.interrupt_assert = ppc_irq_interrupt_assert; |
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template.interrupt_deassert = ppc_irq_interrupt_deassert; |
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interrupt_handler_register(&template); |
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} |
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return 1; |
return 1; |
239 |
} |
} |
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|
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*valuep = cpu->cd.ppc.msr; |
*valuep = cpu->cd.ppc.msr; |
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|
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if (check_for_interrupts && cpu->cd.ppc.msr & PPC_MSR_EE) { |
if (check_for_interrupts && cpu->cd.ppc.msr & PPC_MSR_EE) { |
342 |
if (cpu->cd.ppc.dec_intr_pending) { |
if (cpu->cd.ppc.dec_intr_pending && |
343 |
|
!(cpu->cd.ppc.cpu_type.flags & PPC_NO_DEC)) { |
344 |
ppc_exception(cpu, PPC_EXCEPTION_DEC); |
ppc_exception(cpu, PPC_EXCEPTION_DEC); |
345 |
cpu->cd.ppc.dec_intr_pending = 0; |
cpu->cd.ppc.dec_intr_pending = 0; |
346 |
} else if (cpu->cd.ppc.irq_asserted) |
} else if (cpu->cd.ppc.irq_asserted) |
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cpu->cd.ppc.spr[SPR_SRR1] = (cpu->cd.ppc.msr & 0x87c0ffff); |
cpu->cd.ppc.spr[SPR_SRR1] = (cpu->cd.ppc.msr & 0x87c0ffff); |
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|
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if (!quiet_mode) |
if (!quiet_mode) |
367 |
fatal("[ PPC Exception 0x%x; pc=0x%llx ]\n", exception_nr, |
fatal("[ PPC Exception 0x%x; pc=0x%"PRIx64" ]\n", |
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(long long)cpu->pc); |
exception_nr, cpu->pc); |
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|
|
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/* Disable External Interrupts, Recoverable Interrupt Mode, |
/* Disable External Interrupts, Recoverable Interrupt Mode, |
371 |
and go to Supervisor mode */ |
and go to Supervisor mode */ |
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|
|
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debug("cpu%i: pc = 0x", x); |
debug("cpu%i: pc = 0x", x); |
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if (bits32) |
if (bits32) |
407 |
debug("%08x", (int)cpu->pc); |
debug("%08"PRIx32, (uint32_t)cpu->pc); |
408 |
else |
else |
409 |
debug("%016llx", (long long)cpu->pc); |
debug("%016"PRIx64, (uint64_t)cpu->pc); |
410 |
debug(" <%s>\n", symbol != NULL? symbol : " no symbol "); |
debug(" <%s>\n", symbol != NULL? symbol : " no symbol "); |
411 |
|
|
412 |
debug("cpu%i: lr = 0x", x); |
debug("cpu%i: lr = 0x", x); |
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if (bits32) |
if (bits32) |
414 |
debug("%08x", (int)cpu->cd.ppc.spr[SPR_LR]); |
debug("%08"PRIx32, (uint32_t)cpu->cd.ppc.spr[SPR_LR]); |
415 |
else |
else |
416 |
debug("%016llx", (long long)cpu->cd.ppc.spr[SPR_LR]); |
debug("%016"PRIx64, (uint64_t)cpu->cd.ppc.spr[SPR_LR]); |
417 |
debug(" cr = 0x%08x", (int)cpu->cd.ppc.cr); |
debug(" cr = 0x%08"PRIx32, (uint32_t)cpu->cd.ppc.cr); |
418 |
|
|
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if (bits32) |
if (bits32) |
420 |
debug(" "); |
debug(" "); |
422 |
debug("\ncpu%i: ", x); |
debug("\ncpu%i: ", x); |
423 |
debug("ctr = 0x", x); |
debug("ctr = 0x", x); |
424 |
if (bits32) |
if (bits32) |
425 |
debug("%08x", (int)cpu->cd.ppc.spr[SPR_CTR]); |
debug("%08"PRIx32, (uint32_t)cpu->cd.ppc.spr[SPR_CTR]); |
426 |
else |
else |
427 |
debug("%016llx", (long long)cpu->cd.ppc.spr[SPR_CTR]); |
debug("%016"PRIx64, (uint64_t)cpu->cd.ppc.spr[SPR_CTR]); |
428 |
|
|
429 |
debug(" xer = 0x", x); |
debug(" xer = 0x", x); |
430 |
if (bits32) |
if (bits32) |
431 |
debug("%08x\n", (int)cpu->cd.ppc.spr[SPR_XER]); |
debug("%08"PRIx32, (uint32_t)cpu->cd.ppc.spr[SPR_XER]); |
432 |
else |
else |
433 |
debug("%016llx\n", (long long)cpu->cd.ppc.spr[SPR_XER]); |
debug("%016"PRIx64, (uint64_t)cpu->cd.ppc.spr[SPR_XER]); |
434 |
|
|
435 |
|
debug("\n"); |
436 |
|
|
437 |
if (bits32) { |
if (bits32) { |
438 |
/* 32-bit: */ |
/* 32-bit: */ |
439 |
for (i=0; i<PPC_NGPRS; i++) { |
for (i=0; i<PPC_NGPRS; i++) { |
440 |
if ((i % 4) == 0) |
if ((i % 4) == 0) |
441 |
debug("cpu%i:", x); |
debug("cpu%i:", x); |
442 |
debug(" r%02i = 0x%08x ", i, |
debug(" r%02i = 0x%08"PRIx32" ", i, |
443 |
(int)cpu->cd.ppc.gpr[i]); |
(uint32_t) cpu->cd.ppc.gpr[i]); |
444 |
if ((i % 4) == 3) |
if ((i % 4) == 3) |
445 |
debug("\n"); |
debug("\n"); |
446 |
} |
} |
450 |
int r = (i >> 1) + ((i & 1) << 4); |
int r = (i >> 1) + ((i & 1) << 4); |
451 |
if ((i % 2) == 0) |
if ((i % 2) == 0) |
452 |
debug("cpu%i:", x); |
debug("cpu%i:", x); |
453 |
debug(" r%02i = 0x%016llx ", r, |
debug(" r%02i = 0x%016"PRIx64" ", r, |
454 |
(long long)cpu->cd.ppc.gpr[r]); |
(uint64_t) cpu->cd.ppc.gpr[r]); |
455 |
if ((i % 2) == 1) |
if ((i % 2) == 1) |
456 |
debug("\n"); |
debug("\n"); |
457 |
} |
} |
459 |
|
|
460 |
/* Other special registers: */ |
/* Other special registers: */ |
461 |
if (bits32) { |
if (bits32) { |
462 |
debug("cpu%i: srr0 = 0x%08x srr1 = 0x%08x\n", x, |
debug("cpu%i: srr0 = 0x%08"PRIx32 |
463 |
(int)cpu->cd.ppc.spr[SPR_SRR0], |
" srr1 = 0x%08"PRIx32"\n", x, |
464 |
(int)cpu->cd.ppc.spr[SPR_SRR1]); |
(uint32_t) cpu->cd.ppc.spr[SPR_SRR0], |
465 |
|
(uint32_t) cpu->cd.ppc.spr[SPR_SRR1]); |
466 |
} else { |
} else { |
467 |
debug("cpu%i: srr0 = 0x%016llx srr1 = 0x%016llx\n", x, |
debug("cpu%i: srr0 = 0x%016"PRIx64 |
468 |
(long long)cpu->cd.ppc.spr[SPR_SRR0], |
" srr1 = 0x%016"PRIx64"\n", x, |
469 |
(long long)cpu->cd.ppc.spr[SPR_SRR1]); |
(uint64_t) cpu->cd.ppc.spr[SPR_SRR0], |
470 |
|
(uint64_t) cpu->cd.ppc.spr[SPR_SRR1]); |
471 |
} |
} |
472 |
|
|
473 |
debug("cpu%i: msr = ", x); |
debug("cpu%i: msr = ", x); |
474 |
reg_access_msr(cpu, &tmp, 0, 0); |
reg_access_msr(cpu, &tmp, 0, 0); |
475 |
if (bits32) |
if (bits32) |
476 |
debug("0x%08x ", (int)tmp); |
debug("0x%08"PRIx32, (uint32_t) tmp); |
477 |
else |
else |
478 |
debug("0x%016llx ", (long long)tmp); |
debug("0x%016"PRIx64, (uint64_t) tmp); |
479 |
debug("tb = 0x%08x%08x\n", (int)cpu->cd.ppc.spr[SPR_TBU], |
|
480 |
(int)cpu->cd.ppc.spr[SPR_TBL]); |
debug(" tb = 0x%08"PRIx32"%08"PRIx32"\n", |
481 |
debug("cpu%i: dec = 0x%08x", x, (int)cpu->cd.ppc.spr[SPR_DEC]); |
(uint32_t) cpu->cd.ppc.spr[SPR_TBU], |
482 |
|
(uint32_t) cpu->cd.ppc.spr[SPR_TBL]); |
483 |
|
|
484 |
|
debug("cpu%i: dec = 0x%08"PRIx32, |
485 |
|
x, (uint32_t) cpu->cd.ppc.spr[SPR_DEC]); |
486 |
if (!bits32) |
if (!bits32) |
487 |
debug(" hdec = 0x%08x\n", |
debug(" hdec = 0x%08"PRIx32"\n", |
488 |
(int)cpu->cd.ppc.spr[SPR_HDEC]); |
(uint32_t) cpu->cd.ppc.spr[SPR_HDEC]); |
489 |
|
|
490 |
debug("\n"); |
debug("\n"); |
491 |
} |
} |
492 |
|
|
493 |
if (coprocs & 1) { |
if (coprocs & 1) { |
494 |
debug("cpu%i: fpscr = 0x%08x\n", x, (int)cpu->cd.ppc.fpscr); |
debug("cpu%i: fpscr = 0x%08"PRIx32"\n", |
495 |
|
x, (uint32_t) cpu->cd.ppc.fpscr); |
496 |
|
|
497 |
/* TODO: show floating-point values :-) */ |
/* TODO: show floating-point values :-) */ |
498 |
|
|
501 |
for (i=0; i<PPC_NFPRS; i++) { |
for (i=0; i<PPC_NFPRS; i++) { |
502 |
if ((i % 2) == 0) |
if ((i % 2) == 0) |
503 |
debug("cpu%i:", x); |
debug("cpu%i:", x); |
504 |
debug(" f%02i = 0x%016llx ", i, |
debug(" f%02i = 0x%016"PRIx64" ", i, |
505 |
(long long)cpu->cd.ppc.fpr[i]); |
(uint64_t) cpu->cd.ppc.fpr[i]); |
506 |
if ((i % 2) == 1) |
if ((i % 2) == 1) |
507 |
debug("\n"); |
debug("\n"); |
508 |
} |
} |
509 |
} |
} |
510 |
|
|
511 |
if (coprocs & 2) { |
if (coprocs & 2) { |
512 |
debug("cpu%i: sdr1 = 0x%llx\n", x, |
debug("cpu%i: sdr1 = 0x%"PRIx64"\n", x, |
513 |
(long long)cpu->cd.ppc.spr[SPR_SDR1]); |
(uint64_t) cpu->cd.ppc.spr[SPR_SDR1]); |
514 |
if (cpu->cd.ppc.cpu_type.flags & PPC_601) |
if (cpu->cd.ppc.cpu_type.flags & PPC_601) |
515 |
debug("cpu%i: PPC601-style, TODO!\n"); |
debug("cpu%i: PPC601-style, TODO!\n"); |
516 |
else { |
else { |
520 |
uint32_t lower = cpu->cd.ppc.spr[spr+1]; |
uint32_t lower = cpu->cd.ppc.spr[spr+1]; |
521 |
uint32_t len = (((upper & BAT_BL) << 15) |
uint32_t len = (((upper & BAT_BL) << 15) |
522 |
| 0x1ffff) + 1; |
| 0x1ffff) + 1; |
523 |
debug("cpu%i: %sbat%i: u=0x%08x l=0x%08x ", |
debug("cpu%i: %sbat%i: u=0x%08"PRIx32 |
524 |
|
" l=0x%08"PRIx32" ", |
525 |
x, i<4? "i" : "d", i&3, upper, lower); |
x, i<4? "i" : "d", i&3, upper, lower); |
526 |
if (!(upper & BAT_V)) { |
if (!(upper & BAT_V)) { |
527 |
debug(" (not valid)\n"); |
debug(" (not valid)\n"); |
556 |
if (coprocs & 4) { |
if (coprocs & 4) { |
557 |
for (i=0; i<16; i++) { |
for (i=0; i<16; i++) { |
558 |
uint32_t s = cpu->cd.ppc.sr[i]; |
uint32_t s = cpu->cd.ppc.sr[i]; |
559 |
|
|
560 |
debug("cpu%i:", x); |
debug("cpu%i:", x); |
561 |
debug(" sr%2i = 0x%08x", i, (int)s); |
debug(" sr%-2i = 0x%08"PRIx32, i, s); |
562 |
|
|
563 |
s &= (SR_TYPE | SR_SUKEY | SR_PRKEY | SR_NOEXEC); |
s &= (SR_TYPE | SR_SUKEY | SR_PRKEY | SR_NOEXEC); |
564 |
if (s != 0) { |
if (s != 0) { |
565 |
debug(" ("); |
debug(" ("); |
592 |
|
|
593 |
|
|
594 |
/* |
/* |
595 |
* ppc_cpu_register_match(): |
* ppc_cpu_tlbdump(): |
596 |
|
* |
597 |
|
* Not currently used for PPC. |
598 |
*/ |
*/ |
599 |
void ppc_cpu_register_match(struct machine *m, char *name, |
void ppc_cpu_tlbdump(struct machine *m, int x, int rawflag) |
|
int writeflag, uint64_t *valuep, int *match_register) |
|
600 |
{ |
{ |
|
int cpunr = 0; |
|
|
|
|
|
/* CPU number: */ |
|
|
|
|
|
/* TODO */ |
|
|
|
|
|
/* Register name: */ |
|
|
if (strcasecmp(name, "pc") == 0) { |
|
|
if (writeflag) { |
|
|
m->cpus[cpunr]->pc = *valuep; |
|
|
} else |
|
|
*valuep = m->cpus[cpunr]->pc; |
|
|
*match_register = 1; |
|
|
} else if (strcasecmp(name, "msr") == 0) { |
|
|
if (writeflag) |
|
|
m->cpus[cpunr]->cd.ppc.msr = *valuep; |
|
|
else |
|
|
*valuep = m->cpus[cpunr]->cd.ppc.msr; |
|
|
*match_register = 1; |
|
|
} else if (strcasecmp(name, "lr") == 0) { |
|
|
if (writeflag) |
|
|
m->cpus[cpunr]->cd.ppc.spr[SPR_LR] = *valuep; |
|
|
else |
|
|
*valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_LR]; |
|
|
*match_register = 1; |
|
|
} else if (strcasecmp(name, "cr") == 0) { |
|
|
if (writeflag) |
|
|
m->cpus[cpunr]->cd.ppc.cr = *valuep; |
|
|
else |
|
|
*valuep = m->cpus[cpunr]->cd.ppc.cr; |
|
|
*match_register = 1; |
|
|
} else if (strcasecmp(name, "dec") == 0) { |
|
|
if (writeflag) |
|
|
m->cpus[cpunr]->cd.ppc.spr[SPR_DEC] = *valuep; |
|
|
else |
|
|
*valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_DEC]; |
|
|
*match_register = 1; |
|
|
} else if (strcasecmp(name, "hdec") == 0) { |
|
|
if (writeflag) |
|
|
m->cpus[cpunr]->cd.ppc.spr[SPR_HDEC] = *valuep; |
|
|
else |
|
|
*valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_HDEC]; |
|
|
*match_register = 1; |
|
|
} else if (strcasecmp(name, "ctr") == 0) { |
|
|
if (writeflag) |
|
|
m->cpus[cpunr]->cd.ppc.spr[SPR_CTR] = *valuep; |
|
|
else |
|
|
*valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_CTR]; |
|
|
*match_register = 1; |
|
|
} else if (name[0] == 'r' && isdigit((int)name[1])) { |
|
|
int nr = atoi(name + 1); |
|
|
if (nr >= 0 && nr < PPC_NGPRS) { |
|
|
if (writeflag) { |
|
|
m->cpus[cpunr]->cd.ppc.gpr[nr] = *valuep; |
|
|
} else |
|
|
*valuep = m->cpus[cpunr]->cd.ppc.gpr[nr]; |
|
|
*match_register = 1; |
|
|
} |
|
|
} else if (strcasecmp(name, "xer") == 0) { |
|
|
if (writeflag) |
|
|
m->cpus[cpunr]->cd.ppc.spr[SPR_XER] = *valuep; |
|
|
else |
|
|
*valuep = m->cpus[cpunr]->cd.ppc.spr[SPR_XER]; |
|
|
*match_register = 1; |
|
|
} else if (strcasecmp(name, "fpscr") == 0) { |
|
|
if (writeflag) |
|
|
m->cpus[cpunr]->cd.ppc.fpscr = *valuep; |
|
|
else |
|
|
*valuep = m->cpus[cpunr]->cd.ppc.fpscr; |
|
|
*match_register = 1; |
|
|
} else if (name[0] == 'f' && isdigit((int)name[1])) { |
|
|
int nr = atoi(name + 1); |
|
|
if (nr >= 0 && nr < PPC_NFPRS) { |
|
|
if (writeflag) { |
|
|
m->cpus[cpunr]->cd.ppc.fpr[nr] = *valuep; |
|
|
} else |
|
|
*valuep = m->cpus[cpunr]->cd.ppc.fpr[nr]; |
|
|
*match_register = 1; |
|
|
} |
|
|
} |
|
601 |
} |
} |
602 |
|
|
603 |
|
|
604 |
/* |
/* |
605 |
* ppc_cpu_interrupt(): |
* ppc_irq_interrupt_assert(): |
|
* |
|
|
* 0..31 are used as BeBox interrupt numbers, 32..47 = ISA, |
|
|
* 64 is used as a "re-assert" signal to cpu->machine->md_interrupt(). |
|
|
* |
|
|
* TODO: don't hardcode to BeBox! |
|
606 |
*/ |
*/ |
607 |
int ppc_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr) |
void ppc_irq_interrupt_assert(struct interrupt *interrupt) |
608 |
{ |
{ |
609 |
/* fatal("ppc_cpu_interrupt(): 0x%x\n", (int)irq_nr); */ |
struct cpu *cpu = (struct cpu *) interrupt->extra; |
610 |
if (irq_nr <= 64) { |
cpu->cd.ppc.irq_asserted = 1; |
|
if (cpu->machine->md_interrupt != NULL) |
|
|
cpu->machine->md_interrupt( |
|
|
cpu->machine, cpu, irq_nr, 1); |
|
|
else |
|
|
fatal("ppc_cpu_interrupt(): md_interrupt == NULL\n"); |
|
|
} else { |
|
|
/* Assert PPC IRQ: */ |
|
|
cpu->cd.ppc.irq_asserted = 1; |
|
|
} |
|
|
return 1; |
|
611 |
} |
} |
612 |
|
|
613 |
|
|
614 |
/* |
/* |
615 |
* ppc_cpu_interrupt_ack(): |
* ppc_irq_interrupt_deassert(): |
616 |
*/ |
*/ |
617 |
int ppc_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr) |
void ppc_irq_interrupt_deassert(struct interrupt *interrupt) |
618 |
{ |
{ |
619 |
if (irq_nr <= 64) { |
struct cpu *cpu = (struct cpu *) interrupt->extra; |
620 |
if (cpu->machine->md_interrupt != NULL) |
cpu->cd.ppc.irq_asserted = 0; |
|
cpu->machine->md_interrupt(cpu->machine, |
|
|
cpu, irq_nr, 0); |
|
|
} else { |
|
|
/* De-assert PPC IRQ: */ |
|
|
cpu->cd.ppc.irq_asserted = 0; |
|
|
} |
|
|
return 1; |
|
621 |
} |
} |
622 |
|
|
623 |
|
|
634 |
* cpu->pc for relative addresses. |
* cpu->pc for relative addresses. |
635 |
*/ |
*/ |
636 |
int ppc_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr, |
int ppc_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr, |
637 |
int running, uint64_t dumpaddr, int bintrans) |
int running, uint64_t dumpaddr) |
638 |
{ |
{ |
639 |
int hi6, xo, lev, rt, rs, ra, rb, imm, sh, me, rc, l_bit, oe_bit; |
int hi6, xo, lev, rt, rs, ra, rb, imm, sh, me, rc, l_bit, oe_bit; |
640 |
int spr, aa_bit, lk_bit, bf, bh, bi, bo, mb, nb, bt, ba, bb, fpreg; |
int spr, aa_bit, lk_bit, bf, bh, bi, bo, mb, nb, bt, ba, bb, fpreg; |
656 |
debug("cpu%i: ", cpu->cpu_id); |
debug("cpu%i: ", cpu->cpu_id); |
657 |
|
|
658 |
if (cpu->cd.ppc.bits == 32) |
if (cpu->cd.ppc.bits == 32) |
659 |
debug("%08x", (int)dumpaddr); |
debug("%08"PRIx32, (uint32_t) dumpaddr); |
660 |
else |
else |
661 |
debug("%016llx", (long long)dumpaddr); |
debug("%016"PRIx64, (uint64_t) dumpaddr); |
662 |
|
|
663 |
/* NOTE: Fixed to big-endian. */ |
/* NOTE: Fixed to big-endian. */ |
664 |
iword = (instr[0] << 24) + (instr[1] << 16) + (instr[2] << 8) |
iword = (instr[0] << 24) + (instr[1] << 16) + (instr[2] << 8) |
665 |
+ instr[3]; |
+ instr[3]; |
666 |
|
|
667 |
debug(": %08x\t", iword); |
debug(": %08"PRIx32"\t", iword); |
668 |
|
|
669 |
/* |
/* |
670 |
* Decode the instruction: |
* Decode the instruction: |
765 |
if (cpu->cd.ppc.bits == 32) |
if (cpu->cd.ppc.bits == 32) |
766 |
addr &= 0xffffffff; |
addr &= 0xffffffff; |
767 |
if (cpu->cd.ppc.bits == 32) |
if (cpu->cd.ppc.bits == 32) |
768 |
debug("0x%x", (int)addr); |
debug("0x%"PRIx32, (uint32_t) addr); |
769 |
else |
else |
770 |
debug("0x%llx", (long long)addr); |
debug("0x%"PRIx64, (uint64_t) addr); |
771 |
symbol = get_symbol_name(&cpu->machine->symbol_context, |
symbol = get_symbol_name(&cpu->machine->symbol_context, |
772 |
addr, &offset); |
addr, &offset); |
773 |
if (symbol != NULL) |
if (symbol != NULL) |
798 |
if (cpu->cd.ppc.bits == 32) |
if (cpu->cd.ppc.bits == 32) |
799 |
addr &= 0xffffffff; |
addr &= 0xffffffff; |
800 |
if (cpu->cd.ppc.bits == 32) |
if (cpu->cd.ppc.bits == 32) |
801 |
debug("\t0x%x", (int)addr); |
debug("\t0x%"PRIx32, (uint32_t) addr); |
802 |
else |
else |
803 |
debug("\t0x%llx", (long long)addr); |
debug("\t0x%"PRIx64, (uint64_t) addr); |
804 |
symbol = get_symbol_name(&cpu->machine->symbol_context, |
symbol = get_symbol_name(&cpu->machine->symbol_context, |
805 |
addr, &offset); |
addr, &offset); |
806 |
if (symbol != NULL) |
if (symbol != NULL) |
928 |
case PPC_HI6_30: |
case PPC_HI6_30: |
929 |
xo = (iword >> 2) & 7; |
xo = (iword >> 2) & 7; |
930 |
switch (xo) { |
switch (xo) { |
931 |
|
case PPC_30_RLDICL: |
932 |
case PPC_30_RLDICR: |
case PPC_30_RLDICR: |
933 |
|
case PPC_30_RLDIMI: /* mb, not me */ |
934 |
|
mnem = NULL; |
935 |
|
switch (xo) { |
936 |
|
case PPC_30_RLDICL: mnem = "rldicl"; break; |
937 |
|
case PPC_30_RLDICR: mnem = "rldicr"; break; |
938 |
|
case PPC_30_RLDIMI: mnem = "rldimi"; break; |
939 |
|
} |
940 |
rs = (iword >> 21) & 31; |
rs = (iword >> 21) & 31; |
941 |
ra = (iword >> 16) & 31; |
ra = (iword >> 16) & 31; |
942 |
sh = ((iword >> 11) & 31) | ((iword & 2) << 4); |
sh = ((iword >> 11) & 31) | ((iword & 2) << 4); |
943 |
me = ((iword >> 6) & 31) | (iword & 0x20); |
me = ((iword >> 6) & 31) | (iword & 0x20); |
944 |
rc = iword & 1; |
rc = iword & 1; |
945 |
debug("rldicr%s\tr%i,r%i,%i,%i", |
debug("%s%s\tr%i,r%i,%i,%i", |
946 |
rc?".":"", ra, rs, sh, me); |
mnem, rc?".":"", ra, rs, sh, me); |
947 |
break; |
break; |
948 |
default: |
default: |
949 |
debug("unimplemented hi6_30, xo = 0x%x", xo); |
debug("unimplemented hi6_30, xo = 0x%x", xo); |
1089 |
if (symbol != NULL) |
if (symbol != NULL) |
1090 |
debug(" \t<%s", symbol); |
debug(" \t<%s", symbol); |
1091 |
else |
else |
1092 |
debug(" \t<0x%llx", (long long)addr); |
debug(" \t<0x%"PRIx64, (uint64_t) addr); |
1093 |
if (wlen > 0 && !fpreg /* && !reverse */) { |
if (wlen > 0 && !fpreg /* && !reverse */) { |
1094 |
/* TODO */ |
/* TODO */ |
1095 |
} |
} |
1110 |
case PPC_31_WRTEEI: |
case PPC_31_WRTEEI: |
1111 |
debug("wrteei\t%i", iword & 0x8000? 1 : 0); |
debug("wrteei\t%i", iword & 0x8000? 1 : 0); |
1112 |
break; |
break; |
1113 |
|
case PPC_31_MTMSRD: |
1114 |
|
/* TODO: Just a guess based on MTMSR */ |
1115 |
|
rs = (iword >> 21) & 31; |
1116 |
|
l_bit = (iword >> 16) & 1; |
1117 |
|
debug("mtmsrd\tr%i", rs); |
1118 |
|
if (l_bit) |
1119 |
|
debug(",%i", l_bit); |
1120 |
|
break; |
1121 |
case PPC_31_ADDZE: |
case PPC_31_ADDZE: |
1122 |
case PPC_31_ADDZEO: |
case PPC_31_ADDZEO: |
1123 |
rt = (iword >> 21) & 31; |
rt = (iword >> 21) & 31; |
1260 |
ppc_spr_names[spr]==NULL? "?" : ppc_spr_names[spr]); |
ppc_spr_names[spr]==NULL? "?" : ppc_spr_names[spr]); |
1261 |
if (running) { |
if (running) { |
1262 |
if (cpu->cd.ppc.bits == 32) |
if (cpu->cd.ppc.bits == 32) |
1263 |
debug(": 0x%x", (int) |
debug(": 0x%"PRIx32, (uint32_t) |
1264 |
cpu->cd.ppc.spr[spr]); |
cpu->cd.ppc.spr[spr]); |
1265 |
else |
else |
1266 |
debug(": 0x%llx", (long long) |
debug(": 0x%"PRIx64, (uint64_t) |
1267 |
cpu->cd.ppc.spr[spr]); |
cpu->cd.ppc.spr[spr]); |
1268 |
} |
} |
1269 |
debug(">"); |
debug(">"); |
1338 |
debug("%s\tr%i,r%i", mnem, ra, rb); |
debug("%s\tr%i,r%i", mnem, ra, rb); |
1339 |
break; |
break; |
1340 |
case PPC_31_SLW: |
case PPC_31_SLW: |
1341 |
|
case PPC_31_SLD: |
1342 |
case PPC_31_SRAW: |
case PPC_31_SRAW: |
1343 |
case PPC_31_SRW: |
case PPC_31_SRW: |
1344 |
case PPC_31_AND: |
case PPC_31_AND: |
1345 |
case PPC_31_ANDC: |
case PPC_31_ANDC: |
1346 |
case PPC_31_NOR: |
case PPC_31_NOR: |
1347 |
|
case PPC_31_EQV: |
1348 |
case PPC_31_OR: |
case PPC_31_OR: |
1349 |
case PPC_31_ORC: |
case PPC_31_ORC: |
1350 |
case PPC_31_XOR: |
case PPC_31_XOR: |
1359 |
switch (xo) { |
switch (xo) { |
1360 |
case PPC_31_SLW: mnem = |
case PPC_31_SLW: mnem = |
1361 |
power? "sl" : "slw"; break; |
power? "sl" : "slw"; break; |
1362 |
|
case PPC_31_SLD: mnem = "sld"; break; |
1363 |
case PPC_31_SRAW: mnem = |
case PPC_31_SRAW: mnem = |
1364 |
power? "sra" : "sraw"; break; |
power? "sra" : "sraw"; break; |
1365 |
case PPC_31_SRW: mnem = |
case PPC_31_SRW: mnem = |
1368 |
case PPC_31_NAND: mnem = "nand"; break; |
case PPC_31_NAND: mnem = "nand"; break; |
1369 |
case PPC_31_ANDC: mnem = "andc"; break; |
case PPC_31_ANDC: mnem = "andc"; break; |
1370 |
case PPC_31_NOR: mnem = "nor"; break; |
case PPC_31_NOR: mnem = "nor"; break; |
1371 |
|
case PPC_31_EQV: mnem = "eqv"; break; |
1372 |
case PPC_31_OR: mnem = "or"; break; |
case PPC_31_OR: mnem = "or"; break; |
1373 |
case PPC_31_ORC: mnem = "orc"; break; |
case PPC_31_ORC: mnem = "orc"; break; |
1374 |
case PPC_31_XOR: mnem = "xor"; break; |
case PPC_31_XOR: mnem = "xor"; break; |
1420 |
ppc_spr_names[spr]==NULL? "?" : ppc_spr_names[spr]); |
ppc_spr_names[spr]==NULL? "?" : ppc_spr_names[spr]); |
1421 |
if (running) { |
if (running) { |
1422 |
if (cpu->cd.ppc.bits == 32) |
if (cpu->cd.ppc.bits == 32) |
1423 |
debug(": 0x%x", (int) |
debug(": 0x%"PRIx32, (uint32_t) |
1424 |
cpu->cd.ppc.gpr[rs]); |
cpu->cd.ppc.gpr[rs]); |
1425 |
else |
else |
1426 |
debug(": 0x%llx", (long long) |
debug(": 0x%"PRIx64, (uint64_t) |
1427 |
cpu->cd.ppc.gpr[rs]); |
cpu->cd.ppc.gpr[rs]); |
1428 |
} |
} |
1429 |
debug(">"); |
debug(">"); |
1453 |
debug("%s%s\tr%i,r%i,%i", mnem, |
debug("%s%s\tr%i,r%i,%i", mnem, |
1454 |
rc? "." : "", ra, rs, sh); |
rc? "." : "", ra, rs, sh); |
1455 |
break; |
break; |
1456 |
|
case PPC_31_DSSALL: |
1457 |
|
debug("dssall"); |
1458 |
|
break; |
1459 |
case PPC_31_EIEIO: |
case PPC_31_EIEIO: |
1460 |
debug("%s", power? "eieio?" : "eieio"); |
debug("%s", power? "eieio?" : "eieio"); |
1461 |
break; |
break; |
1478 |
} |
} |
1479 |
debug("%s%s\tr%i,r%i", mnem, rc? "." : "", ra, rs); |
debug("%s%s\tr%i,r%i", mnem, rc? "." : "", ra, rs); |
1480 |
break; |
break; |
|
case 359: |
|
|
debug("TODO: ALTIVEC 359"); |
|
|
break; |
|
1481 |
case PPC_31_LVX: |
case PPC_31_LVX: |
1482 |
debug("lvx\tTODO: ALTIVEC"); |
case PPC_31_LVXL: |
|
break; |
|
1483 |
case PPC_31_STVX: |
case PPC_31_STVX: |
|
debug("stvx\tTODO: ALTIVEC"); |
|
|
break; |
|
1484 |
case PPC_31_STVXL: |
case PPC_31_STVXL: |
1485 |
debug("stvxl\tTODO: ALTIVEC"); |
rs = (iword >> 21) & 31; /* vs for stores, */ |
1486 |
|
ra = (iword >> 16) & 31; /* rs=vl for loads */ |
1487 |
|
rb = (iword >> 11) & 31; |
1488 |
|
rc = iword & 1; |
1489 |
|
switch (xo) { |
1490 |
|
case PPC_31_LVX: mnem = "lvx"; break; |
1491 |
|
case PPC_31_LVXL: mnem = "lvxl"; break; |
1492 |
|
case PPC_31_STVX: mnem = "stvx"; break; |
1493 |
|
case PPC_31_STVXL: mnem = "stvxl"; break; |
1494 |
|
} |
1495 |
|
debug("%s%s\tv%i,r%i,r%i", mnem, rc? "." : "", |
1496 |
|
rs, ra, rb); |
1497 |
break; |
break; |
1498 |
default: |
default: |
1499 |
debug("unimplemented hi6_31, xo = 0x%x", xo); |
debug("unimplemented hi6_31, xo = 0x%x", xo); |
1576 |
if (symbol != NULL) |
if (symbol != NULL) |
1577 |
debug(" \t<%s", symbol); |
debug(" \t<%s", symbol); |
1578 |
else |
else |
1579 |
debug(" \t<0x%llx", (long long)addr); |
debug(" \t<0x%"PRIx64, (uint64_t) addr); |
1580 |
if (wlen > 0 && load && wlen > 0) { |
if (wlen > 0 && load && wlen > 0) { |
1581 |
unsigned char tw[8]; |
unsigned char tw[8]; |
1582 |
uint64_t tdata = 0; |
uint64_t tdata = 0; |
1600 |
if (symbol != NULL) |
if (symbol != NULL) |
1601 |
debug("%s", symbol); |
debug("%s", symbol); |
1602 |
else |
else |
1603 |
debug("0x%llx", |
debug("0x%"PRIx64, |
1604 |
(long long)tdata); |
(uint64_t) tdata); |
1605 |
} else { |
} else { |
1606 |
/* TODO: if load==2, then this is |
/* TODO: if load==2, then this is |
1607 |
a _signed_ load. */ |
a _signed_ load. */ |
1608 |
debug("0x%llx", (long long)tdata); |
debug("0x%"PRIx64, (uint64_t) tdata); |
1609 |
} |
} |
1610 |
} else |
} else |
1611 |
debug(": unreadable"); |
debug(": unreadable"); |
1623 |
if (symbol != NULL) |
if (symbol != NULL) |
1624 |
debug("%s", symbol); |
debug("%s", symbol); |
1625 |
else |
else |
1626 |
debug("0x%llx", (long long)tdata); |
debug("0x%"PRIx64, (uint64_t) tdata); |
1627 |
} else { |
} else { |
1628 |
if (tdata > -256 && tdata < 256) |
if (tdata > -256 && tdata < 256) |
1629 |
debug("%i", (int)tdata); |
debug("%i", (int)tdata); |
1630 |
else |
else |
1631 |
debug("0x%llx", (long long)tdata); |
debug("0x%"PRIx64, (uint64_t) tdata); |
1632 |
} |
} |
1633 |
} |
} |
1634 |
debug(">"); |
debug(">"); |
1820 |
break; |
break; |
1821 |
} else |
} else |
1822 |
fatal("[ using UNIMPLEMENTED spr %i (%s), pc = " |
fatal("[ using UNIMPLEMENTED spr %i (%s), pc = " |
1823 |
"0x%llx ]\n", spr, ppc_spr_names[spr] == NULL? |
"0x%"PRIx64" ]\n", spr, ppc_spr_names[spr] == NULL? |
1824 |
"UNKNOWN" : ppc_spr_names[spr], (long long)pc); |
"UNKNOWN" : ppc_spr_names[spr], (uint64_t) pc); |
1825 |
} |
} |
1826 |
|
|
1827 |
spr_used[spr >> 2] |= (1 << (spr & 3)); |
spr_used[spr >> 2] |= (1 << (spr & 3)); |
1866 |
|
|
1867 |
#include "tmp_ppc_tail.c" |
#include "tmp_ppc_tail.c" |
1868 |
|
|
1869 |
|
|