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dpavlin |
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/* |
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* Copyright (C) 2005 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: cpu_newmips.c,v 1.2 2005/11/17 21:26:06 debug Exp $ |
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* |
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* MIPS CPU emulation. |
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* |
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* TODO |
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*/ |
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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#include <ctype.h> |
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#include "cpu.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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#include "symbol.h" |
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#define DYNTRANS_DUALMODE_32 |
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#include "tmp_newmips_head.c" |
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/* |
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* newmips_cpu_new(): |
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* |
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* Create a new NEWMIPS cpu object. |
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* |
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* Returns 1 on success, 0 if there was no matching NEWMIPS processor with |
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* this cpu_type_name. |
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*/ |
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int newmips_cpu_new(struct cpu *cpu, struct memory *mem, |
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struct machine *machine, int cpu_id, char *cpu_type_name) |
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{ |
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if (strcasecmp(cpu_type_name, "NEWMIPS") != 0) |
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return 0; |
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cpu->memory_rw = newmips_memory_rw; |
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/* TODO: per CPU type? */ |
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cpu->byte_order = EMUL_LITTLE_ENDIAN; |
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cpu->is_32bit = 1; |
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cpu->cd.newmips.bits = 32; |
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if (cpu->is_32bit) { |
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cpu->update_translation_table = |
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newmips32_update_translation_table; |
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cpu->invalidate_translation_caches = |
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newmips32_invalidate_translation_caches; |
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cpu->invalidate_code_translation = |
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newmips32_invalidate_code_translation; |
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} else { |
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cpu->update_translation_table = |
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newmips_update_translation_table; |
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cpu->invalidate_translation_caches = |
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newmips_invalidate_translation_caches; |
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cpu->invalidate_code_translation = |
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newmips_invalidate_code_translation; |
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} |
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/* Only show name and caches etc for CPU nr 0 (in SMP machines): */ |
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if (cpu_id == 0) { |
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debug("%s", cpu->name); |
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} |
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return 1; |
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} |
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/* |
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* newmips_cpu_list_available_types(): |
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* |
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* Print a list of available NEWMIPS CPU types. |
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*/ |
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void newmips_cpu_list_available_types(void) |
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{ |
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debug("NEWMIPS\n"); |
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/* TODO */ |
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} |
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/* |
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* newmips_cpu_dumpinfo(): |
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*/ |
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void newmips_cpu_dumpinfo(struct cpu *cpu) |
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{ |
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debug("\n"); |
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/* TODO */ |
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} |
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/* |
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* newmips_cpu_register_dump(): |
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* |
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* Dump cpu registers in a relatively readable format. |
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* |
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* gprs: set to non-zero to dump GPRs and some special-purpose registers. |
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* coprocs: set bit 0..3 to dump registers in coproc 0..3. |
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*/ |
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void newmips_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs) |
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{ |
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char *symbol; |
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uint64_t offset; |
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int i, x = cpu->cpu_id, nregs = 32; |
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int bits32 = cpu->cd.newmips.bits == 32; |
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if (gprs) { |
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/* Special registers (pc, ...) first: */ |
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symbol = get_symbol_name(&cpu->machine->symbol_context, |
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cpu->pc, &offset); |
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debug("cpu%i: pc = 0x", x); |
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if (bits32) |
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debug("%08x", (int)cpu->pc); |
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else |
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debug("%016llx", (long long)cpu->pc); |
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debug(" <%s>\n", symbol != NULL? symbol : " no symbol "); |
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if (bits32) { |
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/* 32-bit: */ |
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for (i=0; i<nregs; i++) { |
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if ((i % 4) == 0) |
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debug("cpu%i:", x); |
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debug(" r%02i = 0x%08x ", i, |
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(int)cpu->cd.newmips.r[i]); |
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if ((i % 4) == 3) |
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debug("\n"); |
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} |
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} else { |
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/* 64-bit: */ |
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for (i=0; i<nregs; i++) { |
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int r = (i >> 1) + ((i & 1) << 4); |
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if ((i % 2) == 0) |
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debug("cpu%i:", x); |
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debug(" r%02i = 0x%016llx ", r, |
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(long long)cpu->cd.newmips.r[r]); |
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if ((i % 2) == 1) |
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debug("\n"); |
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} |
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} |
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} |
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} |
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/* |
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* newmips_cpu_register_match(): |
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*/ |
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void newmips_cpu_register_match(struct machine *m, char *name, |
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int writeflag, uint64_t *valuep, int *match_register) |
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{ |
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int cpunr = 0; |
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/* CPU number: */ |
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/* TODO */ |
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/* Register name: */ |
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if (strcasecmp(name, "pc") == 0) { |
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if (writeflag) { |
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m->cpus[cpunr]->pc = *valuep; |
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} else |
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*valuep = m->cpus[cpunr]->pc; |
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*match_register = 1; |
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} |
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} |
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/* |
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* newmips_cpu_interrupt(): |
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*/ |
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int newmips_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr) |
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{ |
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fatal("newmips_cpu_interrupt(): TODO\n"); |
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return 0; |
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} |
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/* |
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* newmips_cpu_interrupt_ack(): |
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*/ |
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int newmips_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr) |
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{ |
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/* fatal("newmips_cpu_interrupt_ack(): TODO\n"); */ |
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return 0; |
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} |
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/* |
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* newmips_cpu_disassemble_instr(): |
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* |
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* Convert an instruction word into human readable format, for instruction |
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* tracing. |
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* |
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* If running is 1, cpu->pc should be the address of the instruction. |
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* |
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* If running is 0, things that depend on the runtime environment (eg. |
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* register contents) will not be shown, and addr will be used instead of |
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* cpu->pc for relative addresses. |
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*/ |
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int newmips_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr, |
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int running, uint64_t dumpaddr, int bintrans) |
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{ |
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uint64_t offset; |
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uint32_t iword; |
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char *symbol; |
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if (running) |
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dumpaddr = cpu->pc; |
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symbol = get_symbol_name(&cpu->machine->symbol_context, |
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dumpaddr, &offset); |
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if (symbol != NULL && offset==0) |
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debug("<%s>\n", symbol); |
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if (cpu->machine->ncpus > 1 && running) |
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debug("cpu%i: ", cpu->cpu_id); |
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if (cpu->cd.newmips.bits == 32) |
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debug("%08x", (int)dumpaddr); |
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else |
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debug("%016llx", (long long)dumpaddr); |
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if (cpu->byte_order == EMUL_BIG_ENDIAN) |
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iword = (instr[0] << 24) + (instr[1] << 16) + (instr[2] << 8) |
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+ instr[3]; |
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else |
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iword = (instr[3] << 24) + (instr[2] << 16) + (instr[1] << 8) |
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+ instr[0]; |
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debug(": %08x\t", iword); |
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/* |
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* Decode the instruction: |
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*/ |
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debug("TODO\n"); |
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return sizeof(iword); |
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} |
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#include "tmp_newmips_tail.c" |
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