/[gxemul]/trunk/src/cpus/cpu_mips_instr_loadstore.c
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Annotation of /trunk/src/cpus/cpu_mips_instr_loadstore.c

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Revision 42 - (hide annotations)
Mon Oct 8 16:22:32 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 7789 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1613 2007/06/15 20:11:26 debug Exp $
20070501	Continuing a little on m88k disassembly (control registers,
		more instructions).
		Adding a dummy mvme88k machine mode.
20070502	Re-adding MIPS load/store alignment exceptions.
20070503	Implementing more of the M88K disassembly code.
20070504	Adding disassembly of some more M88K load/store instructions.
		Implementing some relatively simple M88K instructions (br.n,
		xor[.u] imm, and[.u] imm).
20070505	Implementing M88K three-register and, or, xor, and jmp[.n],
		bsr[.n] including function call trace stuff.
		Applying a patch from Bruce M. Simpson which implements the
		SYSCON_BOARD_CPU_CLOCK_FREQ_ID object of the syscon call in
		the yamon PROM emulation.
20070506	Implementing M88K bb0[.n] and bb1[.n], and skeletons for
		ldcr and stcr (although no control regs are implemented yet).
20070509	Found and fixed the bug which caused Linux for QEMU_MIPS to
		stop working in 0.4.5.1: It was a faulty change to the MIPS
		'sc' and 'scd' instructions I made while going through gcc -W
		warnings on 20070428.
20070510	Updating the Linux/QEMU_MIPS section in guestoses.html to
		use mips-test-0.2.tar.gz instead of 0.1.
		A big thank you to Miod Vallat for sending me M88K manuals.
		Implementing more M88K instructions (addu, subu, div[u], mulu,
		ext[u], clr, set, cmp).
20070511	Fixing bugs in the M88K "and" and "and.u" instructions (found
		by comparing against the manual).
		Implementing more M88K instructions (mask[.u], mak, bcnd (auto-
		generated)) and some more control register details.
		Cleanup: Removing the experimental AVR emulation mode and
		corresponding devices; AVR emulation wasn't really meaningful.
		Implementing autogeneration of most M88K loads/stores. The
		rectangle drawing demo (with -O0) for M88K runs :-)
		Beginning on M88K exception handling.
		More M88K instructions: tb0, tb1, rte, sub, jsr[.n].
		Adding some skeleton MVME PROM ("BUG") emulation.
20070512	Fixing a bug in the M88K cmp instruction.
		Adding the M88K lda (scaled register) instruction.
		Fixing bugs in 64-bit (32-bit pairs) M88K loads/stores.
		Removing the unused tick_hz stuff from the machine struct.
		Implementing the M88K xmem instruction. OpenBSD/mvme88k gets
		far enough to display the Copyright banner :-)
		Implementing subu.co (guess), addu.co, addu.ci, ff0, and ff1.
		Adding a dev_mvme187, for MVME187-specific devices/registers.
		OpenBSD/mvme88k prints more boot messages. :)
20070515	Continuing on MVME187 emulation (adding more devices, beginning
		on the CMMUs, etc).
		Adding the M88K and.c, xor.c, and or.c instructions, and making
		sure that mul, div, etc cause exceptions if executed when SFD1
		is disabled.
20070517	Continuing on M88K and MVME187 emulation in general; moving
		the CMMU registers to the CPU struct, separating dev_pcc2 from
		dev_mvme187, and beginning on memory_m88k.c (BATC and PATC).
		Fixing a bug in 64-bit (32-bit pairs) M88K fast stores.
		Implementing the clock part of dev_mk48txx.
		Implementing the M88K fstcr and xcr instructions.
		Implementing m88k_cpu_tlbdump().
		Beginning on the implementation of a separate address space
		for M88K .usr loads/stores.
20070520	Removing the non-working (skeleton) Sandpoint, SonyNEWS, SHARK
		Dnard, and Zaurus machine modes.
		Experimenting with dyntrans to_be_translated read-ahead. It
		seems to give a very small performance increase for MIPS
		emulation, but a large performance degradation for SuperH. Hm.
20070522	Disabling correct SuperH ITLB emulation; it does not seem to be
		necessary in order to let SH4 guest OSes run, and it slows down
		userspace code.
		Implementing "samepage" branches for SuperH emulation, and some
		other minor speed hacks.
20070525	Continuing on M88K memory-related stuff: exceptions, memory
		transaction register contents, etc.
		Implementing the M88K subu.ci instruction.
		Removing the non-working (skeleton) Iyonix machine mode.
		OpenBSD/mvme88k reaches userland :-), starts executing
		/sbin/init's instructions, and issues a few syscalls, before
		crashing.
20070526	Fixing bugs in dev_mk48txx, so that OpenBSD/mvme88k detects
		the correct time-of-day.
		Implementing a generic IRQ controller for the test machines
		(dev_irqc), similar to a proposed patch from Petr Stepan.
		Experimenting some more with translation read-ahead.
		Adding an "expect" script for automated OpenBSD/landisk
		install regression/performance tests.
20070527	Adding a dummy mmEye (SH3) machine mode skeleton.
		FINALLY found the strange M88K bug I have been hunting: I had
		not emulated the SNIP value for exceptions occurring in
		branch delay slots correctly.
		Implementing correct exceptions for 64-bit M88K loads/stores.
		Address to symbol lookups are now disabled when M88K is
		running in usermode (because usermode addresses don't have
		anything to do with supervisor addresses).
20070531	Removing the mmEye machine mode skeleton.
20070604	Some minor code cleanup.
20070605	Moving src/useremul.c into a subdir (src/useremul/), and
		cleaning up some more legacy constructs.
		Adding -Wstrict-aliasing and -fstrict-aliasing detection to
		the configure script.
20070606	Adding a check for broken GCC on Solaris to the configure
		script. (GCC 3.4.3 on Solaris cannot handle static variables
		which are initialized to 0 or NULL. :-/)
		Removing the old (non-working) ARC emulation modes: NEC RD94,
		R94, R96, and R98, and the last traces of Olivetti M700 and
		Deskstation Tyne.
		Removing the non-working skeleton WDSC device (dev_wdsc).
20070607	Thinking about how to use the host's cc + ld at runtime to
		generate native code. (See experiments/native_cc_ld_test.i
		for an example.)
20070608	Adding a program counter sampling timer, which could be useful
		for native code generation experiments.
		The KN02_CSR_NRMMOD bit in the DECstation 5000/200 (KN02) CSR
		should always be set, to allow a 5000/200 PROM to boot.
20070609	Moving out breakpoint details from the machine struct into
		a helper struct, and removing the limit on max nr of
		breakpoints.
20070610	Moving out tick functions into a helper struct as well (which
		also gets rid of the max limit).
20070612	FINALLY figured out why Debian/DECstation stopped working when
		translation read-ahead was enabled: in src/memory_rw.c, the
		call to invalidate_code_translation was made also if the
		memory access was an instruction load (if the page was mapped
		as writable); it shouldn't be called in that case.
20070613	Implementing some more MIPS32/64 revision 2 instructions: di,
		ei, ext, dext, dextm, dextu, and ins.
20070614	Implementing an instruction combination for the NetBSD/arm
		idle loop (making the host not use any cpu if NetBSD/arm
		inside the emulator is not using any cpu).
		Increasing the nr of ARM VPH entries from 128 to 384.
20070615	Removing the ENABLE_arch stuff from the configure script, so
		that all included architectures are included in both release
		and development builds.
		Moving memory related helper functions from misc.c to memory.c.
		Adding preliminary instructions for netbooting NetBSD/pmppc to
		guestoses.html; it doesn't work yet, there are weird timeouts.
		Beginning a total rewrite of the userland emulation modes
		(removing all emulation modes, beginning from scratch with
		NetBSD/MIPS and FreeBSD/Alpha only).
20070616	After fixing a bug in the DEC21143 NIC (the TDSTAT_OWN bit was
		only cleared for the last segment when transmitting, not all
		segments), NetBSD/pmppc boots with root-on-nfs without the
		timeouts. Updating guestoses.html.
		Removing the skeleton PSP (Playstation Portable) mode.
		Moving X11-related stuff in the machine struct into a helper
		struct.
		Cleanup of out-of-memory checks, to use a new CHECK_ALLOCATION
		macro (which prints a meaningful error message).
		Adding a COMMENT to each machine and device (for automagic
		.index comment generation).
		Doing regression testing for the next release.

==============  RELEASE 0.4.6  ==============


1 dpavlin 24 /*
2 dpavlin 34 * Copyright (C) 2006-2007 Anders Gavare. All rights reserved.
3 dpavlin 24 *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 42 * $Id: cpu_mips_instr_loadstore.c,v 1.14 2007/05/02 08:26:12 debug Exp $
29 dpavlin 24 *
30     * MIPS load/store instructions; the following args are used:
31     *
32     * arg[0] = pointer to the register to load to or store from
33     * arg[1] = pointer to the base register
34     * arg[2] = offset (as an int32_t)
35     *
36     * The GENERIC function always checks for alignment, and supports both big
37     * and little endian byte order.
38     *
39     * The quick function is included twice (big/little endian) for each
40     * GENERIC function.
41     */
42    
43    
44     #ifdef LS_INCLUDE_GENERIC
45     void LS_GENERIC_N(struct cpu *cpu, struct mips_instr_call *ic)
46     {
47     MODE_int_t addr = reg(ic->arg[1]) + (int32_t)ic->arg[2];
48     uint8_t data[LS_SIZE];
49     #ifdef LS_LOAD
50     uint64_t x;
51     #endif
52    
53     /* Synchronize the PC: */
54     int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
55     / sizeof(struct mips_instr_call);
56     cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)<<MIPS_INSTR_ALIGNMENT_SHIFT);
57     cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
58    
59     #ifndef LS_1
60     /* Check alignment: */
61     if (addr & (LS_SIZE - 1)) {
62 dpavlin 42 #if 1
63     /* Cause an address alignment exception: */
64     mips_cpu_exception(cpu,
65     #ifdef LS_LOAD
66     EXCEPTION_ADEL,
67     #else
68     EXCEPTION_ADES,
69     #endif
70     0, addr, 0, 0, 0, 0);
71     #else
72     fatal("{ mips dyntrans alignment exception, size = %i,"
73     " addr = %016"PRIx64", pc = %016"PRIx64" }\n", LS_SIZE,
74 dpavlin 24 (uint64_t) addr, cpu->pc);
75    
76     /* TODO: Generalize this into a abort_call, or similar: */
77     cpu->running = 0;
78     debugger_n_steps_left_before_interaction = 0;
79     cpu->cd.mips.next_ic = &nothing_call;
80 dpavlin 42 #endif
81 dpavlin 24 return;
82     }
83     #endif
84    
85     #ifdef LS_LOAD
86     if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data),
87     MEM_READ, CACHE_DATA)) {
88     /* Exception. */
89     return;
90     }
91     x = memory_readmax64(cpu, data, LS_SIZE);
92     #ifdef LS_SIGNED
93     #ifdef LS_1
94     x = (int8_t)x;
95     #endif
96     #ifdef LS_2
97     x = (int16_t)x;
98     #endif
99     #ifdef LS_4
100     x = (int32_t)x;
101     #endif
102     #endif
103     reg(ic->arg[0]) = x;
104     #else /* LS_STORE: */
105     memory_writemax64(cpu, data, LS_SIZE, reg(ic->arg[0]));
106     if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data),
107     MEM_WRITE, CACHE_DATA)) {
108     /* Exception. */
109     return;
110     }
111     #endif
112     }
113     #endif /* LS_INCLUDE_GENERIC */
114    
115    
116     void LS_N(struct cpu *cpu, struct mips_instr_call *ic)
117     {
118     MODE_uint_t addr = reg(ic->arg[1]) + (int32_t)ic->arg[2];
119     unsigned char *p;
120     #ifdef MODE32
121     #ifdef LS_LOAD
122     p = cpu->cd.mips.host_load[addr >> 12];
123     #else
124     p = cpu->cd.mips.host_store[addr >> 12];
125     #endif
126     #else /* !MODE32 */
127     const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
128     const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
129     const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
130     uint32_t x1, x2, x3;
131     struct DYNTRANS_L2_64_TABLE *l2;
132     struct DYNTRANS_L3_64_TABLE *l3;
133    
134     x1 = (addr >> (64-DYNTRANS_L1N)) & mask1;
135     x2 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
136     x3 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) & mask3;
137     /* fatal("X3: addr=%016"PRIx64" x1=%x x2=%x x3=%x\n",
138     (uint64_t) addr, (int) x1, (int) x2, (int) x3); */
139     l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
140     /* fatal(" l2 = %p\n", l2); */
141     l3 = l2->l3[x2];
142     /* fatal(" l3 = %p\n", l3); */
143     #ifdef LS_LOAD
144     p = l3->host_load[x3];
145     #else
146     p = l3->host_store[x3];
147     #endif
148     /* fatal(" p = %p\n", p); */
149     #endif
150    
151     if (p == NULL
152     #ifndef LS_1
153     || addr & (LS_SIZE - 1)
154     #endif
155     ) {
156     LS_GENERIC_N(cpu, ic);
157     return;
158     }
159    
160     addr &= 0xfff;
161    
162     #ifdef LS_LOAD
163     /* Load: */
164    
165     #ifdef LS_1
166     reg(ic->arg[0]) =
167     #ifdef LS_SIGNED
168     (int8_t)
169     #endif
170     p[addr];
171     #endif /* LS_1 */
172    
173     #ifdef LS_2
174     reg(ic->arg[0]) =
175     #ifdef LS_SIGNED
176     (int16_t)
177     #endif
178     #ifdef LS_BE
179     #ifdef HOST_BIG_ENDIAN
180     ( *(uint16_t *)(p + addr) );
181     #else
182     ((p[addr]<<8) + p[addr+1]);
183     #endif
184     #else
185     #ifdef HOST_LITTLE_ENDIAN
186     ( *(uint16_t *)(p + addr) );
187     #else
188     (p[addr] + (p[addr+1]<<8));
189     #endif
190     #endif
191     #endif /* LS_2 */
192    
193     #ifdef LS_4
194     reg(ic->arg[0]) =
195     #ifdef LS_SIGNED
196     (int32_t)
197     #else
198     (uint32_t)
199     #endif
200     #ifdef LS_BE
201     #ifdef HOST_BIG_ENDIAN
202     ( *(uint32_t *)(p + addr) );
203     #else
204     ((p[addr]<<24) + (p[addr+1]<<16) + (p[addr+2]<<8) + p[addr+3]);
205     #endif
206     #else
207     #ifdef HOST_LITTLE_ENDIAN
208     ( *(uint32_t *)(p + addr) );
209     #else
210     (p[addr] + (p[addr+1]<<8) + (p[addr+2]<<16) + (p[addr+3]<<24));
211     #endif
212     #endif
213     #endif /* LS_4 */
214    
215     #ifdef LS_8
216     *((uint64_t *)ic->arg[0]) =
217     #ifdef LS_BE
218     #ifdef HOST_BIG_ENDIAN
219     ( *(uint64_t *)(p + addr) );
220     #else
221     ((uint64_t)p[addr] << 56) + ((uint64_t)p[addr+1] << 48) +
222     ((uint64_t)p[addr+2] << 40) + ((uint64_t)p[addr+3] << 32) +
223     ((uint64_t)p[addr+4] << 24) +
224     (p[addr+5] << 16) + (p[addr+6] << 8) + p[addr+7];
225     #endif
226     #else
227     #ifdef HOST_LITTLE_ENDIAN
228     ( *(uint64_t *)(p + addr) );
229     #else
230     p[addr+0] + (p[addr+1] << 8) + (p[addr+2] << 16) +
231     ((uint64_t)p[addr+3] << 24) + ((uint64_t)p[addr+4] << 32) +
232     ((uint64_t)p[addr+5] << 40) + ((uint64_t)p[addr+6] << 48) +
233     ((uint64_t)p[addr+7] << 56);
234     #endif
235     #endif
236     #endif /* LS_8 */
237    
238     #else
239     /* Store: */
240    
241     #ifdef LS_1
242     p[addr] = reg(ic->arg[0]);
243     #endif
244     #ifdef LS_2
245     { uint32_t x = reg(ic->arg[0]);
246     #ifdef LS_BE
247     #ifdef HOST_BIG_ENDIAN
248     *((uint16_t *)(p+addr)) = x; }
249     #else
250     p[addr] = x >> 8; p[addr+1] = x; }
251     #endif
252     #else
253     #ifdef HOST_LITTLE_ENDIAN
254     *((uint16_t *)(p+addr)) = x; }
255     #else
256     p[addr] = x; p[addr+1] = x >> 8; }
257     #endif
258     #endif
259     #endif /* LS_2 */
260     #ifdef LS_4
261     { uint32_t x = reg(ic->arg[0]);
262     #ifdef LS_BE
263     #ifdef HOST_BIG_ENDIAN
264     *((uint32_t *)(p+addr)) = x; }
265     #else
266     p[addr] = x >> 24; p[addr+1] = x >> 16;
267     p[addr+2] = x >> 8; p[addr+3] = x; }
268     #endif
269     #else
270     #ifdef HOST_LITTLE_ENDIAN
271     *((uint32_t *)(p+addr)) = x; }
272     #else
273     p[addr] = x; p[addr+1] = x >> 8;
274     p[addr+2] = x >> 16; p[addr+3] = x >> 24; }
275     #endif
276     #endif
277     #endif /* LS_4 */
278     #ifdef LS_8
279     { uint64_t x = *(uint64_t *)(ic->arg[0]);
280     #ifdef LS_BE
281     #ifdef HOST_BIG_ENDIAN
282     *((uint64_t *)(p+addr)) = x; }
283     #else
284     p[addr] = x >> 56; p[addr+1] = x >> 48; p[addr+2] = x >> 40;
285     p[addr+3] = x >> 32; p[addr+4] = x >> 24; p[addr+5] = x >> 16;
286     p[addr+6] = x >> 8; p[addr+7] = x; }
287     #endif
288     #else
289     #ifdef HOST_LITTLE_ENDIAN
290     *((uint64_t *)(p+addr)) = x; }
291     #else
292     p[addr] = x; p[addr+1] = x >> 8; p[addr+2] = x >> 16;
293     p[addr+3] = x >> 24; p[addr+4] = x >> 32; p[addr+5] = x >> 40;
294     p[addr+6] = x >> 48; p[addr+7] = x >> 56; }
295     #endif
296     #endif
297     #endif /* LS_8 */
298    
299     #endif /* store */
300     }
301    

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