25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: cpu_mips_instr.c,v 1.127 2007/04/28 09:19:51 debug Exp $ |
* $Id: cpu_mips_instr.c,v 1.133 2007/06/13 02:08:03 debug Exp $ |
29 |
* |
* |
30 |
* MIPS instructions. |
* MIPS instructions. |
31 |
* |
* |
1149 |
|
|
1150 |
|
|
1151 |
/* |
/* |
1152 |
|
* ins: Insert bitfield. |
1153 |
|
* |
1154 |
|
* arg[0] = pointer to rt |
1155 |
|
* arg[1] = pointer to rs |
1156 |
|
* arg[2] = (msb << 5) + lsb |
1157 |
|
*/ |
1158 |
|
X(ins) |
1159 |
|
{ |
1160 |
|
int msb = ic->arg[2] >> 5, pos = ic->arg[2] & 0x1f; |
1161 |
|
int size = msb + 1 - pos; |
1162 |
|
uint32_t rt = reg(ic->arg[0]); |
1163 |
|
uint32_t rs = reg(ic->arg[1]); |
1164 |
|
uint32_t mask = (-1) << pos; |
1165 |
|
|
1166 |
|
mask <<= (32 - pos - size); |
1167 |
|
mask >>= (32 - pos - size); |
1168 |
|
|
1169 |
|
reg(ic->arg[0]) = (int32_t) ((rt & ~mask) | ((rs << pos) & mask)); |
1170 |
|
} |
1171 |
|
|
1172 |
|
|
1173 |
|
/* |
1174 |
* ext: Extract bitfield. |
* ext: Extract bitfield. |
1175 |
* |
* |
1176 |
* arg[0] = pointer to rt |
* arg[0] = pointer to rt |
1179 |
*/ |
*/ |
1180 |
X(ext) |
X(ext) |
1181 |
{ |
{ |
1182 |
fatal("ext: todo\n"); |
int msbd = ic->arg[2] >> 5, lsb = ic->arg[2] & 0x1f; |
1183 |
exit(1); |
int size = msbd + 1; |
1184 |
|
uint32_t rs = reg(ic->arg[1]); |
1185 |
|
uint32_t x = (rs << (32-lsb-size)) >> (32-lsb-size); |
1186 |
|
reg(ic->arg[0]) = (int32_t) (x >> lsb); |
1187 |
|
} |
1188 |
|
|
1189 |
|
|
1190 |
|
/* |
1191 |
|
* dext: Extract bitfield (64-bit). |
1192 |
|
* |
1193 |
|
* arg[0] = pointer to rt |
1194 |
|
* arg[1] = pointer to rs |
1195 |
|
* arg[2] = (msbd << 6) + lsb |
1196 |
|
*/ |
1197 |
|
X(dext) |
1198 |
|
{ |
1199 |
|
int msbd = ic->arg[2] >> 6, lsb = ic->arg[2] & 0x3f; |
1200 |
|
int size = msbd + 1; |
1201 |
|
uint64_t rs = reg(ic->arg[1]); |
1202 |
|
uint64_t x = (rs << (uint64_t)(64-lsb-size)) >> (uint64_t)(64-lsb-size); |
1203 |
|
reg(ic->arg[0]) = x >> lsb; |
1204 |
} |
} |
1205 |
|
|
1206 |
|
|
2088 |
|
|
2089 |
|
|
2090 |
/* |
/* |
2091 |
|
* ei_or_di: MIPS32/64 rev 2, Enable or disable interrupts |
2092 |
|
* |
2093 |
|
* arg[0] = ptr to rt |
2094 |
|
* arg[1] = non-zero to enable interrupts |
2095 |
|
*/ |
2096 |
|
X(ei_or_di) |
2097 |
|
{ |
2098 |
|
reg(ic->arg[0]) = cpu->cd.mips.coproc[0]->reg[COP0_STATUS]; |
2099 |
|
if (ic->arg[1]) |
2100 |
|
cpu->cd.mips.coproc[0]->reg[COP0_STATUS] |= STATUS_IE; |
2101 |
|
else |
2102 |
|
cpu->cd.mips.coproc[0]->reg[COP0_STATUS] &= ~STATUS_IE; |
2103 |
|
} |
2104 |
|
|
2105 |
|
|
2106 |
|
/* |
2107 |
* rfe: Return from exception handler (R2000/R3000) |
* rfe: Return from exception handler (R2000/R3000) |
2108 |
*/ |
*/ |
2109 |
X(rfe) |
X(rfe) |
2341 |
} |
} |
2342 |
X(sc) |
X(sc) |
2343 |
{ |
{ |
2344 |
MODE_uint_t addr = reg(ic->arg[1]) + (int32_t)ic->arg[2]; |
MODE_int_t addr = reg(ic->arg[1]) + (int32_t)ic->arg[2]; |
2345 |
uint64_t r = reg(ic->arg[0]); |
uint64_t r = reg(ic->arg[0]); |
2346 |
int low_pc, i; |
int low_pc, i; |
2347 |
uint8_t word[sizeof(uint32_t)]; |
uint8_t word[sizeof(uint32_t)]; |
2399 |
} |
} |
2400 |
X(scd) |
X(scd) |
2401 |
{ |
{ |
2402 |
MODE_uint_t addr = reg(ic->arg[1]) + (int32_t)ic->arg[2]; |
MODE_int_t addr = reg(ic->arg[1]) + (int32_t)ic->arg[2]; |
2403 |
uint64_t r = reg(ic->arg[0]); |
uint64_t r = reg(ic->arg[0]); |
2404 |
int low_pc, i; |
int low_pc, i; |
2405 |
uint8_t word[sizeof(uint64_t)]; |
uint8_t word[sizeof(uint64_t)]; |
3427 |
*/ |
*/ |
3428 |
X(to_be_translated) |
X(to_be_translated) |
3429 |
{ |
{ |
|
#ifdef NATIVE_CODE_GENERATION |
|
|
int native = 0; |
|
|
#endif |
|
3430 |
uint64_t addr, low_pc; |
uint64_t addr, low_pc; |
3431 |
uint32_t iword, imm; |
uint32_t iword, imm; |
3432 |
unsigned char *page; |
unsigned char *page; |
3707 |
} |
} |
3708 |
} |
} |
3709 |
if (rd != MIPS_GPR_ZERO) { |
if (rd != MIPS_GPR_ZERO) { |
3710 |
fatal("TODO: rd NON-zero\n"); |
if (!cpu->translation_readahead) |
3711 |
|
fatal("TODO: rd NON-zero\n"); |
3712 |
goto bad; |
goto bad; |
3713 |
} |
} |
3714 |
/* These instructions don't use rd. */ |
/* These instructions don't use rd. */ |
3739 |
} else { |
} else { |
3740 |
ic->f = instr(jr); |
ic->f = instr(jr); |
3741 |
} |
} |
3742 |
|
if (cpu->translation_readahead > 2) |
3743 |
|
cpu->translation_readahead = 2; |
3744 |
break; |
break; |
3745 |
case SPECIAL_JALR: |
case SPECIAL_JALR: |
3746 |
if (cpu->machine->show_trace_tree) |
if (cpu->machine->show_trace_tree) |
3750 |
break; |
break; |
3751 |
} |
} |
3752 |
if (cpu->delay_slot) { |
if (cpu->delay_slot) { |
3753 |
fatal("TODO: branch in delay slot? (1)\n"); |
if (!cpu->translation_readahead) |
3754 |
|
fatal("TODO: branch in delay " |
3755 |
|
"slot? (1)\n"); |
3756 |
goto bad; |
goto bad; |
3757 |
} |
} |
3758 |
break; |
break; |
3850 |
ic->f = samepage_function; |
ic->f = samepage_function; |
3851 |
} |
} |
3852 |
if (cpu->delay_slot) { |
if (cpu->delay_slot) { |
3853 |
fatal("TODO: branch in delay slot? (2)\n"); |
if (!cpu->translation_readahead) |
3854 |
|
fatal("TODO: branch in delay slot? (2)\n"); |
3855 |
goto bad; |
goto bad; |
3856 |
} |
} |
3857 |
break; |
break; |
3923 |
switch (main_opcode) { |
switch (main_opcode) { |
3924 |
case HI6_J: |
case HI6_J: |
3925 |
ic->f = instr(j); |
ic->f = instr(j); |
3926 |
|
if (cpu->translation_readahead > 2) |
3927 |
|
cpu->translation_readahead = 2; |
3928 |
break; |
break; |
3929 |
case HI6_JAL: |
case HI6_JAL: |
3930 |
if (cpu->machine->show_trace_tree) |
if (cpu->machine->show_trace_tree) |
3936 |
ic->arg[0] = (iword & 0x03ffffff) << 2; |
ic->arg[0] = (iword & 0x03ffffff) << 2; |
3937 |
ic->arg[1] = (addr & 0xffc) + 8; |
ic->arg[1] = (addr & 0xffc) + 8; |
3938 |
if (cpu->delay_slot) { |
if (cpu->delay_slot) { |
3939 |
fatal("TODO: branch in delay slot (=%i)? (3); addr=%016" |
if (!cpu->translation_readahead) |
3940 |
PRIx64" iword=%08"PRIx32"\n", cpu->delay_slot, |
fatal("TODO: branch in delay slot (=%i)? (3);" |
3941 |
(uint64_t)addr, iword); |
" addr=%016"PRIx64" iword=%08"PRIx32"\n", |
3942 |
|
cpu->delay_slot, (uint64_t)addr, iword); |
3943 |
goto bad; |
goto bad; |
3944 |
} |
} |
3945 |
break; |
break; |
3976 |
cpu->cd.mips.cpu_type.isa_level < 32) { |
cpu->cd.mips.cpu_type.isa_level < 32) { |
3977 |
static int warned = 0; |
static int warned = 0; |
3978 |
ic->f = instr(reserved); |
ic->f = instr(reserved); |
3979 |
if (!warned) { |
if (!warned && |
3980 |
|
!cpu->translation_readahead) { |
3981 |
fatal("{ WARNING: Attempt to " |
fatal("{ WARNING: Attempt to " |
3982 |
"execute the WAIT instruct" |
"execute the WAIT instruct" |
3983 |
"ion, but the emulated CPU " |
"ion, but the emulated CPU " |
3993 |
if (cpu->cd.mips.cpu_type.rev != MIPS_R4100) { |
if (cpu->cd.mips.cpu_type.rev != MIPS_R4100) { |
3994 |
static int warned = 0; |
static int warned = 0; |
3995 |
ic->f = instr(reserved); |
ic->f = instr(reserved); |
3996 |
if (!warned) { |
if (!warned && |
3997 |
|
!cpu->translation_readahead) { |
3998 |
fatal("{ WARNING: Attempt to " |
fatal("{ WARNING: Attempt to " |
3999 |
"execute a R41xx instruct" |
"execute a R41xx instruct" |
4000 |
"ion, but the emulated CPU " |
"ion, but the emulated CPU " |
4023 |
} else |
} else |
4024 |
goto bad; |
goto bad; |
4025 |
break; |
break; |
4026 |
default:fatal("UNIMPLEMENTED cop0 (func 0x%02x)\n", |
default:if (!cpu->translation_readahead) |
4027 |
iword & 0xff); |
fatal("UNIMPLEMENTED cop0 (func " |
4028 |
|
"0x%02x)\n", iword & 0xff); |
4029 |
goto bad; |
goto bad; |
4030 |
} |
} |
4031 |
break; |
break; |
4069 |
COMBINE(netbsd_r3k_cache_inv); |
COMBINE(netbsd_r3k_cache_inv); |
4070 |
|
|
4071 |
break; |
break; |
4072 |
case 8: if (iword == 0x4100ffff) { |
case COPz_MFMCz: |
4073 |
|
if ((iword & 0xffdf) == 0x6000) { |
4074 |
|
/* MIPS32/64 rev 2 "ei" or "di": */ |
4075 |
|
if (cpu->cd.mips.cpu_type.isa_level < 32 || |
4076 |
|
cpu->cd.mips.cpu_type.isa_revision < 2) { |
4077 |
|
static int warning_ei_di = 0; |
4078 |
|
if (!warning_ei_di && |
4079 |
|
!cpu->translation_readahead) { |
4080 |
|
fatal("[ WARNING! MIPS32/64 " |
4081 |
|
"revision 2 di or ei opcode" |
4082 |
|
" used, but the %s process" |
4083 |
|
"or does not implement " |
4084 |
|
"such instructions. Only " |
4085 |
|
"printing this " |
4086 |
|
"warning once. ]\n", |
4087 |
|
cpu->cd.mips.cpu_type.name); |
4088 |
|
warning_ei_di = 1; |
4089 |
|
} |
4090 |
|
ic->f = instr(reserved); |
4091 |
|
break; |
4092 |
|
} |
4093 |
|
ic->f = instr(ei_or_di); |
4094 |
|
ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rt]; |
4095 |
|
if (rt == MIPS_GPR_ZERO) |
4096 |
|
ic->arg[0] = |
4097 |
|
(size_t)&cpu->cd.mips.scratch; |
4098 |
|
ic->arg[1] = iword & 0x20; |
4099 |
|
} else { |
4100 |
|
if (!cpu->translation_readahead) |
4101 |
|
fatal("Unimplemented COP0_MFMCz\n"); |
4102 |
|
goto bad; |
4103 |
|
} |
4104 |
|
break; |
4105 |
|
case COPz_BCzc: |
4106 |
|
if (iword == 0x4100ffff) { |
4107 |
/* R2020 DECstation write-loop thingy. */ |
/* R2020 DECstation write-loop thingy. */ |
4108 |
ic->f = instr(nop); |
ic->f = instr(nop); |
4109 |
} else { |
} else { |
4110 |
fatal("Unimplemented blah blah zzzz...\n"); |
if (!cpu->translation_readahead) |
4111 |
|
fatal("Unimplemented COP0_BCzc\n"); |
4112 |
goto bad; |
goto bad; |
4113 |
} |
} |
4114 |
break; |
break; |
4115 |
|
|
4116 |
default:fatal("UNIMPLEMENTED cop0 (rs = %i)\n", rs); |
default:if (!cpu->translation_readahead) |
4117 |
|
fatal("UNIMPLEMENTED cop0 (rs = %i)\n", rs); |
4118 |
goto bad; |
goto bad; |
4119 |
} |
} |
4120 |
break; |
break; |
4141 |
ic->arg[2] = (int32_t) ((imm << |
ic->arg[2] = (int32_t) ((imm << |
4142 |
MIPS_INSTR_ALIGNMENT_SHIFT) + (addr & 0xffc) + 4); |
MIPS_INSTR_ALIGNMENT_SHIFT) + (addr & 0xffc) + 4); |
4143 |
if (cpu->delay_slot) { |
if (cpu->delay_slot) { |
4144 |
fatal("TODO: branch in delay slot? (4)\n"); |
if (!cpu->translation_readahead) |
4145 |
|
fatal("TODO: branch in delay slot 4\n"); |
4146 |
goto bad; |
goto bad; |
4147 |
} |
} |
4148 |
if (cpu->cd.mips.cpu_type.isa_level <= 3 && |
if (cpu->cd.mips.cpu_type.isa_level <= 3 && |
4149 |
ic->arg[0] != 0) { |
ic->arg[0] != 0) { |
4150 |
fatal("Attempt to execute a non-cc-0 BC*" |
if (!cpu->translation_readahead) |
4151 |
" instruction on an isa level %i cpu. " |
fatal("Attempt to execute a non-cc-0 " |
4152 |
"TODO: How should this be handled?\n", |
"BC* instruction on an isa level " |
4153 |
cpu->cd.mips.cpu_type.isa_level); |
"%i cpu. TODO: How should this be " |
4154 |
|
"handled?\n", |
4155 |
|
cpu->cd.mips.cpu_type.isa_level); |
4156 |
goto bad; |
goto bad; |
4157 |
} |
} |
4158 |
|
|
4177 |
ic->arg[0] = (uint32_t)iword & ((1 << 26) - 1); |
ic->arg[0] = (uint32_t)iword & ((1 << 26) - 1); |
4178 |
break; |
break; |
4179 |
|
|
4180 |
default:fatal("COP1 floating point opcode = 0x%02x\n", rs); |
default:if (!cpu->translation_readahead) |
4181 |
|
fatal("COP1 floating point opcode = 0x%02x\n", rs); |
4182 |
goto bad; |
goto bad; |
4183 |
} |
} |
4184 |
break; |
break; |
4191 |
ic->arg[0] = 2; |
ic->arg[0] = 2; |
4192 |
break; |
break; |
4193 |
} |
} |
4194 |
fatal("COP2 functionality not yet implemented\n"); |
if (!cpu->translation_readahead) |
4195 |
|
fatal("COP2 functionality not yet implemented\n"); |
4196 |
goto bad; |
goto bad; |
4197 |
break; |
break; |
4198 |
|
|
4210 |
on MIPSMATE. */ |
on MIPSMATE. */ |
4211 |
ic->f = instr(nop); |
ic->f = instr(nop); |
4212 |
} else { |
} else { |
4213 |
fatal("COP3 iword=0x%08x\n", iword); |
if (!cpu->translation_readahead) |
4214 |
|
fatal("COP3 iword=0x%08x\n", iword); |
4215 |
goto bad; |
goto bad; |
4216 |
} |
} |
4217 |
break; |
break; |
4395 |
ic->f = samepage_function; |
ic->f = samepage_function; |
4396 |
} |
} |
4397 |
if (cpu->delay_slot) { |
if (cpu->delay_slot) { |
4398 |
fatal("TODO: branch in delay slot? (5)\n"); |
if (!cpu->translation_readahead) |
4399 |
|
fatal("TODO: branch in delay slot:5\n"); |
4400 |
goto bad; |
goto bad; |
4401 |
} |
} |
4402 |
break; |
break; |
4403 |
default:fatal("UNIMPLEMENTED regimm rt=%i\n", rt); |
|
4404 |
|
default:if (!cpu->translation_readahead) |
4405 |
|
fatal("UNIMPLEMENTED regimm rt=%i\n", rt); |
4406 |
goto bad; |
goto bad; |
4407 |
} |
} |
4408 |
break; |
break; |
4482 |
ic->arg[1] = (size_t)&cpu->cd.mips.gpr[rs]; |
ic->arg[1] = (size_t)&cpu->cd.mips.gpr[rs]; |
4483 |
ic->arg[2] = (int32_t)imm; |
ic->arg[2] = (int32_t)imm; |
4484 |
if (!store && rt == MIPS_GPR_ZERO) { |
if (!store && rt == MIPS_GPR_ZERO) { |
4485 |
fatal("HM... unusual load linked\n"); |
if (!cpu->translation_readahead) |
4486 |
|
fatal("HM... unusual load linked\n"); |
4487 |
goto bad; |
goto bad; |
4488 |
} |
} |
4489 |
break; |
break; |
4553 |
/* Treat as nop for now: */ |
/* Treat as nop for now: */ |
4554 |
ic->f = instr(nop); |
ic->f = instr(nop); |
4555 |
} else { |
} else { |
4556 |
fatal("TODO: lwc3 not implemented yet\n"); |
if (!cpu->translation_readahead) |
4557 |
|
fatal("TODO: lwc3 not implemented yet\n"); |
4558 |
goto bad; |
goto bad; |
4559 |
} |
} |
4560 |
break; |
break; |
4561 |
|
|
4562 |
case HI6_LQ_MDMX: |
case HI6_LQ_MDMX: |
4563 |
if (cpu->cd.mips.cpu_type.rev == MIPS_R5900) { |
if (cpu->cd.mips.cpu_type.rev == MIPS_R5900) { |
4564 |
fatal("TODO: R5900 128-bit loads\n"); |
if (!cpu->translation_readahead) |
4565 |
|
fatal("TODO: R5900 128-bit loads\n"); |
4566 |
goto bad; |
goto bad; |
4567 |
} |
} |
4568 |
|
|
4569 |
fatal("TODO: MDMX\n"); |
if (!cpu->translation_readahead) |
4570 |
|
fatal("TODO: MDMX\n"); |
4571 |
|
|
4572 |
goto bad; |
goto bad; |
4573 |
/* break */ |
/* break */ |
4574 |
|
|
4575 |
case HI6_SQ_SPECIAL3: |
case HI6_SQ_SPECIAL3: |
4576 |
if (cpu->cd.mips.cpu_type.rev == MIPS_R5900) { |
if (cpu->cd.mips.cpu_type.rev == MIPS_R5900) { |
4577 |
fatal("TODO: R5900 128-bit stores\n"); |
if (!cpu->translation_readahead) |
4578 |
|
fatal("TODO: R5900 128-bit stores\n"); |
4579 |
goto bad; |
goto bad; |
4580 |
} |
} |
4581 |
|
|
4582 |
if (cpu->cd.mips.cpu_type.isa_level < 32 || |
if (cpu->cd.mips.cpu_type.isa_level < 32 || |
4583 |
cpu->cd.mips.cpu_type.isa_revision < 2) { |
cpu->cd.mips.cpu_type.isa_revision < 2) { |
4584 |
static int warning = 0; |
static int warning = 0; |
4585 |
if (!warning) { |
if (!warning && !cpu->translation_readahead) { |
4586 |
fatal("[ WARNING! SPECIAL3 opcode used, but" |
fatal("[ WARNING! SPECIAL3 opcode used, but" |
4587 |
" the %s processor does not implement " |
" the %s processor does not implement " |
4588 |
"such instructions. Only printing this " |
"such instructions. Only printing this " |
4597 |
switch (s6) { |
switch (s6) { |
4598 |
|
|
4599 |
case SPECIAL3_EXT: |
case SPECIAL3_EXT: |
|
/* TODO: Cleanup and extend to DEXT... etc */ |
|
4600 |
{ |
{ |
4601 |
int msbd = rd, lsb = (iword >> 6) & 0x1f; |
int msbd = rd, lsb = (iword >> 6) & 0x1f; |
4602 |
ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rt]; |
ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rt]; |
4608 |
} |
} |
4609 |
break; |
break; |
4610 |
|
|
4611 |
|
case SPECIAL3_DEXT: |
4612 |
|
case SPECIAL3_DEXTM: |
4613 |
|
case SPECIAL3_DEXTU: |
4614 |
|
{ |
4615 |
|
int msbd = rd, lsb = (iword >> 6) & 0x1f; |
4616 |
|
if (s6 == SPECIAL3_DEXTM) |
4617 |
|
msbd += 32; |
4618 |
|
if (s6 == SPECIAL3_DEXTU) |
4619 |
|
lsb += 32; |
4620 |
|
ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rt]; |
4621 |
|
ic->arg[1] = (size_t)&cpu->cd.mips.gpr[rs]; |
4622 |
|
ic->arg[2] = (msbd << 6) + lsb; |
4623 |
|
ic->f = instr(dext); |
4624 |
|
if (rt == MIPS_GPR_ZERO) |
4625 |
|
ic->f = instr(nop); |
4626 |
|
} |
4627 |
|
break; |
4628 |
|
|
4629 |
|
case SPECIAL3_INS: |
4630 |
|
{ |
4631 |
|
int msb = rd, lsb = (iword >> 6) & 0x1f; |
4632 |
|
ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rt]; |
4633 |
|
ic->arg[1] = (size_t)&cpu->cd.mips.gpr[rs]; |
4634 |
|
ic->arg[2] = (msb << 5) + lsb; |
4635 |
|
ic->f = instr(ins); |
4636 |
|
if (rt == MIPS_GPR_ZERO) |
4637 |
|
ic->f = instr(nop); |
4638 |
|
} |
4639 |
|
break; |
4640 |
|
|
4641 |
case SPECIAL3_BSHFL: |
case SPECIAL3_BSHFL: |
4642 |
ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rt]; |
ic->arg[0] = (size_t)&cpu->cd.mips.gpr[rt]; |
4643 |
ic->arg[1] = (size_t)&cpu->cd.mips.gpr[rd]; |
ic->arg[1] = (size_t)&cpu->cd.mips.gpr[rd]; |
4679 |
ic->f = instr(nop); |
ic->f = instr(nop); |
4680 |
break; |
break; |
4681 |
|
|
4682 |
default:fatal("unimplemented rdhwr register rd=%i\n", |
default:if (!cpu->translation_readahead) |
4683 |
rd); |
fatal("unimplemented rdhwr " |
4684 |
|
"register rd=%i\n", rd); |
4685 |
goto bad; |
goto bad; |
4686 |
} |
} |
4687 |
break; |
break; |
4702 |
#ifdef MODE32 |
#ifdef MODE32 |
4703 |
if (x64) { |
if (x64) { |
4704 |
static int has_warned = 0; |
static int has_warned = 0; |
4705 |
if (!has_warned) |
if (!has_warned && !cpu->translation_readahead) { |
4706 |
fatal("[ WARNING/NOTE: attempt to execute a 64-bit" |
fatal("[ WARNING/NOTE: attempt to execute a 64-bit" |
4707 |
" instruction on an emulated 32-bit processor; " |
" instruction on an emulated 32-bit processor; " |
4708 |
"pc=0x%08"PRIx32" ]\n", (uint32_t)cpu->pc); |
"pc=0x%08"PRIx32" ]\n", (uint32_t)cpu->pc); |
4709 |
has_warned = 1; |
has_warned = 1; |
4710 |
ic->f = instr(reserved); |
} |
4711 |
} |
if (cpu->translation_readahead) |
4712 |
#endif |
goto bad; |
4713 |
|
else |
4714 |
|
ic->f = instr(reserved); |
|
#ifdef NATIVE_CODE_GENERATION |
|
|
if (native == 0 || (addr & 0xffc) == 0xffc || |
|
|
ic[1].f != instr(to_be_translated)) { |
|
|
/* TODO */ |
|
|
/* flush etc. */ |
|
4715 |
} |
} |
4716 |
#endif |
#endif |
4717 |
|
|