25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: cpu_mips_instr.c,v 1.124 2007/02/03 10:00:52 debug Exp $ |
* $Id: cpu_mips_instr.c,v 1.126 2007/03/28 18:33:36 debug Exp $ |
29 |
* |
* |
30 |
* MIPS instructions. |
* MIPS instructions. |
31 |
* |
* |
3369 |
*/ |
*/ |
3370 |
X(to_be_translated) |
X(to_be_translated) |
3371 |
{ |
{ |
3372 |
|
#ifdef NATIVE_CODE_GENERATION |
3373 |
|
int native = 0; |
3374 |
|
#endif |
3375 |
uint64_t addr, low_pc; |
uint64_t addr, low_pc; |
3376 |
uint32_t iword, imm; |
uint32_t iword, imm; |
3377 |
unsigned char *page; |
unsigned char *page; |
3380 |
int in_crosspage_delayslot = 0; |
int in_crosspage_delayslot = 0; |
3381 |
void (*samepage_function)(struct cpu *, struct mips_instr_call *); |
void (*samepage_function)(struct cpu *, struct mips_instr_call *); |
3382 |
int store, signedness, size; |
int store, signedness, size; |
|
#ifdef NATIVE_CODE_GENERATION |
|
|
int native = 0; |
|
|
|
|
|
if (!cpu->currently_translating_to_native) |
|
|
cpu->native_code_function_pointer = (void *) &ic->f; |
|
|
#endif |
|
3383 |
|
|
3384 |
/* Figure out the (virtual) address of the instruction: */ |
/* Figure out the (virtual) address of the instruction: */ |
3385 |
low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page) |
low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page) |
3529 |
default:goto bad; |
default:goto bad; |
3530 |
} |
} |
3531 |
} |
} |
|
|
|
|
#ifdef NATIVE_CODE_GENERATION |
|
|
if (native_code_translation_enabled && |
|
|
!cpu->delay_slot && ic->f == instr(nop)) |
|
|
native = native_nop(cpu); |
|
|
#endif |
|
|
|
|
3532 |
break; |
break; |
3533 |
|
|
3534 |
case SPECIAL_ADD: |
case SPECIAL_ADD: |
3855 |
instruction combinations, to do lui + addiu, etc. */ |
instruction combinations, to do lui + addiu, etc. */ |
3856 |
if (rt == MIPS_GPR_ZERO) |
if (rt == MIPS_GPR_ZERO) |
3857 |
ic->f = instr(nop); |
ic->f = instr(nop); |
|
#ifdef NATIVE_CODE_GENERATION |
|
|
#ifdef MODE32 |
|
|
if (native_code_translation_enabled && !cpu->delay_slot |
|
|
&& (addr & 0xffc) >= 4) |
|
|
native = native_set_u32_p32(cpu, |
|
|
ic->arg[1], ®(&cpu->cd.mips.gpr[rt])); |
|
|
#endif |
|
|
#endif |
|
3858 |
break; |
break; |
3859 |
|
|
3860 |
case HI6_J: |
case HI6_J: |
4563 |
} |
} |
4564 |
#endif |
#endif |
4565 |
|
|
4566 |
|
|
4567 |
#ifdef NATIVE_CODE_GENERATION |
#ifdef NATIVE_CODE_GENERATION |
4568 |
/* |
if (native == 0 || (addr & 0xffc) == 0xffc || |
4569 |
* End the native code generation when an instruction is translated |
ic[1].f != instr(to_be_translated)) { |
4570 |
* (or found in the following slow) which is not translatable. |
/* TODO */ |
4571 |
*/ |
/* flush etc. */ |
|
if (cpu->currently_translating_to_native && (!native || |
|
|
(addr & 0xffc) == 0xffc || |
|
|
cpu->cd.mips.next_ic->f != instr(to_be_translated))) { |
|
|
native_commit(cpu); |
|
4572 |
} |
} |
4573 |
#endif |
#endif |
4574 |
|
|