/[gxemul]/trunk/src/cpus/cpu_mips_instr.c
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Diff of /trunk/src/cpus/cpu_mips_instr.c

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revision 25 by dpavlin, Mon Oct 8 16:19:56 2007 UTC revision 26 by dpavlin, Mon Oct 8 16:20:10 2007 UTC
# Line 25  Line 25 
25   *  SUCH DAMAGE.   *  SUCH DAMAGE.
26   *   *
27   *   *
28   *  $Id: cpu_mips_instr.c,v 1.85 2006/06/22 13:22:41 debug Exp $   *  $Id: cpu_mips_instr.c,v 1.87 2006/06/25 02:46:08 debug Exp $
29   *   *
30   *  MIPS instructions.   *  MIPS instructions.
31   *   *
# Line 1616  X(mtc0) Line 1616  X(mtc0)
1616  {  {
1617          int rd = ic->arg[1] & 31, select = ic->arg[1] >> 5;          int rd = ic->arg[1] & 31, select = ic->arg[1] >> 5;
1618          uint64_t tmp = (int32_t) reg(ic->arg[0]);          uint64_t tmp = (int32_t) reg(ic->arg[0]);
1619  #if 0  
         uint32_t oldstatus = cpu->cd.mips.coproc[0]->reg[COP0_STATUS];  
 #endif  
1620          cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)<<MIPS_INSTR_ALIGNMENT_SHIFT);          cpu->pc &= ~((MIPS_IC_ENTRIES_PER_PAGE-1)<<MIPS_INSTR_ALIGNMENT_SHIFT);
1621          cpu->pc |= ic->arg[2];          cpu->pc |= ic->arg[2];
1622    
1623          /*  TODO: cause exception if necessary  */          /*  TODO: cause exception if necessary  */
1624          coproc_register_write(cpu, cpu->cd.mips.coproc[0], rd, &tmp, 0, select);          coproc_register_write(cpu, cpu->cd.mips.coproc[0], rd, &tmp, 0, select);
1625    
1626  #if 0          /*
1627          /*  Interrupts enabled, and any interrupt pending?  */           *  Interrupts enabled, and any interrupt pending? (Note/TODO: This
1628          if (rd == COP0_STATUS && !(oldstatus & STATUS_IE)) {           *  code is duplicated in cpu_dyntrans.c. Fix this?)
1629             */
1630            if (rd == COP0_STATUS && !cpu->delay_slot) {
1631                  uint32_t status = cpu->cd.mips.coproc[0]->reg[COP0_STATUS];                  uint32_t status = cpu->cd.mips.coproc[0]->reg[COP0_STATUS];
1632                  uint32_t cause = cpu->cd.mips.coproc[0]->reg[COP0_CAUSE];                  uint32_t cause = cpu->cd.mips.coproc[0]->reg[COP0_CAUSE];
1633                  /*  NOTE: STATUS_IE happens to match the enable bit also                  /*  NOTE: STATUS_IE happens to match the enable bit also
1634                      on R2000/R3000, so this is ok.  */                      on R2000/R3000, so this is ok.  */
1635                  if (status & STATUS_IE && (status & cause & STATUS_IM_MASK))                  if (status & (STATUS_EXL | STATUS_ERL))
1636                          cpu->running_translated = 0;                          status &= ~STATUS_IE;
1637                    /*  Ugly R5900 special case:  (TODO: move this?)  */
1638                    if (cpu->cd.mips.cpu_type.rev == MIPS_R5900 &&
1639                        !(status & R5900_STATUS_EIE))
1640                            status &= ~STATUS_IE;
1641                    if (status & STATUS_IE && (status & cause & STATUS_IM_MASK)) {
1642                            cpu->pc += sizeof(uint32_t);
1643                            mips_cpu_exception(cpu, EXCEPTION_INT, 0, 0,0,0,0,0);
1644                    }
1645          }          }
 #endif  
1646  }  }
1647  X(dmfc0)  X(dmfc0)
1648  {  {
# Line 1654  X(dmtc0) Line 1661  X(dmtc0)
1661          /*  TODO: cause exception if necessary  */          /*  TODO: cause exception if necessary  */
1662          coproc_register_write(cpu, cpu->cd.mips.coproc[0], rd,          coproc_register_write(cpu, cpu->cd.mips.coproc[0], rd,
1663              (uint64_t *)ic->arg[0], 1, select);              (uint64_t *)ic->arg[0], 1, select);
   
 /*  TODO: fix/remove these!  */  
 cpu->invalidate_translation_caches(cpu, 0, INVALIDATE_ALL);  
1664  }  }
1665    
1666    

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