--- trunk/src/cpus/cpu_mips_coproc.c	2007/10/08 16:19:28	21
+++ trunk/src/cpus/cpu_mips_coproc.c	2007/10/08 16:19:37	22
@@ -25,7 +25,7 @@
  *  SUCH DAMAGE.
  *
  *
- *  $Id: cpu_mips_coproc.c,v 1.8 2005/11/23 02:17:41 debug Exp $
+ *  $Id: cpu_mips_coproc.c,v 1.10 2005/12/26 12:32:10 debug Exp $
  *
  *  Emulation of MIPS coprocessors.
  */
@@ -600,36 +600,37 @@
 	if (writeflag == -1) {
 		/*  Forced downgrade to read-only:  */
 		tbl1->haddr_entry[b*2 + 1] = NULL;
-		if (cpu->cd.mips.host_store ==
+		if (cpu->cd.mips.host_OLD_store ==
 		    cpu->cd.mips.host_store_orig)
-			cpu->cd.mips.host_store[index] = NULL;
+			cpu->cd.mips.host_OLD_store[index] = NULL;
 	} else if (writeflag==0 && p_w != NULL && host_page != NULL) {
 		/*  Don't degrade a page from writable to readonly.  */
 	} else {
 		if (host_page != NULL) {
 			tbl1->haddr_entry[b*2] = host_page;
-			if (cpu->cd.mips.host_load ==
+			if (cpu->cd.mips.host_OLD_load ==
 			    cpu->cd.mips.host_load_orig)
-				cpu->cd.mips.host_load[index] = host_page;
+				cpu->cd.mips.host_OLD_load[index] = host_page;
 			if (writeflag) {
 				tbl1->haddr_entry[b*2+1] = host_page;
-				if (cpu->cd.mips.host_store ==
+				if (cpu->cd.mips.host_OLD_store ==
 				    cpu->cd.mips.host_store_orig)
-					cpu->cd.mips.host_store[index] =
+					cpu->cd.mips.host_OLD_store[index] =
 					    host_page;
 			} else {
 				tbl1->haddr_entry[b*2+1] = NULL;
-				if (cpu->cd.mips.host_store ==
+				if (cpu->cd.mips.host_OLD_store ==
 				    cpu->cd.mips.host_store_orig)
-					cpu->cd.mips.host_store[index] = NULL;
+					cpu->cd.mips.host_OLD_store[index] =
+					    NULL;
 			}
 		} else {
 			tbl1->haddr_entry[b*2] = NULL;
 			tbl1->haddr_entry[b*2+1] = NULL;
-			if (cpu->cd.mips.host_store ==
+			if (cpu->cd.mips.host_OLD_store ==
 			    cpu->cd.mips.host_store_orig) {
-				cpu->cd.mips.host_load[index] = NULL;
-				cpu->cd.mips.host_store[index] = NULL;
+				cpu->cd.mips.host_OLD_load[index] = NULL;
+				cpu->cd.mips.host_OLD_store[index] = NULL;
 			}
 		}
 		tbl1->paddr_entry[b] = paddr_page;
@@ -639,9 +640,9 @@
 
 
 /*
- *  mips_update_translation_table():
+ *  mips_OLD_update_translation_table():
  */
-void mips_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
+void mips_OLD_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
 	unsigned char *host_page, int writeflag, uint64_t paddr_page)
 {
 	if (!cpu->machine->bintrans_enable)
@@ -748,11 +749,13 @@
 				tbl1->paddr_entry[b] = 0;
 				tbl1->bintrans_chunks[b] = NULL;
 
-				if (cpu->cd.mips.host_store ==
+				if (cpu->cd.mips.host_OLD_store ==
 				    cpu->cd.mips.host_store_orig) {
 					index = (a << 10) + b;
-					cpu->cd.mips.host_load[index] = NULL;
-					cpu->cd.mips.host_store[index] = NULL;
+					cpu->cd.mips.host_OLD_load[index] =
+					    NULL;
+					cpu->cd.mips.host_OLD_store[index] =
+					    NULL;
 				}
 			}
 		}
@@ -1191,7 +1194,7 @@
 			unimpl = 0;
 			break;
 		case COP0_COUNT:
-			if (tmp != (int64_t)(int32_t)tmp)
+			if (tmp != (uint64_t)(int64_t)(int32_t)tmp)
 				fatal("WARNING: trying to write a 64-bit value"
 				    " to the COUNT register!\n");
 			tmp = (int64_t)(int32_t)tmp;
@@ -1201,7 +1204,7 @@
 			/*  Clear the timer interrupt bit (bit 7):  */
 			cpu->cd.mips.compare_register_set = 1;
 			mips_cpu_interrupt_ack(cpu, 7);
-			if (tmp != (int64_t)(int32_t)tmp)
+			if (tmp != (uint64_t)(int64_t)(int32_t)tmp)
 				fatal("WARNING: trying to write a 64-bit value"
 				    " to the COMPARE register!\n");
 			tmp = (int64_t)(int32_t)tmp;
@@ -1306,7 +1309,7 @@
 #endif
 
 			if (cpu->cd.mips.cpu_type.mmu_model == MMU3K &&
-			    (oldmode & MIPS1_ISOL_CACHES) !=
+			    ((uint32_t)oldmode & MIPS1_ISOL_CACHES) !=
 			    (tmp & MIPS1_ISOL_CACHES)) {
 				/*  R3000-style caches when isolated are
 				    treated in bintrans mode by changing
@@ -1321,8 +1324,8 @@
 					  vaddr_to_hostaddr_table0_cacheisol_d;
 
 					/*  1M-entry table:  */
-					cpu->cd.mips.host_load =
-					    cpu->cd.mips.host_store =
+					cpu->cd.mips.host_OLD_load =
+					    cpu->cd.mips.host_OLD_store =
 					    cpu->cd.mips.huge_r2k3k_cache_table;
 				} else {
 					/*  2-level table:  */
@@ -1334,9 +1337,9 @@
 					    vaddr_to_hostaddr_table0_user;  */
 
 					/*  1M-entry table:  */
-					cpu->cd.mips.host_load =
+					cpu->cd.mips.host_OLD_load =
 					    cpu->cd.mips.host_load_orig;
-					cpu->cd.mips.host_store =
+					cpu->cd.mips.host_OLD_store =
 					    cpu->cd.mips.host_store_orig;
 				}
 			}
@@ -2163,7 +2166,8 @@
 	if (cpu->cd.mips.cpu_type.mmu_model != MMU3K &&
 	    cpu->cd.mips.cpu_type.rev != MIPS_R4100) {
 		uint64_t vaddr1, vaddr2;
-		int i, asid;
+		int i;
+		unsigned int asid;
 
 		vaddr1 = cp->reg[COP0_ENTRYHI] & ENTRYHI_VPN2_MASK_R10K;
 		asid = cp->reg[COP0_ENTRYHI] & ENTRYHI_ASID;