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/* |
/* |
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* Copyright (C) 2003-2006 Anders Gavare. All rights reserved. |
* Copyright (C) 2003-2007 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: cpu_mips_coproc.c,v 1.60 2006/10/14 23:47:37 debug Exp $ |
* $Id: cpu_mips_coproc.c,v 1.62 2007/02/03 16:18:56 debug Exp $ |
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* |
* |
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* Emulation of MIPS coprocessors. |
* Emulation of MIPS coprocessors. |
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*/ |
*/ |
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cpu->cd.mips.compare_interrupts_pending --; |
cpu->cd.mips.compare_interrupts_pending --; |
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|
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/* Clear the timer interrupt assertion (bit 7): */ |
/* Clear the timer interrupt assertion (bit 7): */ |
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mips_cpu_interrupt_ack(cpu, 7); |
cp->reg[COP0_CAUSE] &= ~0x8000; |
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if (tmp != (uint64_t)(int64_t)(int32_t)tmp) |
if (tmp != (uint64_t)(int64_t)(int32_t)tmp) |
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fatal("WARNING: trying to write a 64-bit value" |
fatal("WARNING: trying to write a 64-bit value" |