25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: cpu_mips_coproc.c,v 1.53 2006/08/11 17:43:30 debug Exp $ |
* $Id: cpu_mips_coproc.c,v 1.60 2006/10/14 23:47:37 debug Exp $ |
29 |
* |
* |
30 |
* Emulation of MIPS coprocessors. |
* Emulation of MIPS coprocessors. |
31 |
*/ |
*/ |
45 |
#include "mips_cpu_types.h" |
#include "mips_cpu_types.h" |
46 |
#include "misc.h" |
#include "misc.h" |
47 |
#include "opcodes_mips.h" |
#include "opcodes_mips.h" |
48 |
|
#include "timer.h" |
49 |
|
|
50 |
|
|
51 |
#ifndef ENABLE_MIPS |
#ifndef ENABLE_MIPS |
439 |
|
|
440 |
|
|
441 |
/* |
/* |
442 |
|
* mips_timer_tick(): |
443 |
|
*/ |
444 |
|
static void mips_timer_tick(struct timer *timer, void *extra) |
445 |
|
{ |
446 |
|
struct cpu *cpu = (struct cpu *) extra; |
447 |
|
|
448 |
|
cpu->cd.mips.compare_interrupts_pending ++; |
449 |
|
|
450 |
|
if ((int32_t) (cpu->cd.mips.coproc[0]->reg[COP0_COUNT] - |
451 |
|
cpu->cd.mips.coproc[0]->reg[COP0_COMPARE]) < 0) { |
452 |
|
cpu->cd.mips.coproc[0]->reg[COP0_COUNT] = |
453 |
|
cpu->cd.mips.coproc[0]->reg[COP0_COMPARE]; |
454 |
|
} |
455 |
|
} |
456 |
|
|
457 |
|
|
458 |
|
/* |
459 |
* mips_coproc_tlb_set_entry(): |
* mips_coproc_tlb_set_entry(): |
460 |
* |
* |
461 |
* Used by machine setup code, if a specific machine emulation starts up |
* Used by machine setup code, if a specific machine emulation starts up |
613 |
if (cp->coproc_nr==0 && reg_nr==COP0_PAGEMASK) unimpl = 0; |
if (cp->coproc_nr==0 && reg_nr==COP0_PAGEMASK) unimpl = 0; |
614 |
if (cp->coproc_nr==0 && reg_nr==COP0_WIRED) unimpl = 0; |
if (cp->coproc_nr==0 && reg_nr==COP0_WIRED) unimpl = 0; |
615 |
if (cp->coproc_nr==0 && reg_nr==COP0_BADVADDR) unimpl = 0; |
if (cp->coproc_nr==0 && reg_nr==COP0_BADVADDR) unimpl = 0; |
616 |
if (cp->coproc_nr==0 && reg_nr==COP0_COUNT) unimpl = 0; |
if (cp->coproc_nr==0 && reg_nr==COP0_COUNT) { |
617 |
|
/* TODO: Increase count in a more meaningful way! */ |
618 |
|
cp->reg[COP0_COUNT] = (int32_t) (cp->reg[COP0_COUNT] + 1); |
619 |
|
unimpl = 0; |
620 |
|
} |
621 |
if (cp->coproc_nr==0 && reg_nr==COP0_ENTRYHI) unimpl = 0; |
if (cp->coproc_nr==0 && reg_nr==COP0_ENTRYHI) unimpl = 0; |
622 |
if (cp->coproc_nr==0 && reg_nr==COP0_COMPARE) unimpl = 0; |
if (cp->coproc_nr==0 && reg_nr==COP0_COMPARE) unimpl = 0; |
623 |
if (cp->coproc_nr==0 && reg_nr==COP0_STATUS) unimpl = 0; |
if (cp->coproc_nr==0 && reg_nr==COP0_STATUS) unimpl = 0; |
775 |
unimpl = 0; |
unimpl = 0; |
776 |
break; |
break; |
777 |
case COP0_COMPARE: |
case COP0_COMPARE: |
778 |
/* Clear the timer interrupt bit (bit 7): */ |
if (cpu->machine->emulated_hz > 0) { |
779 |
cpu->cd.mips.compare_register_set = 1; |
int32_t compare_diff = tmp - |
780 |
|
cp->reg[COP0_COMPARE]; |
781 |
|
double hz; |
782 |
|
|
783 |
|
if (compare_diff < 0) |
784 |
|
hz = tmp - cp->reg[COP0_COUNT]; |
785 |
|
|
786 |
|
if (compare_diff == 0) |
787 |
|
hz = 0; |
788 |
|
else |
789 |
|
hz = (double)cpu->machine->emulated_hz |
790 |
|
/ (double)compare_diff; |
791 |
|
/* |
792 |
|
* TODO: DON'T HARDCODE THIS! |
793 |
|
*/ |
794 |
|
hz = 100.0; |
795 |
|
|
796 |
|
/* Initialize or re-set the periodic timer: */ |
797 |
|
if (hz > 0) { |
798 |
|
if (cpu->cd.mips.timer == NULL) |
799 |
|
cpu->cd.mips.timer = timer_add( |
800 |
|
hz, mips_timer_tick, cpu); |
801 |
|
else |
802 |
|
timer_update_frequency( |
803 |
|
cpu->cd.mips.timer, hz); |
804 |
|
} |
805 |
|
} |
806 |
|
|
807 |
|
/* Ack the periodic timer, if it was asserted: */ |
808 |
|
if (cp->reg[COP0_CAUSE] & 0x8000 && |
809 |
|
cpu->cd.mips.compare_interrupts_pending > 0) |
810 |
|
cpu->cd.mips.compare_interrupts_pending --; |
811 |
|
|
812 |
|
/* Clear the timer interrupt assertion (bit 7): */ |
813 |
mips_cpu_interrupt_ack(cpu, 7); |
mips_cpu_interrupt_ack(cpu, 7); |
814 |
|
|
815 |
if (tmp != (uint64_t)(int64_t)(int32_t)tmp) |
if (tmp != (uint64_t)(int64_t)(int32_t)tmp) |
816 |
fatal("WARNING: trying to write a 64-bit value" |
fatal("WARNING: trying to write a 64-bit value" |
817 |
" to the COMPARE register!\n"); |
" to the COMPARE register!\n"); |
818 |
|
|
819 |
tmp = (int64_t)(int32_t)tmp; |
tmp = (int64_t)(int32_t)tmp; |
820 |
|
cpu->cd.mips.compare_register_set = 1; |
821 |
unimpl = 0; |
unimpl = 0; |
822 |
break; |
break; |
823 |
case COP0_ENTRYHI: |
case COP0_ENTRYHI: |
1680 |
(cp->reg[COP0_ENTRYHI] & R2K3K_ENTRYHI_ASID_MASK) )) |
(cp->reg[COP0_ENTRYHI] & R2K3K_ENTRYHI_ASID_MASK) )) |
1681 |
cpu->invalidate_translation_caches(cpu, oldvaddr, |
cpu->invalidate_translation_caches(cpu, oldvaddr, |
1682 |
INVALIDATE_VADDR); |
INVALIDATE_VADDR); |
1683 |
|
|
1684 |
break; |
break; |
1685 |
|
|
1686 |
default:if (cpu->cd.mips.cpu_type.mmu_model == MMU10K) { |
default:if (cpu->cd.mips.cpu_type.mmu_model == MMU10K) { |
1687 |
oldvaddr = cp->tlbs[index].hi & ENTRYHI_VPN2_MASK_R10K; |
oldvaddr = cp->tlbs[index].hi & |
1688 |
|
(ENTRYHI_VPN2_MASK_R10K | ENTRYHI_R_MASK); |
1689 |
/* 44 addressable bits: */ |
/* 44 addressable bits: */ |
1690 |
if (oldvaddr & 0x80000000000ULL) |
if (oldvaddr & 0x80000000000ULL) |
1691 |
oldvaddr |= 0xfffff00000000000ULL; |
oldvaddr |= 0x3ffff00000000000ULL; |
1692 |
} else if (cpu->is_32bit) { |
} else if (cpu->is_32bit) { |
1693 |
/* MIPS32 etc.: */ |
/* MIPS32 etc.: */ |
1694 |
oldvaddr = cp->tlbs[index].hi & ENTRYHI_VPN2_MASK; |
oldvaddr = cp->tlbs[index].hi & ENTRYHI_VPN2_MASK; |
1695 |
oldvaddr = (int32_t)oldvaddr; |
oldvaddr = (int32_t)oldvaddr; |
1696 |
} else { |
} else { |
1697 |
/* Assume MMU4K */ |
/* Assume MMU4K */ |
1698 |
oldvaddr = cp->tlbs[index].hi & ENTRYHI_VPN2_MASK; |
oldvaddr = cp->tlbs[index].hi & |
1699 |
|
(ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK); |
1700 |
/* 40 addressable bits: */ |
/* 40 addressable bits: */ |
1701 |
if (oldvaddr & 0x8000000000ULL) |
if (oldvaddr & 0x8000000000ULL) |
1702 |
oldvaddr |= 0xffffff0000000000ULL; |
oldvaddr |= 0x3fffff0000000000ULL; |
1703 |
} |
} |
1704 |
|
|
|
#if 0 |
|
|
/* TODO: FIX THIS! It shouldn't be needed! */ |
|
|
cpu->invalidate_translation_caches(cpu, 0, INVALIDATE_ALL); |
|
|
#else |
|
1705 |
/* |
/* |
1706 |
* TODO: non-4KB page sizes! |
* TODO: non-4KB page sizes! |
1707 |
*/ |
*/ |
1711 |
if (cp->tlbs[index].lo1 & ENTRYLO_V) |
if (cp->tlbs[index].lo1 & ENTRYLO_V) |
1712 |
cpu->invalidate_translation_caches(cpu, oldvaddr|0x1000, |
cpu->invalidate_translation_caches(cpu, oldvaddr|0x1000, |
1713 |
INVALIDATE_VADDR); |
INVALIDATE_VADDR); |
|
#endif |
|
1714 |
} |
} |
1715 |
|
|
1716 |
#if 0 |
#if 0 |
1728 |
int i; |
int i; |
1729 |
unsigned int asid; |
unsigned int asid; |
1730 |
|
|
1731 |
vaddr1 = cp->reg[COP0_ENTRYHI] & ENTRYHI_VPN2_MASK_R10K; |
vaddr1 = cp->reg[COP0_ENTRYHI] & |
1732 |
|
(ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK_R10K); |
1733 |
asid = cp->reg[COP0_ENTRYHI] & ENTRYHI_ASID; |
asid = cp->reg[COP0_ENTRYHI] & ENTRYHI_ASID; |
1734 |
/* Since this is just a warning, it's probably not necessary |
/* Since this is just a warning, it's probably not necessary |
1735 |
to use R4000 masks etc. */ |
to use R4000 masks etc. */ |
1742 |
(cp->tlbs[i].hi & ENTRYHI_ASID) != asid) |
(cp->tlbs[i].hi & ENTRYHI_ASID) != asid) |
1743 |
continue; |
continue; |
1744 |
|
|
1745 |
vaddr2 = cp->tlbs[i].hi & ENTRYHI_VPN2_MASK_R10K; |
vaddr2 = cp->tlbs[i].hi & |
1746 |
|
(ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK_R10K); |
1747 |
if (vaddr1 == vaddr2 && ((cp->tlbs[i].lo0 & |
if (vaddr1 == vaddr2 && ((cp->tlbs[i].lo0 & |
1748 |
ENTRYLO_V) || (cp->tlbs[i].lo1 & ENTRYLO_V))) |
ENTRYLO_V) || (cp->tlbs[i].lo1 & ENTRYLO_V))) |
1749 |
fatal("\n[ WARNING! tlbw%s to index 0x%02x " |
fatal("\n[ WARNING! tlbw%s to index 0x%02x " |
1777 |
INVALIDATE_PADDR); |
INVALIDATE_PADDR); |
1778 |
} |
} |
1779 |
|
|
1780 |
|
/* Set new last_written_tlb_index hint: */ |
1781 |
|
cpu->cd.mips.last_written_tlb_index = index; |
1782 |
|
|
1783 |
if (cp->reg[COP0_STATUS] & MIPS1_ISOL_CACHES) { |
if (cp->reg[COP0_STATUS] & MIPS1_ISOL_CACHES) { |
1784 |
fatal("Wow! Interesting case; tlbw* while caches" |
fatal("Wow! Interesting case; tlbw* while caches" |
1785 |
" are isolated. TODO\n"); |
" are isolated. TODO\n"); |
1843 |
>> ENTRYLO_PFN_SHIFT) << pfn_shift; |
>> ENTRYLO_PFN_SHIFT) << pfn_shift; |
1844 |
|
|
1845 |
if (cpu->cd.mips.cpu_type.mmu_model == MMU10K) { |
if (cpu->cd.mips.cpu_type.mmu_model == MMU10K) { |
1846 |
vaddr0 = cp->tlbs[index].hi & ENTRYHI_VPN2_MASK_R10K; |
vaddr0 = cp->tlbs[index].hi & |
1847 |
|
(ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK_R10K); |
1848 |
/* 44 addressable bits: */ |
/* 44 addressable bits: */ |
1849 |
if (vaddr0 & 0x80000000000ULL) |
if (vaddr0 & 0x80000000000ULL) |
1850 |
vaddr0 |= 0xfffff00000000000ULL; |
vaddr0 |= 0x3ffff00000000000ULL; |
1851 |
} else if (cpu->is_32bit) { |
} else if (cpu->is_32bit) { |
1852 |
/* MIPS32 etc.: */ |
/* MIPS32 etc.: */ |
1853 |
vaddr0 = cp->tlbs[index].hi & ENTRYHI_VPN2_MASK; |
vaddr0 = cp->tlbs[index].hi & ENTRYHI_VPN2_MASK; |
1854 |
vaddr0 = (int32_t)vaddr0; |
vaddr0 = (int32_t)vaddr0; |
1855 |
} else { |
} else { |
1856 |
/* Assume MMU4K */ |
/* Assume MMU4K */ |
1857 |
vaddr0 = cp->tlbs[index].hi & ENTRYHI_VPN2_MASK; |
vaddr0 = cp->tlbs[index].hi & |
1858 |
|
(ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK); |
1859 |
/* 40 addressable bits: */ |
/* 40 addressable bits: */ |
1860 |
if (vaddr0 & 0x8000000000ULL) |
if (vaddr0 & 0x8000000000ULL) |
1861 |
vaddr0 |= 0xffffff0000000000ULL; |
vaddr0 |= 0x3fffff0000000000ULL; |
1862 |
} |
} |
1863 |
|
|
1864 |
vaddr1 = vaddr0 | (1 << vpn_shift); |
vaddr1 = vaddr0 | (1 << vpn_shift); |
1910 |
if (memblock != NULL && cp->reg[COP0_ENTRYLO1] & ENTRYLO_V) |
if (memblock != NULL && cp->reg[COP0_ENTRYLO1] & ENTRYLO_V) |
1911 |
cpu->update_translation_table(cpu, vaddr1, memblock, |
cpu->update_translation_table(cpu, vaddr1, memblock, |
1912 |
wf1, paddr1); |
wf1, paddr1); |
1913 |
|
|
1914 |
|
/* Set new last_written_tlb_index hint: */ |
1915 |
|
cpu->cd.mips.last_written_tlb_index = index; |
1916 |
} |
} |
1917 |
} |
} |
1918 |
|
|