25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: cpu_mips_coproc.c,v 1.8 2005/11/23 02:17:41 debug Exp $ |
* $Id: cpu_mips_coproc.c,v 1.10 2005/12/26 12:32:10 debug Exp $ |
29 |
* |
* |
30 |
* Emulation of MIPS coprocessors. |
* Emulation of MIPS coprocessors. |
31 |
*/ |
*/ |
600 |
if (writeflag == -1) { |
if (writeflag == -1) { |
601 |
/* Forced downgrade to read-only: */ |
/* Forced downgrade to read-only: */ |
602 |
tbl1->haddr_entry[b*2 + 1] = NULL; |
tbl1->haddr_entry[b*2 + 1] = NULL; |
603 |
if (cpu->cd.mips.host_store == |
if (cpu->cd.mips.host_OLD_store == |
604 |
cpu->cd.mips.host_store_orig) |
cpu->cd.mips.host_store_orig) |
605 |
cpu->cd.mips.host_store[index] = NULL; |
cpu->cd.mips.host_OLD_store[index] = NULL; |
606 |
} else if (writeflag==0 && p_w != NULL && host_page != NULL) { |
} else if (writeflag==0 && p_w != NULL && host_page != NULL) { |
607 |
/* Don't degrade a page from writable to readonly. */ |
/* Don't degrade a page from writable to readonly. */ |
608 |
} else { |
} else { |
609 |
if (host_page != NULL) { |
if (host_page != NULL) { |
610 |
tbl1->haddr_entry[b*2] = host_page; |
tbl1->haddr_entry[b*2] = host_page; |
611 |
if (cpu->cd.mips.host_load == |
if (cpu->cd.mips.host_OLD_load == |
612 |
cpu->cd.mips.host_load_orig) |
cpu->cd.mips.host_load_orig) |
613 |
cpu->cd.mips.host_load[index] = host_page; |
cpu->cd.mips.host_OLD_load[index] = host_page; |
614 |
if (writeflag) { |
if (writeflag) { |
615 |
tbl1->haddr_entry[b*2+1] = host_page; |
tbl1->haddr_entry[b*2+1] = host_page; |
616 |
if (cpu->cd.mips.host_store == |
if (cpu->cd.mips.host_OLD_store == |
617 |
cpu->cd.mips.host_store_orig) |
cpu->cd.mips.host_store_orig) |
618 |
cpu->cd.mips.host_store[index] = |
cpu->cd.mips.host_OLD_store[index] = |
619 |
host_page; |
host_page; |
620 |
} else { |
} else { |
621 |
tbl1->haddr_entry[b*2+1] = NULL; |
tbl1->haddr_entry[b*2+1] = NULL; |
622 |
if (cpu->cd.mips.host_store == |
if (cpu->cd.mips.host_OLD_store == |
623 |
cpu->cd.mips.host_store_orig) |
cpu->cd.mips.host_store_orig) |
624 |
cpu->cd.mips.host_store[index] = NULL; |
cpu->cd.mips.host_OLD_store[index] = |
625 |
|
NULL; |
626 |
} |
} |
627 |
} else { |
} else { |
628 |
tbl1->haddr_entry[b*2] = NULL; |
tbl1->haddr_entry[b*2] = NULL; |
629 |
tbl1->haddr_entry[b*2+1] = NULL; |
tbl1->haddr_entry[b*2+1] = NULL; |
630 |
if (cpu->cd.mips.host_store == |
if (cpu->cd.mips.host_OLD_store == |
631 |
cpu->cd.mips.host_store_orig) { |
cpu->cd.mips.host_store_orig) { |
632 |
cpu->cd.mips.host_load[index] = NULL; |
cpu->cd.mips.host_OLD_load[index] = NULL; |
633 |
cpu->cd.mips.host_store[index] = NULL; |
cpu->cd.mips.host_OLD_store[index] = NULL; |
634 |
} |
} |
635 |
} |
} |
636 |
tbl1->paddr_entry[b] = paddr_page; |
tbl1->paddr_entry[b] = paddr_page; |
640 |
|
|
641 |
|
|
642 |
/* |
/* |
643 |
* mips_update_translation_table(): |
* mips_OLD_update_translation_table(): |
644 |
*/ |
*/ |
645 |
void mips_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
void mips_OLD_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
646 |
unsigned char *host_page, int writeflag, uint64_t paddr_page) |
unsigned char *host_page, int writeflag, uint64_t paddr_page) |
647 |
{ |
{ |
648 |
if (!cpu->machine->bintrans_enable) |
if (!cpu->machine->bintrans_enable) |
749 |
tbl1->paddr_entry[b] = 0; |
tbl1->paddr_entry[b] = 0; |
750 |
tbl1->bintrans_chunks[b] = NULL; |
tbl1->bintrans_chunks[b] = NULL; |
751 |
|
|
752 |
if (cpu->cd.mips.host_store == |
if (cpu->cd.mips.host_OLD_store == |
753 |
cpu->cd.mips.host_store_orig) { |
cpu->cd.mips.host_store_orig) { |
754 |
index = (a << 10) + b; |
index = (a << 10) + b; |
755 |
cpu->cd.mips.host_load[index] = NULL; |
cpu->cd.mips.host_OLD_load[index] = |
756 |
cpu->cd.mips.host_store[index] = NULL; |
NULL; |
757 |
|
cpu->cd.mips.host_OLD_store[index] = |
758 |
|
NULL; |
759 |
} |
} |
760 |
} |
} |
761 |
} |
} |
1194 |
unimpl = 0; |
unimpl = 0; |
1195 |
break; |
break; |
1196 |
case COP0_COUNT: |
case COP0_COUNT: |
1197 |
if (tmp != (int64_t)(int32_t)tmp) |
if (tmp != (uint64_t)(int64_t)(int32_t)tmp) |
1198 |
fatal("WARNING: trying to write a 64-bit value" |
fatal("WARNING: trying to write a 64-bit value" |
1199 |
" to the COUNT register!\n"); |
" to the COUNT register!\n"); |
1200 |
tmp = (int64_t)(int32_t)tmp; |
tmp = (int64_t)(int32_t)tmp; |
1204 |
/* Clear the timer interrupt bit (bit 7): */ |
/* Clear the timer interrupt bit (bit 7): */ |
1205 |
cpu->cd.mips.compare_register_set = 1; |
cpu->cd.mips.compare_register_set = 1; |
1206 |
mips_cpu_interrupt_ack(cpu, 7); |
mips_cpu_interrupt_ack(cpu, 7); |
1207 |
if (tmp != (int64_t)(int32_t)tmp) |
if (tmp != (uint64_t)(int64_t)(int32_t)tmp) |
1208 |
fatal("WARNING: trying to write a 64-bit value" |
fatal("WARNING: trying to write a 64-bit value" |
1209 |
" to the COMPARE register!\n"); |
" to the COMPARE register!\n"); |
1210 |
tmp = (int64_t)(int32_t)tmp; |
tmp = (int64_t)(int32_t)tmp; |
1309 |
#endif |
#endif |
1310 |
|
|
1311 |
if (cpu->cd.mips.cpu_type.mmu_model == MMU3K && |
if (cpu->cd.mips.cpu_type.mmu_model == MMU3K && |
1312 |
(oldmode & MIPS1_ISOL_CACHES) != |
((uint32_t)oldmode & MIPS1_ISOL_CACHES) != |
1313 |
(tmp & MIPS1_ISOL_CACHES)) { |
(tmp & MIPS1_ISOL_CACHES)) { |
1314 |
/* R3000-style caches when isolated are |
/* R3000-style caches when isolated are |
1315 |
treated in bintrans mode by changing |
treated in bintrans mode by changing |
1324 |
vaddr_to_hostaddr_table0_cacheisol_d; |
vaddr_to_hostaddr_table0_cacheisol_d; |
1325 |
|
|
1326 |
/* 1M-entry table: */ |
/* 1M-entry table: */ |
1327 |
cpu->cd.mips.host_load = |
cpu->cd.mips.host_OLD_load = |
1328 |
cpu->cd.mips.host_store = |
cpu->cd.mips.host_OLD_store = |
1329 |
cpu->cd.mips.huge_r2k3k_cache_table; |
cpu->cd.mips.huge_r2k3k_cache_table; |
1330 |
} else { |
} else { |
1331 |
/* 2-level table: */ |
/* 2-level table: */ |
1337 |
vaddr_to_hostaddr_table0_user; */ |
vaddr_to_hostaddr_table0_user; */ |
1338 |
|
|
1339 |
/* 1M-entry table: */ |
/* 1M-entry table: */ |
1340 |
cpu->cd.mips.host_load = |
cpu->cd.mips.host_OLD_load = |
1341 |
cpu->cd.mips.host_load_orig; |
cpu->cd.mips.host_load_orig; |
1342 |
cpu->cd.mips.host_store = |
cpu->cd.mips.host_OLD_store = |
1343 |
cpu->cd.mips.host_store_orig; |
cpu->cd.mips.host_store_orig; |
1344 |
} |
} |
1345 |
} |
} |
2166 |
if (cpu->cd.mips.cpu_type.mmu_model != MMU3K && |
if (cpu->cd.mips.cpu_type.mmu_model != MMU3K && |
2167 |
cpu->cd.mips.cpu_type.rev != MIPS_R4100) { |
cpu->cd.mips.cpu_type.rev != MIPS_R4100) { |
2168 |
uint64_t vaddr1, vaddr2; |
uint64_t vaddr1, vaddr2; |
2169 |
int i, asid; |
int i; |
2170 |
|
unsigned int asid; |
2171 |
|
|
2172 |
vaddr1 = cp->reg[COP0_ENTRYHI] & ENTRYHI_VPN2_MASK_R10K; |
vaddr1 = cp->reg[COP0_ENTRYHI] & ENTRYHI_VPN2_MASK_R10K; |
2173 |
asid = cp->reg[COP0_ENTRYHI] & ENTRYHI_ASID; |
asid = cp->reg[COP0_ENTRYHI] & ENTRYHI_ASID; |