25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: cpu_mips.c,v 1.79 2007/04/28 09:19:51 debug Exp $ |
* $Id: cpu_mips.c,v 1.84 2007/06/28 13:36:46 debug Exp $ |
29 |
* |
* |
30 |
* MIPS core CPU emulation. |
* MIPS core CPU emulation. |
31 |
*/ |
*/ |
54 |
#include "symbol.h" |
#include "symbol.h" |
55 |
|
|
56 |
|
|
|
extern volatile int single_step; |
|
|
|
|
57 |
static char *exception_names[] = EXCEPTION_NAMES; |
static char *exception_names[] = EXCEPTION_NAMES; |
58 |
|
|
59 |
static char *hi6_names[] = HI6_NAMES; |
static char *hi6_names[] = HI6_NAMES; |
81 |
|
|
82 |
|
|
83 |
/* |
/* |
|
* regname(): |
|
|
* |
|
|
* Convert a register number into either 'r0', 'r31' etc, or a symbolic |
|
|
* name, depending on machine->show_symbolic_register_names. |
|
|
* |
|
|
* NOTE: This helper function is _NOT_ reentrant. |
|
|
*/ |
|
|
static char *regname(struct machine *machine, int r) |
|
|
{ |
|
|
static char ch[4]; |
|
|
ch[3] = ch[2] = '\0'; |
|
|
|
|
|
if (r<0 || r>=32) |
|
|
strlcpy(ch, "xx", sizeof(ch)); |
|
|
else if (machine->show_symbolic_register_names) |
|
|
strlcpy(ch, regnames[r], sizeof(ch)); |
|
|
else |
|
|
snprintf(ch, sizeof(ch), "r%i", r); |
|
|
|
|
|
return ch; |
|
|
} |
|
|
|
|
|
|
|
|
/* |
|
84 |
* mips_cpu_new(): |
* mips_cpu_new(): |
85 |
* |
* |
86 |
* Create a new MIPS cpu object. |
* Create a new MIPS cpu object. |
156 |
x = DEFAULT_PCACHE_SIZE; |
x = DEFAULT_PCACHE_SIZE; |
157 |
if (cpu->cd.mips.cpu_type.pdcache) |
if (cpu->cd.mips.cpu_type.pdcache) |
158 |
x = cpu->cd.mips.cpu_type.pdcache; |
x = cpu->cd.mips.cpu_type.pdcache; |
159 |
if (machine->cache_pdcache == 0) |
if (cpu->cd.mips.cache_pdcache == 0) |
160 |
machine->cache_pdcache = x; |
cpu->cd.mips.cache_pdcache = x; |
161 |
|
|
162 |
x = DEFAULT_PCACHE_SIZE; |
x = DEFAULT_PCACHE_SIZE; |
163 |
if (cpu->cd.mips.cpu_type.picache) |
if (cpu->cd.mips.cpu_type.picache) |
164 |
x = cpu->cd.mips.cpu_type.picache; |
x = cpu->cd.mips.cpu_type.picache; |
165 |
if (machine->cache_picache == 0) |
if (cpu->cd.mips.cache_picache == 0) |
166 |
machine->cache_picache = x; |
cpu->cd.mips.cache_picache = x; |
167 |
|
|
168 |
if (machine->cache_secondary == 0) |
if (cpu->cd.mips.cache_secondary == 0) |
169 |
machine->cache_secondary = cpu->cd.mips.cpu_type.scache; |
cpu->cd.mips.cache_secondary = cpu->cd.mips.cpu_type.scache; |
170 |
|
|
171 |
linesize = DEFAULT_PCACHE_LINESIZE; |
linesize = DEFAULT_PCACHE_LINESIZE; |
172 |
if (cpu->cd.mips.cpu_type.pdlinesize) |
if (cpu->cd.mips.cpu_type.pdlinesize) |
173 |
linesize = cpu->cd.mips.cpu_type.pdlinesize; |
linesize = cpu->cd.mips.cpu_type.pdlinesize; |
174 |
if (machine->cache_pdcache_linesize == 0) |
if (cpu->cd.mips.cache_pdcache_linesize == 0) |
175 |
machine->cache_pdcache_linesize = linesize; |
cpu->cd.mips.cache_pdcache_linesize = linesize; |
176 |
|
|
177 |
linesize = DEFAULT_PCACHE_LINESIZE; |
linesize = DEFAULT_PCACHE_LINESIZE; |
178 |
if (cpu->cd.mips.cpu_type.pilinesize) |
if (cpu->cd.mips.cpu_type.pilinesize) |
179 |
linesize = cpu->cd.mips.cpu_type.pilinesize; |
linesize = cpu->cd.mips.cpu_type.pilinesize; |
180 |
if (machine->cache_picache_linesize == 0) |
if (cpu->cd.mips.cache_picache_linesize == 0) |
181 |
machine->cache_picache_linesize = linesize; |
cpu->cd.mips.cache_picache_linesize = linesize; |
182 |
|
|
183 |
linesize = 0; |
linesize = 0; |
184 |
if (cpu->cd.mips.cpu_type.slinesize) |
if (cpu->cd.mips.cpu_type.slinesize) |
185 |
linesize = cpu->cd.mips.cpu_type.slinesize; |
linesize = cpu->cd.mips.cpu_type.slinesize; |
186 |
if (machine->cache_secondary_linesize == 0) |
if (cpu->cd.mips.cache_secondary_linesize == 0) |
187 |
machine->cache_secondary_linesize = linesize; |
cpu->cd.mips.cache_secondary_linesize = linesize; |
188 |
|
|
189 |
|
|
190 |
/* |
/* |
193 |
for (i=CACHE_DATA; i<=CACHE_INSTRUCTION; i++) { |
for (i=CACHE_DATA; i<=CACHE_INSTRUCTION; i++) { |
194 |
switch (i) { |
switch (i) { |
195 |
case CACHE_DATA: |
case CACHE_DATA: |
196 |
x = 1 << machine->cache_pdcache; |
x = 1 << cpu->cd.mips.cache_pdcache; |
197 |
linesize = 1 << machine->cache_pdcache_linesize; |
linesize = 1 << cpu->cd.mips.cache_pdcache_linesize; |
198 |
break; |
break; |
199 |
case CACHE_INSTRUCTION: |
case CACHE_INSTRUCTION: |
200 |
x = 1 << machine->cache_picache; |
x = 1 << cpu->cd.mips.cache_picache; |
201 |
linesize = 1 << machine->cache_picache_linesize; |
linesize = 1 << cpu->cd.mips.cache_picache_linesize; |
202 |
break; |
break; |
203 |
} |
} |
204 |
|
|
212 |
size_per_cache_line = sizeof(struct r3000_cache_line); |
size_per_cache_line = sizeof(struct r3000_cache_line); |
213 |
break; |
break; |
214 |
default: |
default: |
215 |
size_per_cache_line = sizeof(struct r4000_cache_line); |
size_per_cache_line = 32; /* TODO */ |
216 |
} |
} |
217 |
|
|
218 |
cpu->cd.mips.cache_mask[i] = cpu->cd.mips.cache_size[i] - 1; |
cpu->cd.mips.cache_mask[i] = cpu->cd.mips.cache_size[i] - 1; |
|
cpu->cd.mips.cache_miss_penalty[i] = 10; /* TODO ? */ |
|
219 |
|
|
220 |
cpu->cd.mips.cache[i] = malloc(cpu->cd.mips.cache_size[i]); |
CHECK_ALLOCATION(cpu->cd.mips.cache[i] = |
221 |
if (cpu->cd.mips.cache[i] == NULL) { |
malloc(cpu->cd.mips.cache_size[i])); |
|
fprintf(stderr, "out of memory\n"); |
|
|
} |
|
222 |
|
|
223 |
n_cache_lines = cpu->cd.mips.cache_size[i] / |
n_cache_lines = cpu->cd.mips.cache_size[i] / |
224 |
cpu->cd.mips.cache_linesize[i]; |
cpu->cd.mips.cache_linesize[i]; |
225 |
tags_size = n_cache_lines * size_per_cache_line; |
tags_size = n_cache_lines * size_per_cache_line; |
226 |
|
|
227 |
cpu->cd.mips.cache_tags[i] = malloc(tags_size); |
CHECK_ALLOCATION(cpu->cd.mips.cache_tags[i] = |
228 |
if (cpu->cd.mips.cache_tags[i] == NULL) { |
malloc(tags_size)); |
|
fprintf(stderr, "out of memory\n"); |
|
|
} |
|
229 |
|
|
230 |
/* Initialize the cache tags: */ |
/* Initialize the cache tags: */ |
231 |
switch (cpu->cd.mips.cpu_type.rev) { |
switch (cpu->cd.mips.cpu_type.rev) { |
251 |
* Secondary cache: |
* Secondary cache: |
252 |
*/ |
*/ |
253 |
secondary_cache_size = 0; |
secondary_cache_size = 0; |
254 |
if (machine->cache_secondary) |
if (cpu->cd.mips.cache_secondary) |
255 |
secondary_cache_size = 1 << machine->cache_secondary; |
secondary_cache_size = 1 << cpu->cd.mips.cache_secondary; |
256 |
/* TODO: linesize... */ |
/* TODO: linesize... */ |
257 |
|
|
258 |
if (cpu_id == 0) { |
if (cpu_id == 0) { |
783 |
|
|
784 |
switch (sub) { |
switch (sub) { |
785 |
case 0x00: |
case 0x00: |
786 |
debug("%s\t%s,", |
debug("%s\t%s,", special_names[special6], |
787 |
special_names[special6], |
regnames[rd]); |
788 |
regname(cpu->machine, rd)); |
debug("%s,%i", regnames[rt], sa); |
|
debug("%s,%i", regname(cpu->machine, rt), sa); |
|
789 |
break; |
break; |
790 |
case 0x01: |
case 0x01: |
791 |
debug("%s\t%s,", |
debug("%s\t%s,", |
792 |
special_rot_names[special6], |
special_rot_names[special6], |
793 |
regname(cpu->machine, rd)); |
regnames[rd]); |
794 |
debug("%s,%i", regname(cpu->machine, rt), sa); |
debug("%s,%i", regnames[rt], sa); |
795 |
break; |
break; |
796 |
default:debug("UNIMPLEMENTED special, sub=0x%02x\n", |
default:debug("UNIMPLEMENTED special, sub=0x%02x\n", |
797 |
sub); |
sub); |
811 |
switch (sub) { |
switch (sub) { |
812 |
case 0x00: |
case 0x00: |
813 |
debug("%s\t%s", special_names[special6], |
debug("%s\t%s", special_names[special6], |
814 |
regname(cpu->machine, rd)); |
regnames[rd]); |
815 |
debug(",%s", regname(cpu->machine, rt)); |
debug(",%s", regnames[rt]); |
816 |
debug(",%s", regname(cpu->machine, rs)); |
debug(",%s", regnames[rs]); |
817 |
break; |
break; |
818 |
case 0x01: |
case 0x01: |
819 |
debug("%s\t%s", special_rot_names[special6], |
debug("%s\t%s", special_rot_names[special6], |
820 |
regname(cpu->machine, rd)); |
regnames[rd]); |
821 |
debug(",%s", regname(cpu->machine, rt)); |
debug(",%s", regnames[rt]); |
822 |
debug(",%s", regname(cpu->machine, rs)); |
debug(",%s", regnames[rs]); |
823 |
break; |
break; |
824 |
default:debug("UNIMPLEMENTED special, sub=0x%02x\n", |
default:debug("UNIMPLEMENTED special, sub=0x%02x\n", |
825 |
sub); |
sub); |
832 |
/* .hb = hazard barrier hint on MIPS32/64 rev 2 */ |
/* .hb = hazard barrier hint on MIPS32/64 rev 2 */ |
833 |
debug("jr%s\t%s", |
debug("jr%s\t%s", |
834 |
(instr[1] & 0x04) ? ".hb" : "", |
(instr[1] & 0x04) ? ".hb" : "", |
835 |
regname(cpu->machine, rs)); |
regnames[rs]); |
836 |
if (running && symbol != NULL) |
if (running && symbol != NULL) |
837 |
debug("\t<%s>", symbol); |
debug("\t<%s>", symbol); |
838 |
break; |
break; |
844 |
/* .hb = hazard barrier hint on MIPS32/64 rev 2 */ |
/* .hb = hazard barrier hint on MIPS32/64 rev 2 */ |
845 |
debug("jalr%s\t%s", |
debug("jalr%s\t%s", |
846 |
(instr[1] & 0x04) ? ".hb" : "", |
(instr[1] & 0x04) ? ".hb" : "", |
847 |
regname(cpu->machine, rd)); |
regnames[rd]); |
848 |
debug(",%s", regname(cpu->machine, rs)); |
debug(",%s", regnames[rs]); |
849 |
if (running && symbol != NULL) |
if (running && symbol != NULL) |
850 |
debug("\t<%s>", symbol); |
debug("\t<%s>", symbol); |
851 |
break; |
break; |
852 |
case SPECIAL_MFHI: |
case SPECIAL_MFHI: |
853 |
case SPECIAL_MFLO: |
case SPECIAL_MFLO: |
854 |
rd = (instr[1] >> 3) & 31; |
rd = (instr[1] >> 3) & 31; |
855 |
debug("%s\t%s", special_names[special6], |
debug("%s\t%s", special_names[special6], regnames[rd]); |
|
regname(cpu->machine, rd)); |
|
856 |
break; |
break; |
857 |
case SPECIAL_MTLO: |
case SPECIAL_MTLO: |
858 |
case SPECIAL_MTHI: |
case SPECIAL_MTHI: |
859 |
rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7); |
rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7); |
860 |
debug("%s\t%s", special_names[special6], |
debug("%s\t%s", special_names[special6], regnames[rs]); |
|
regname(cpu->machine, rs)); |
|
861 |
break; |
break; |
862 |
case SPECIAL_ADD: |
case SPECIAL_ADD: |
863 |
case SPECIAL_ADDU: |
case SPECIAL_ADDU: |
882 |
special6 == SPECIAL_SUBU) && rt == 0) { |
special6 == SPECIAL_SUBU) && rt == 0) { |
883 |
/* Special case 1: addu/subu with |
/* Special case 1: addu/subu with |
884 |
rt = the zero register ==> move */ |
rt = the zero register ==> move */ |
885 |
debug("move\t%s", regname(cpu->machine, rd)); |
debug("move\t%s", regnames[rd]); |
886 |
debug(",%s", regname(cpu->machine, rs)); |
debug(",%s", regnames[rs]); |
887 |
} else if (special6 == SPECIAL_ADDU && cpu->is_32bit |
} else if (special6 == SPECIAL_ADDU && cpu->is_32bit |
888 |
&& rs == 0) { |
&& rs == 0) { |
889 |
/* Special case 2: addu with |
/* Special case 2: addu with |
890 |
rs = the zero register ==> move */ |
rs = the zero register ==> move */ |
891 |
debug("move\t%s", regname(cpu->machine, rd)); |
debug("move\t%s", regnames[rd]); |
892 |
debug(",%s", regname(cpu->machine, rt)); |
debug(",%s", regnames[rt]); |
893 |
} else { |
} else { |
894 |
debug("%s\t%s", special_names[special6], |
debug("%s\t%s", special_names[special6], |
895 |
regname(cpu->machine, rd)); |
regnames[rd]); |
896 |
debug(",%s", regname(cpu->machine, rs)); |
debug(",%s", regnames[rs]); |
897 |
debug(",%s", regname(cpu->machine, rt)); |
debug(",%s", regnames[rt]); |
898 |
} |
} |
899 |
break; |
break; |
900 |
case SPECIAL_MULT: |
case SPECIAL_MULT: |
919 |
if (cpu->cd.mips.cpu_type.rev == MIPS_R5900) { |
if (cpu->cd.mips.cpu_type.rev == MIPS_R5900) { |
920 |
if (special6 == SPECIAL_MULT || |
if (special6 == SPECIAL_MULT || |
921 |
special6 == SPECIAL_MULTU) |
special6 == SPECIAL_MULTU) |
922 |
debug("%s,", |
debug("%s,", regnames[rd]); |
|
regname(cpu->machine, rd)); |
|
923 |
else |
else |
924 |
debug("WEIRD_R5900_RD,"); |
debug("WEIRD_R5900_RD,"); |
925 |
} else { |
} else { |
926 |
debug("WEIRD_RD_NONZERO,"); |
debug("WEIRD_RD_NONZERO,"); |
927 |
} |
} |
928 |
} |
} |
929 |
debug("%s", regname(cpu->machine, rs)); |
debug("%s", regnames[rs]); |
930 |
debug(",%s", regname(cpu->machine, rt)); |
debug(",%s", regnames[rt]); |
931 |
break; |
break; |
932 |
case SPECIAL_SYNC: |
case SPECIAL_SYNC: |
933 |
imm = ((instr[1] & 7) << 2) + (instr[0] >> 6); |
imm = ((instr[1] & 7) << 2) + (instr[0] >> 6); |
952 |
case SPECIAL_MFSA: |
case SPECIAL_MFSA: |
953 |
if (cpu->cd.mips.cpu_type.rev == MIPS_R5900) { |
if (cpu->cd.mips.cpu_type.rev == MIPS_R5900) { |
954 |
rd = (instr[1] >> 3) & 31; |
rd = (instr[1] >> 3) & 31; |
955 |
debug("mfsa\t%s", regname(cpu->machine, rd)); |
debug("mfsa\t%s", regnames[rd]); |
956 |
} else { |
} else { |
957 |
debug("unimplemented special 0x28"); |
debug("unimplemented special 0x28"); |
958 |
} |
} |
961 |
if (cpu->cd.mips.cpu_type.rev == MIPS_R5900) { |
if (cpu->cd.mips.cpu_type.rev == MIPS_R5900) { |
962 |
rs = ((instr[3] & 3) << 3) + |
rs = ((instr[3] & 3) << 3) + |
963 |
((instr[2] >> 5) & 7); |
((instr[2] >> 5) & 7); |
964 |
debug("mtsa\t%s", regname(cpu->machine, rs)); |
debug("mtsa\t%s", regnames[rs]); |
965 |
} else { |
} else { |
966 |
debug("unimplemented special 0x29"); |
debug("unimplemented special 0x29"); |
967 |
} |
} |
995 |
case HI6_BEQL: |
case HI6_BEQL: |
996 |
case HI6_BNE: |
case HI6_BNE: |
997 |
case HI6_BNEL: |
case HI6_BNEL: |
998 |
debug("%s,", regname(cpu->machine, rt)); |
debug("%s,", regnames[rt]); |
999 |
} |
} |
1000 |
debug("%s,", regname(cpu->machine, rs)); |
debug("%s,", regnames[rs]); |
1001 |
} |
} |
1002 |
|
|
1003 |
if (cpu->is_32bit) |
if (cpu->is_32bit) |
1024 |
imm = (instr[1] << 8) + instr[0]; |
imm = (instr[1] << 8) + instr[0]; |
1025 |
if (imm >= 32768) |
if (imm >= 32768) |
1026 |
imm -= 65536; |
imm -= 65536; |
1027 |
debug("%s\t%s,", hi6_names[hi6], regname(cpu->machine, rt)); |
debug("%s\t%s,", hi6_names[hi6], regnames[rt]); |
1028 |
debug("%s,", regname(cpu->machine, rs)); |
debug("%s,", regnames[rs]); |
1029 |
if (hi6 == HI6_ANDI || hi6 == HI6_ORI || hi6 == HI6_XORI) |
if (hi6 == HI6_ANDI || hi6 == HI6_ORI || hi6 == HI6_XORI) |
1030 |
debug("0x%04x", imm & 0xffff); |
debug("0x%04x", imm & 0xffff); |
1031 |
else |
else |
1034 |
case HI6_LUI: |
case HI6_LUI: |
1035 |
rt = instr[2] & 31; |
rt = instr[2] & 31; |
1036 |
imm = (instr[1] << 8) + instr[0]; |
imm = (instr[1] << 8) + instr[0]; |
1037 |
debug("lui\t%s,0x%x", regname(cpu->machine, rt), imm); |
debug("lui\t%s,0x%x", regnames[rt], imm); |
1038 |
break; |
break; |
1039 |
case HI6_LB: |
case HI6_LB: |
1040 |
case HI6_LBU: |
case HI6_LBU: |
1097 |
msbd += 32; |
msbd += 32; |
1098 |
if (special6 == SPECIAL3_DEXTU) |
if (special6 == SPECIAL3_DEXTU) |
1099 |
lsb += 32; |
lsb += 32; |
1100 |
debug("\t%s", regname(cpu->machine, rt)); |
debug("\t%s", regnames[rt]); |
1101 |
debug(",%s", regname(cpu->machine, rs)); |
debug(",%s", regnames[rs]); |
1102 |
debug(",%i,%i", lsb, msbd + 1); |
debug(",%i,%i", lsb, msbd + 1); |
1103 |
break; |
break; |
1104 |
|
|
1114 |
msbd += 32; |
msbd += 32; |
1115 |
} |
} |
1116 |
msbd -= lsb; |
msbd -= lsb; |
1117 |
debug("\t%s", regname(cpu->machine, rt)); |
debug("\t%s", regnames[rt]); |
1118 |
debug(",%s", regname(cpu->machine, rs)); |
debug(",%s", regnames[rs]); |
1119 |
debug(",%i,%i", lsb, msbd + 1); |
debug(",%i,%i", lsb, msbd + 1); |
1120 |
break; |
break; |
1121 |
|
|
1129 |
case BSHFL_SEB: debug("seb"); break; |
case BSHFL_SEB: debug("seb"); break; |
1130 |
case BSHFL_SEH: debug("seh"); break; |
case BSHFL_SEH: debug("seh"); break; |
1131 |
} |
} |
1132 |
debug("\t%s", regname(cpu->machine,rd)); |
debug("\t%s", regnames[rd]); |
1133 |
debug(",%s", regname(cpu->machine,rt)); |
debug(",%s", regnames[rt]); |
1134 |
break; |
break; |
1135 |
default:debug("%s", special3_names[special6]); |
default:debug("%s", special3_names[special6]); |
1136 |
debug("\t(UNIMPLEMENTED)"); |
debug("\t(UNIMPLEMENTED)"); |
1145 |
case BSHFL_DSBH: debug("dsbh"); break; |
case BSHFL_DSBH: debug("dsbh"); break; |
1146 |
case BSHFL_DSHD: debug("dshd"); break; |
case BSHFL_DSHD: debug("dshd"); break; |
1147 |
} |
} |
1148 |
debug("\t%s", regname(cpu->machine,rd)); |
debug("\t%s", regnames[rd]); |
1149 |
debug(",%s", regname(cpu->machine,rt)); |
debug(",%s", regnames[rt]); |
1150 |
break; |
break; |
1151 |
default:debug("%s", special3_names[special6]); |
default:debug("%s", special3_names[special6]); |
1152 |
debug("\t(UNIMPLEMENTED)"); |
debug("\t(UNIMPLEMENTED)"); |
1155 |
|
|
1156 |
case SPECIAL3_RDHWR: |
case SPECIAL3_RDHWR: |
1157 |
debug("%s", special3_names[special6]); |
debug("%s", special3_names[special6]); |
1158 |
debug("\t%s", regname(cpu->machine, rt)); |
debug("\t%s", regnames[rt]); |
1159 |
debug(",hwr%i", rd); |
debug(",hwr%i", rd); |
1160 |
break; |
break; |
1161 |
|
|
1177 |
/* TODO: Which ISAs? IV? V? 32? 64? */ |
/* TODO: Which ISAs? IV? V? 32? 64? */ |
1178 |
if (cpu->cd.mips.cpu_type.isa_level >= 4 && hi6 == HI6_LWC3) { |
if (cpu->cd.mips.cpu_type.isa_level >= 4 && hi6 == HI6_LWC3) { |
1179 |
debug("pref\t0x%x,%i(%s)", |
debug("pref\t0x%x,%i(%s)", |
1180 |
rt, imm, regname(cpu->machine, rs)); |
rt, imm, regnames[rs]); |
1181 |
|
|
1182 |
if (running) { |
if (running) { |
1183 |
debug("\t[0x%016"PRIx64" = %s]", |
debug("\t[0x%016"PRIx64" = %s]", |
1197 |
hi6 == HI6_LDC1 || hi6 == HI6_LDC2) |
hi6 == HI6_LDC1 || hi6 == HI6_LDC2) |
1198 |
debug("r%i", rt); |
debug("r%i", rt); |
1199 |
else |
else |
1200 |
debug("%s", regname(cpu->machine, rt)); |
debug("%s", regnames[rt]); |
1201 |
|
|
1202 |
debug(",%i(%s)", imm, regname(cpu->machine, rs)); |
debug(",%i(%s)", imm, regnames[rs]); |
1203 |
|
|
1204 |
if (running) { |
if (running) { |
1205 |
debug("\t["); |
debug("\t["); |
1259 |
cache_op = copz >> 2; |
cache_op = copz >> 2; |
1260 |
which_cache = copz & 3; |
which_cache = copz & 3; |
1261 |
showtag = 0; |
showtag = 0; |
1262 |
debug("cache\t0x%02x,0x%04x(%s)", copz, imm, |
debug("cache\t0x%02x,0x%04x(%s)", copz, imm, regnames[rt]); |
|
regname(cpu->machine, rt)); |
|
1263 |
if (which_cache==0) debug(" [ primary I-cache"); |
if (which_cache==0) debug(" [ primary I-cache"); |
1264 |
if (which_cache==1) debug(" [ primary D-cache"); |
if (which_cache==1) debug(" [ primary D-cache"); |
1265 |
if (which_cache==2) debug(" [ secondary I-cache"); |
if (which_cache==2) debug(" [ secondary I-cache"); |
1302 |
case MMI_MADD: |
case MMI_MADD: |
1303 |
case MMI_MADDU: |
case MMI_MADDU: |
1304 |
if (rd != MIPS_GPR_ZERO) { |
if (rd != MIPS_GPR_ZERO) { |
1305 |
debug("%s,", regname(cpu->machine, rd)); |
debug("%s,", regnames[rd]); |
1306 |
} |
} |
1307 |
debug("%s", regname(cpu->machine, rs)); |
debug("%s,%s", regnames[rs], regnames[rt]); |
|
debug(",%s", regname(cpu->machine, rt)); |
|
1308 |
break; |
break; |
1309 |
|
|
1310 |
case MMI_MMI0: |
case MMI_MMI0: |
1319 |
case MMI0_PPACB: |
case MMI0_PPACB: |
1320 |
case MMI0_PPACH: |
case MMI0_PPACH: |
1321 |
case MMI0_PPACW: |
case MMI0_PPACW: |
1322 |
debug("%s", regname(cpu->machine, rd)); |
debug("%s,%s,%s", regnames[rd], |
1323 |
debug(",%s", regname(cpu->machine, rs)); |
regnames[rs], regnames[rt]); |
|
debug(",%s", regname(cpu->machine, rt)); |
|
1324 |
break; |
break; |
1325 |
|
|
1326 |
default:debug("(UNIMPLEMENTED)"); |
default:debug("(UNIMPLEMENTED)"); |
1336 |
case MMI1_PEXTUW: |
case MMI1_PEXTUW: |
1337 |
case MMI1_PMINH: |
case MMI1_PMINH: |
1338 |
case MMI1_PMINW: |
case MMI1_PMINW: |
1339 |
debug("%s", regname(cpu->machine, rd)); |
debug("%s,%s,%s", regnames[rd], |
1340 |
debug(",%s", regname(cpu->machine, rs)); |
regnames[rs], regnames[rt]); |
|
debug(",%s", regname(cpu->machine, rt)); |
|
1341 |
break; |
break; |
1342 |
|
|
1343 |
default:debug("(UNIMPLEMENTED)"); |
default:debug("(UNIMPLEMENTED)"); |
1350 |
|
|
1351 |
case MMI2_PMFHI: |
case MMI2_PMFHI: |
1352 |
case MMI2_PMFLO: |
case MMI2_PMFLO: |
1353 |
debug("%s", regname(cpu->machine, rd)); |
debug("%s", regnames[rd]); |
1354 |
break; |
break; |
1355 |
|
|
1356 |
case MMI2_PHMADH: |
case MMI2_PHMADH: |
1363 |
case MMI2_PMULTH: |
case MMI2_PMULTH: |
1364 |
case MMI2_PMULTW: |
case MMI2_PMULTW: |
1365 |
case MMI2_PSLLVW: |
case MMI2_PSLLVW: |
1366 |
debug("%s", regname(cpu->machine, rd)); |
debug("%s,%s,%s", regnames[rd], |
1367 |
debug(",%s", regname(cpu->machine, rs)); |
regnames[rs], regnames[rt]); |
|
debug(",%s", regname(cpu->machine, rt)); |
|
1368 |
break; |
break; |
1369 |
|
|
1370 |
default:debug("(UNIMPLEMENTED)"); |
default:debug("(UNIMPLEMENTED)"); |
1377 |
|
|
1378 |
case MMI3_PMTHI: |
case MMI3_PMTHI: |
1379 |
case MMI3_PMTLO: |
case MMI3_PMTLO: |
1380 |
debug("%s", regname(cpu->machine, rs)); |
debug("%s", regnames[rs]); |
1381 |
break; |
break; |
1382 |
|
|
1383 |
case MMI3_PINTEH: |
case MMI3_PINTEH: |
1386 |
case MMI3_PNOR: |
case MMI3_PNOR: |
1387 |
case MMI3_POR: |
case MMI3_POR: |
1388 |
case MMI3_PSRAVW: |
case MMI3_PSRAVW: |
1389 |
debug("%s", regname(cpu->machine, rd)); |
debug("%s,%s,%s", regnames[rd], |
1390 |
debug(",%s", regname(cpu->machine, rs)); |
regnames[rs], regnames[rt]); |
|
debug(",%s", regname(cpu->machine, rt)); |
|
1391 |
break; |
break; |
1392 |
|
|
1393 |
default:debug("(UNIMPLEMENTED)"); |
default:debug("(UNIMPLEMENTED)"); |
1410 |
case SPECIAL2_MSUBU: |
case SPECIAL2_MSUBU: |
1411 |
if (rd != MIPS_GPR_ZERO) { |
if (rd != MIPS_GPR_ZERO) { |
1412 |
debug("WEIRD_NONZERO_RD(%s),", |
debug("WEIRD_NONZERO_RD(%s),", |
1413 |
regname(cpu->machine, rd)); |
regnames[rd]); |
1414 |
} |
} |
1415 |
debug("%s", regname(cpu->machine, rs)); |
debug("%s,%s", regnames[rs], regnames[rt]); |
|
debug(",%s", regname(cpu->machine, rt)); |
|
1416 |
break; |
break; |
1417 |
|
|
1418 |
case SPECIAL2_MUL: |
case SPECIAL2_MUL: |
1419 |
/* Apparently used both on R5900 and MIPS32: */ |
/* Apparently used both on R5900 and MIPS32: */ |
1420 |
debug("%s", regname(cpu->machine, rd)); |
debug("%s,%s,%s", regnames[rd], |
1421 |
debug(",%s", regname(cpu->machine, rs)); |
regnames[rs], regnames[rt]); |
|
debug(",%s", regname(cpu->machine, rt)); |
|
1422 |
break; |
break; |
1423 |
|
|
1424 |
case SPECIAL2_CLZ: |
case SPECIAL2_CLZ: |
1425 |
case SPECIAL2_CLO: |
case SPECIAL2_CLO: |
1426 |
case SPECIAL2_DCLZ: |
case SPECIAL2_DCLZ: |
1427 |
case SPECIAL2_DCLO: |
case SPECIAL2_DCLO: |
1428 |
debug("%s", regname(cpu->machine, rd)); |
debug("%s,%s", regnames[rd], regnames[rs]); |
|
debug(",%s", regname(cpu->machine, rs)); |
|
1429 |
break; |
break; |
1430 |
|
|
1431 |
default: |
default: |
1450 |
case REGIMM_BLTZALL: |
case REGIMM_BLTZALL: |
1451 |
case REGIMM_BGEZAL: |
case REGIMM_BGEZAL: |
1452 |
case REGIMM_BGEZALL: |
case REGIMM_BGEZALL: |
1453 |
debug("%s\t%s,", regimm_names[regimm5], |
debug("%s\t%s,", regimm_names[regimm5], regnames[rs]); |
|
regname(cpu->machine, rs)); |
|
1454 |
|
|
1455 |
addr = (dumpaddr + 4) + (imm << 2); |
addr = (dumpaddr + 4) + (imm << 2); |
1456 |
|
|
1462 |
|
|
1463 |
case REGIMM_SYNCI: |
case REGIMM_SYNCI: |
1464 |
debug("%s\t%i(%s)", regimm_names[regimm5], |
debug("%s\t%i(%s)", regimm_names[regimm5], |
1465 |
imm, regname(cpu->machine, rs)); |
imm, regnames[rs]); |
1466 |
break; |
break; |
1467 |
|
|
1468 |
default: |
default: |
1542 |
" "); |
" "); |
1543 |
else |
else |
1544 |
debug(" %3s=%016"PRIx64"%016"PRIx64, |
debug(" %3s=%016"PRIx64"%016"PRIx64, |
1545 |
regname(cpu->machine, r), (uint64_t) |
regnames[r], (uint64_t) |
1546 |
cpu->cd.mips.gpr_quadhi[r], |
cpu->cd.mips.gpr_quadhi[r], |
1547 |
(uint64_t)cpu->cd.mips.gpr[r]); |
(uint64_t)cpu->cd.mips.gpr[r]); |
1548 |
if ((i & 1) == 1) |
if ((i & 1) == 1) |
1556 |
if (i == MIPS_GPR_ZERO) |
if (i == MIPS_GPR_ZERO) |
1557 |
debug(" "); |
debug(" "); |
1558 |
else |
else |
1559 |
debug(" %3s = %08"PRIx32, |
debug(" %3s = %08"PRIx32, regnames[i], |
|
regname(cpu->machine, i), |
|
1560 |
(uint32_t)cpu->cd.mips.gpr[i]); |
(uint32_t)cpu->cd.mips.gpr[i]); |
1561 |
if ((i & 3) == 3) |
if ((i & 3) == 3) |
1562 |
debug("\n"); |
debug("\n"); |
1571 |
debug(" "); |
debug(" "); |
1572 |
else |
else |
1573 |
debug(" %3s = 0x%016"PRIx64, |
debug(" %3s = 0x%016"PRIx64, |
1574 |
regname(cpu->machine, r), |
regnames[r], |
1575 |
(uint64_t)cpu->cd.mips.gpr[r]); |
(uint64_t)cpu->cd.mips.gpr[r]); |
1576 |
if ((i & 1) == 1) |
if ((i & 1) == 1) |
1577 |
debug("\n"); |
debug("\n"); |
1599 |
if ((i & nm1) == 0) |
if ((i & nm1) == 0) |
1600 |
debug("cpu%i:", cpu->cpu_id); |
debug("cpu%i:", cpu->cpu_id); |
1601 |
|
|
1602 |
if (cpu->machine->show_symbolic_register_names && |
if (coprocnr == 0) |
|
coprocnr == 0) |
|
1603 |
debug(" %8s", cop0_names[i]); |
debug(" %8s", cop0_names[i]); |
1604 |
else |
else |
1605 |
debug(" c%i,%02i", coprocnr, i); |
debug(" c%i,%02i", coprocnr, i); |