25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: cpu_mips.c,v 1.56 2006/06/22 13:22:41 debug Exp $ |
* $Id: cpu_mips.c,v 1.61 2006/07/16 13:32:26 debug Exp $ |
29 |
* |
* |
30 |
* MIPS core CPU emulation. |
* MIPS core CPU emulation. |
31 |
*/ |
*/ |
53 |
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54 |
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55 |
extern volatile int single_step; |
extern volatile int single_step; |
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extern int old_show_trace_tree; |
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extern int old_instruction_trace; |
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extern int old_quiet_mode; |
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extern int quiet_mode; |
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56 |
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57 |
static char *exception_names[] = EXCEPTION_NAMES; |
static char *exception_names[] = EXCEPTION_NAMES; |
58 |
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144 |
cpu->is_32bit = 1; |
cpu->is_32bit = 1; |
145 |
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|
146 |
if (cpu->is_32bit) { |
if (cpu->is_32bit) { |
147 |
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cpu->run_instr = mips32_run_instr; |
148 |
cpu->update_translation_table = mips32_update_translation_table; |
cpu->update_translation_table = mips32_update_translation_table; |
149 |
cpu->invalidate_translation_caches = |
cpu->invalidate_translation_caches = |
150 |
mips32_invalidate_translation_caches; |
mips32_invalidate_translation_caches; |
151 |
cpu->invalidate_code_translation = |
cpu->invalidate_code_translation = |
152 |
mips32_invalidate_code_translation; |
mips32_invalidate_code_translation; |
153 |
} else { |
} else { |
154 |
|
cpu->run_instr = mips_run_instr; |
155 |
cpu->update_translation_table = mips_update_translation_table; |
cpu->update_translation_table = mips_update_translation_table; |
156 |
cpu->invalidate_translation_caches = |
cpu->invalidate_translation_caches = |
157 |
mips_invalidate_translation_caches; |
mips_invalidate_translation_caches; |
307 |
|
|
308 |
switch (cpu->cd.mips.cpu_type.mmu_model) { |
switch (cpu->cd.mips.cpu_type.mmu_model) { |
309 |
case MMU3K: |
case MMU3K: |
310 |
cpu->translate_address = translate_address_mmu3k; |
cpu->translate_v2p = translate_v2p_mmu3k; |
311 |
break; |
break; |
312 |
case MMU8K: |
case MMU8K: |
313 |
cpu->translate_address = translate_address_mmu8k; |
cpu->translate_v2p = translate_v2p_mmu8k; |
314 |
break; |
break; |
315 |
case MMU10K: |
case MMU10K: |
316 |
cpu->translate_address = translate_address_mmu10k; |
cpu->translate_v2p = translate_v2p_mmu10k; |
317 |
break; |
break; |
318 |
default: |
default: |
319 |
if (cpu->cd.mips.cpu_type.rev == MIPS_R4100) |
if (cpu->cd.mips.cpu_type.rev == MIPS_R4100) |
320 |
cpu->translate_address = translate_address_mmu4100; |
cpu->translate_v2p = translate_v2p_mmu4100; |
321 |
else |
else |
322 |
cpu->translate_address = translate_address_generic; |
cpu->translate_v2p = translate_v2p_generic; |
323 |
} |
} |
324 |
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mips_init_64bit_dummy_tables(cpu); |
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|
325 |
return 1; |
return 1; |
326 |
} |
} |
327 |
|
|
749 |
} |
} |
750 |
|
|
751 |
/* TODO: Coprocessor 1,2,3 registers. */ |
/* TODO: Coprocessor 1,2,3 registers. */ |
752 |
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753 |
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/* Only return lowest 32 bits when doing 32-bit emulation: */ |
754 |
|
if (!writeflag && m->cpus[cpunr]->is_32bit) |
755 |
|
*valuep = (uint32_t) (*valuep); |
756 |
} |
} |
757 |
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|
758 |
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|
1603 |
} |
} |
1604 |
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|
1605 |
/* Coprocessor registers: */ |
/* Coprocessor registers: */ |
|
/* TODO: multiple selections per register? */ |
|
1606 |
for (i=0; i<32; i++) { |
for (i=0; i<32; i++) { |
1607 |
/* 32-bit: */ |
/* 32-bit: */ |
1608 |
if ((i & nm1) == 0) |
if ((i & nm1) == 0) |