--- trunk/src/cpus/cpu_mips.c	2007/10/08 16:19:01	16
+++ trunk/src/cpus/cpu_mips.c	2007/10/08 16:19:11	18
@@ -25,7 +25,7 @@
  *  SUCH DAMAGE.
  *
  *
- *  $Id: cpu_mips.c,v 1.4 2005/10/07 23:13:51 debug Exp $
+ *  $Id: cpu_mips.c,v 1.6 2005/10/26 14:37:02 debug Exp $
  *
  *  MIPS core CPU emulation.
  */
@@ -158,7 +158,7 @@
 	cpu->byte_order         = EMUL_LITTLE_ENDIAN;
 	cpu->cd.mips.gpr[MIPS_GPR_SP] = INITIAL_STACK_POINTER;
 	cpu->update_translation_table = mips_update_translation_table;
-	cpu->invalidate_translation_caches_paddr =
+	cpu->invalidate_translation_caches =
 	    mips_invalidate_translation_caches_paddr;
 
 	if (cpu->cd.mips.cpu_type.isa_level <= 2 ||
@@ -1468,7 +1468,7 @@
  *  Acknowledge an interrupt. If irq_nr is 2..7, then it is a MIPS hardware
  *  interrupt.  Interrupts 0..1 are ignored (software interrupts).
  *
- *  If irq_nr is >= 8, then it is machine dependant, and md_interrupt() is
+ *  If irq_nr is >= 8, then it is machine dependent, and md_interrupt() is
  *  called.
  */
 int mips_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr)