1 |
/* |
/* |
2 |
* Copyright (C) 2003-2006 Anders Gavare. All rights reserved. |
* Copyright (C) 2003-2007 Anders Gavare. All rights reserved. |
3 |
* |
* |
4 |
* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
5 |
* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: cpu_mips.c,v 1.69 2006/10/07 02:05:21 debug Exp $ |
* $Id: cpu_mips.c,v 1.77 2007/04/10 17:52:27 debug Exp $ |
29 |
* |
* |
30 |
* MIPS core CPU emulation. |
* MIPS core CPU emulation. |
31 |
*/ |
*/ |
88 |
* Convert a register number into either 'r0', 'r31' etc, or a symbolic |
* Convert a register number into either 'r0', 'r31' etc, or a symbolic |
89 |
* name, depending on machine->show_symbolic_register_names. |
* name, depending on machine->show_symbolic_register_names. |
90 |
* |
* |
91 |
* NOTE: _NOT_ reentrant. |
* NOTE: This helper function is _NOT_ reentrant. |
92 |
*/ |
*/ |
93 |
static char *regname(struct machine *machine, int r) |
static char *regname(struct machine *machine, int r) |
94 |
{ |
{ |
304 |
debug(")"); |
debug(")"); |
305 |
} |
} |
306 |
|
|
307 |
|
/* Register the CPU's interrupts: */ |
308 |
|
for (i=2; i<8; i++) { |
309 |
|
struct interrupt template; |
310 |
|
char name[50]; |
311 |
|
snprintf(name, sizeof(name), "%s.%i", cpu->path, i); |
312 |
|
memset(&template, 0, sizeof(template)); |
313 |
|
template.line = 1 << (STATUS_IM_SHIFT + i); |
314 |
|
template.name = name; |
315 |
|
template.extra = cpu; |
316 |
|
template.interrupt_assert = mips_cpu_interrupt_assert; |
317 |
|
template.interrupt_deassert = mips_cpu_interrupt_deassert; |
318 |
|
interrupt_handler_register(&template); |
319 |
|
|
320 |
|
if (i == 7) |
321 |
|
INTERRUPT_CONNECT(name, cpu->cd.mips.irq_compare); |
322 |
|
} |
323 |
|
|
324 |
/* System coprocessor (0), and FPU (1): */ |
/* System coprocessor (0), and FPU (1): */ |
325 |
cpu->cd.mips.coproc[0] = mips_coproc_new(cpu, 0); |
cpu->cd.mips.coproc[0] = mips_coproc_new(cpu, 0); |
326 |
cpu->cd.mips.coproc[1] = mips_coproc_new(cpu, 1); |
cpu->cd.mips.coproc[1] = mips_coproc_new(cpu, 1); |
533 |
/* Raw output: */ |
/* Raw output: */ |
534 |
if (rawflag) { |
if (rawflag) { |
535 |
for (i=0; i<m->ncpus; i++) { |
for (i=0; i<m->ncpus; i++) { |
536 |
|
struct mips_coproc *cop0 = |
537 |
|
m->cpus[i]->cd.mips.coproc[0]; |
538 |
|
|
539 |
if (x >= 0 && i != x) |
if (x >= 0 && i != x) |
540 |
continue; |
continue; |
541 |
|
|
543 |
printf("cpu%i: (", i); |
printf("cpu%i: (", i); |
544 |
|
|
545 |
if (m->cpus[i]->is_32bit) |
if (m->cpus[i]->is_32bit) |
546 |
printf("index=0x%08x random=0x%08x", (int)m-> |
printf("index=0x%08x random=0x%08x", |
547 |
cpus[i]->cd.mips.coproc[0]->reg[COP0_INDEX], |
(int) cop0->reg[COP0_INDEX], |
548 |
(int)m->cpus[i]->cd.mips.coproc[0]->reg |
(int) cop0->reg[COP0_RANDOM]); |
|
[COP0_RANDOM]); |
|
549 |
else |
else |
550 |
printf("index=0x%016"PRIx64 |
printf("index=0x%016"PRIx64 |
551 |
" random=0x%016"PRIx64, |
" random=0x%016"PRIx64, |
552 |
(uint64_t)m->cpus[i]->cd.mips.coproc[0]-> |
(uint64_t) cop0->reg[COP0_INDEX], |
553 |
reg[COP0_INDEX], (uint64_t)m->cpus[i]-> |
(uint64_t) cop0->reg[COP0_RANDOM]); |
|
cd.mips.coproc[0]->reg[COP0_RANDOM]); |
|
554 |
|
|
555 |
if (m->cpus[i]->cd.mips.cpu_type.isa_level >= 3) |
if (m->cpus[i]->cd.mips.cpu_type.isa_level >= 3) |
556 |
printf(" wired=0x%"PRIx64, (uint64_t) m->cpus |
printf(" wired=0x%"PRIx64, |
557 |
[i]->cd.mips.coproc[0]->reg[COP0_WIRED]); |
(uint64_t) cop0->reg[COP0_WIRED]); |
558 |
|
|
559 |
printf(")\n"); |
printf(")\n"); |
560 |
|
|
562 |
nr_of_tlb_entries; j++) { |
nr_of_tlb_entries; j++) { |
563 |
if (m->cpus[i]->cd.mips.cpu_type.mmu_model == |
if (m->cpus[i]->cd.mips.cpu_type.mmu_model == |
564 |
MMU3K) |
MMU3K) |
565 |
printf("%3i: hi=0x%08x lo=0x%08x\n", j, |
printf("%3i: hi=0x%08"PRIx32" lo=0x%08" |
566 |
(int)m->cpus[i]->cd.mips.coproc[0]->tlbs[j].hi, |
PRIx32"\n", j, |
567 |
(int)m->cpus[i]->cd.mips.coproc[0]->tlbs[j].lo0); |
(uint32_t) cop0->tlbs[j].hi, |
568 |
|
(uint32_t) cop0->tlbs[j].lo0); |
569 |
else if (m->cpus[i]->is_32bit) |
else if (m->cpus[i]->is_32bit) |
570 |
printf("%3i: hi=0x%08x mask=0x%08x " |
printf("%3i: hi=0x%08"PRIx32" mask=0x" |
571 |
"lo0=0x%08x lo1=0x%08x\n", j, |
"%08"PRIx32" lo0=0x%08"PRIx32 |
572 |
(int)m->cpus[i]->cd.mips.coproc[0]->tlbs[j].hi, |
" lo1=0x%08"PRIx32"\n", j, |
573 |
(int)m->cpus[i]->cd.mips.coproc[0]->tlbs[j].mask, |
(uint32_t) cop0->tlbs[j].hi, |
574 |
(int)m->cpus[i]->cd.mips.coproc[0]->tlbs[j].lo0, |
(uint32_t) cop0->tlbs[j].mask, |
575 |
(int)m->cpus[i]->cd.mips.coproc[0]->tlbs[j].lo1); |
(uint32_t) cop0->tlbs[j].lo0, |
576 |
|
(uint32_t) cop0->tlbs[j].lo1); |
577 |
else |
else |
578 |
printf("%3i: hi=0x%016"PRIx64" mask=0x%016"PRIx64" " |
printf("%3i: hi=0x%016"PRIx64" mask=" |
579 |
"lo0=0x%016"PRIx64" lo1=0x%016"PRIx64"\n", j, |
"0x%016"PRIx64" lo0=0x%016"PRIx64 |
580 |
(uint64_t)m->cpus[i]->cd.mips.coproc[0]->tlbs[j].hi, |
" lo1=0x%016"PRIx64"\n", j, |
581 |
(uint64_t)m->cpus[i]->cd.mips.coproc[0]->tlbs[j].mask, |
(uint64_t) cop0->tlbs[j].hi, |
582 |
(uint64_t)m->cpus[i]->cd.mips.coproc[0]->tlbs[j].lo0, |
(uint64_t) cop0->tlbs[j].mask, |
583 |
(uint64_t)m->cpus[i]->cd.mips.coproc[0]->tlbs[j].lo1); |
(uint64_t) cop0->tlbs[j].lo0, |
584 |
|
(uint64_t) cop0->tlbs[j].lo1); |
585 |
} |
} |
586 |
} |
} |
587 |
|
|
588 |
return; |
return; |
589 |
} |
} |
590 |
|
|
591 |
/* Nicely formatted output: */ |
/* Nicely formatted output: */ |
592 |
for (i=0; i<m->ncpus; i++) { |
for (i=0; i<m->ncpus; i++) { |
593 |
int pageshift = 12; |
int pageshift = 12; |
594 |
|
struct mips_coproc *cop0 = m->cpus[i]->cd.mips.coproc[0]; |
595 |
|
|
596 |
if (x >= 0 && i != x) |
if (x >= 0 && i != x) |
597 |
continue; |
continue; |
604 |
switch (m->cpus[i]->cd.mips.cpu_type.isa_level) { |
switch (m->cpus[i]->cd.mips.cpu_type.isa_level) { |
605 |
case 1: |
case 1: |
606 |
case 2: printf("index=0x%x random=0x%x", |
case 2: printf("index=0x%x random=0x%x", |
607 |
(int) ((m->cpus[i]->cd.mips.coproc[0]-> |
(int) ((cop0->reg[COP0_INDEX] & R2K3K_INDEX_MASK) |
|
reg[COP0_INDEX] & R2K3K_INDEX_MASK) |
|
608 |
>> R2K3K_INDEX_SHIFT), |
>> R2K3K_INDEX_SHIFT), |
609 |
(int) ((m->cpus[i]->cd.mips.coproc[0]-> |
(int) ((cop0->reg[COP0_RANDOM] & R2K3K_RANDOM_MASK) |
|
reg[COP0_RANDOM] & R2K3K_RANDOM_MASK) |
|
610 |
>> R2K3K_RANDOM_SHIFT)); |
>> R2K3K_RANDOM_SHIFT)); |
611 |
break; |
break; |
612 |
default:printf("index=0x%x random=0x%x", |
default:printf("index=0x%x random=0x%x", |
613 |
(int) (m->cpus[i]->cd.mips.coproc[0]-> |
(int) (cop0->reg[COP0_INDEX] & INDEX_MASK), |
614 |
reg[COP0_INDEX] & INDEX_MASK), |
(int) (cop0->reg[COP0_RANDOM] & RANDOM_MASK)); |
615 |
(int) (m->cpus[i]->cd.mips.coproc[0]-> |
printf(" wired=0x%"PRIx64, |
616 |
reg[COP0_RANDOM] & RANDOM_MASK)); |
(uint64_t) cop0->reg[COP0_WIRED]); |
|
printf(" wired=0x%"PRIx64, (uint64_t) |
|
|
m->cpus[i]->cd.mips.coproc[0]->reg[COP0_WIRED]); |
|
617 |
} |
} |
618 |
|
|
619 |
printf(")\n"); |
printf(")\n"); |
620 |
|
|
621 |
for (j=0; j<m->cpus[i]->cd.mips.cpu_type. |
for (j=0; j<m->cpus[i]->cd.mips.cpu_type. |
622 |
nr_of_tlb_entries; j++) { |
nr_of_tlb_entries; j++) { |
623 |
uint64_t hi,lo0,lo1,mask; |
uint64_t hi = cop0->tlbs[j].hi; |
624 |
hi = m->cpus[i]->cd.mips.coproc[0]->tlbs[j].hi; |
uint64_t lo0 = cop0->tlbs[j].lo0; |
625 |
lo0 = m->cpus[i]->cd.mips.coproc[0]->tlbs[j].lo0; |
uint64_t lo1 = cop0->tlbs[j].lo1; |
626 |
lo1 = m->cpus[i]->cd.mips.coproc[0]->tlbs[j].lo1; |
uint64_t mask = cop0->tlbs[j].mask; |
|
mask = m->cpus[i]->cd.mips.coproc[0]->tlbs[j].mask; |
|
627 |
|
|
628 |
printf("%3i: ", j); |
printf("%3i: ", j); |
629 |
switch (m->cpus[i]->cd.mips.cpu_type.mmu_model) { |
switch (m->cpus[i]->cd.mips.cpu_type.mmu_model) { |
1295 |
if (cache_op==2) debug("index store tag"), showtag=1; |
if (cache_op==2) debug("index store tag"), showtag=1; |
1296 |
if (cache_op==3) debug("create dirty exclusive"); |
if (cache_op==3) debug("create dirty exclusive"); |
1297 |
if (cache_op==4) debug("hit invalidate"); |
if (cache_op==4) debug("hit invalidate"); |
1298 |
if (cache_op==5) debug("fill OR hit writeback invalidate"); |
if (cache_op==5) debug("fill OR hit writeback invalidate"); |
1299 |
if (cache_op==6) debug("hit writeback"); |
if (cache_op==6) debug("hit writeback"); |
1300 |
if (cache_op==7) debug("hit set virtual"); |
if (cache_op==7) debug("hit set virtual"); |
1301 |
if (running) |
if (running) |
1576 |
" "); |
" "); |
1577 |
else |
else |
1578 |
debug(" %3s=%016"PRIx64"%016"PRIx64, |
debug(" %3s=%016"PRIx64"%016"PRIx64, |
1579 |
regname(cpu->machine, r), |
regname(cpu->machine, r), (uint64_t) |
1580 |
(uint64_t)cpu->cd.mips.gpr_quadhi[r], |
cpu->cd.mips.gpr_quadhi[r], |
1581 |
(uint64_t)cpu->cd.mips.gpr[r]); |
(uint64_t)cpu->cd.mips.gpr[r]); |
1582 |
if ((i & 1) == 1) |
if ((i & 1) == 1) |
1583 |
debug("\n"); |
debug("\n"); |
1641 |
debug(" c%i,%02i", coprocnr, i); |
debug(" c%i,%02i", coprocnr, i); |
1642 |
|
|
1643 |
if (bits32) |
if (bits32) |
1644 |
debug("=%08x", (int)cpu->cd.mips.coproc[coprocnr]->reg[i]); |
debug("=%08x", (int)cpu->cd.mips. |
1645 |
|
coproc[coprocnr]->reg[i]); |
1646 |
else { |
else { |
1647 |
if (coprocnr == 0 && (i == COP0_COUNT |
if (coprocnr == 0 && (i == COP0_COUNT |
1648 |
|| i == COP0_COMPARE || i == COP0_INDEX |
|| i == COP0_COMPARE || i == COP0_INDEX |
1649 |
|| i == COP0_RANDOM || i == COP0_WIRED)) |
|| i == COP0_RANDOM || i == COP0_WIRED)) |
1650 |
debug(" = 0x%08x", (int)cpu->cd.mips.coproc[coprocnr]->reg[i]); |
debug(" = 0x%08x", |
1651 |
|
(int) cpu->cd.mips.coproc[ |
1652 |
|
coprocnr]->reg[i]); |
1653 |
else |
else |
1654 |
debug(" = 0x%016"PRIx64, (uint64_t) |
debug(" = 0x%016"PRIx64, (uint64_t) |
1655 |
cpu->cd.mips.coproc[coprocnr]->reg[i]); |
cpu->cd.mips.coproc[ |
1656 |
|
coprocnr]->reg[i]); |
1657 |
} |
} |
1658 |
|
|
1659 |
if ((i & nm1) == nm1) |
if ((i & nm1) == nm1) |
1705 |
} |
} |
1706 |
|
|
1707 |
|
|
|
static void add_response_word(struct cpu *cpu, char *r, uint64_t value, |
|
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size_t maxlen, int len) |
|
|
{ |
|
|
char *format = (len == 4)? "%08"PRIx64 : "%016"PRIx64; |
|
|
if (len == 4) |
|
|
value &= 0xffffffffULL; |
|
|
if (cpu->byte_order == EMUL_LITTLE_ENDIAN) { |
|
|
if (len == 4) { |
|
|
value = ((value & 0xff) << 24) + |
|
|
((value & 0xff00) << 8) + |
|
|
((value & 0xff0000) >> 8) + |
|
|
((value & 0xff000000) >> 24); |
|
|
} else { |
|
|
value = ((value & 0xff) << 56) + |
|
|
((value & 0xff00) << 40) + |
|
|
((value & 0xff0000) << 24) + |
|
|
((value & 0xff000000ULL) << 8) + |
|
|
((value & 0xff00000000ULL) >> 8) + |
|
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((value & 0xff0000000000ULL) >> 24) + |
|
|
((value & 0xff000000000000ULL) >> 40) + |
|
|
((value & 0xff00000000000000ULL) >> 56); |
|
|
} |
|
|
} |
|
|
snprintf(r + strlen(r), maxlen - strlen(r), format, (uint64_t)value); |
|
|
} |
|
|
|
|
|
|
|
1708 |
/* |
/* |
1709 |
* mips_cpu_gdb_stub(): |
* mips_cpu_interrupt_assert(), mips_cpu_interrupt_deassert(): |
1710 |
* |
* |
1711 |
* Execute a "remote GDB" command. Returns 1 on success, 0 on error. |
* Assert or deassert a MIPS CPU interrupt by masking in or out bits |
1712 |
|
* in the CAUSE register of coprocessor 0. |
1713 |
*/ |
*/ |
1714 |
char *mips_cpu_gdb_stub(struct cpu *cpu, char *cmd) |
void mips_cpu_interrupt_assert(struct interrupt *interrupt) |
1715 |
{ |
{ |
1716 |
if (strcmp(cmd, "g") == 0) { |
struct cpu *cpu = interrupt->extra; |
1717 |
/* 76 registers: gprs, sr, lo, hi, badvaddr, cause, pc, |
cpu->cd.mips.coproc[0]->reg[COP0_CAUSE] |= interrupt->line; |
|
fprs, fsr, fir, fp. */ |
|
|
int i; |
|
|
char *r; |
|
|
size_t wlen = cpu->is_32bit? |
|
|
sizeof(uint32_t) : sizeof(uint64_t); |
|
|
size_t len = 1 + 76 * wlen; |
|
|
r = malloc(len); |
|
|
if (r == NULL) { |
|
|
fprintf(stderr, "out of memory\n"); |
|
|
exit(1); |
|
|
} |
|
|
r[0] = '\0'; |
|
|
for (i=0; i<32; i++) |
|
|
add_response_word(cpu, r, cpu->cd.mips.gpr[i], |
|
|
len, wlen); |
|
|
add_response_word(cpu, r, |
|
|
cpu->cd.mips.coproc[0]->reg[COP0_STATUS], len, wlen); |
|
|
add_response_word(cpu, r, cpu->cd.mips.lo, len, wlen); |
|
|
add_response_word(cpu, r, cpu->cd.mips.hi, len, wlen); |
|
|
add_response_word(cpu, r, |
|
|
cpu->cd.mips.coproc[0]->reg[COP0_BADVADDR], len, wlen); |
|
|
add_response_word(cpu, r, |
|
|
cpu->cd.mips.coproc[0]->reg[COP0_CAUSE], len, wlen); |
|
|
add_response_word(cpu, r, cpu->pc, len, wlen); |
|
|
for (i=0; i<32; i++) |
|
|
add_response_word(cpu, r, |
|
|
cpu->cd.mips.coproc[1]->reg[i], len, wlen); |
|
|
add_response_word(cpu, r, |
|
|
cpu->cd.mips.coproc[1]->reg[31] /* fcsr */, len, wlen); |
|
|
add_response_word(cpu, r, |
|
|
cpu->cd.mips.coproc[1]->reg[0] /* fcir */, len, wlen); |
|
|
|
|
|
/* TODO: fp = gpr 30? */ |
|
|
add_response_word(cpu, r, cpu->cd.mips.gpr[30], len, wlen); |
|
|
|
|
|
return r; |
|
|
} |
|
|
|
|
|
if (cmd[0] == 'p') { |
|
|
int regnr = strtol(cmd + 1, NULL, 16); |
|
|
size_t wlen = cpu->is_32bit? sizeof(uint32_t):sizeof(uint64_t); |
|
|
size_t len = 2 * wlen + 1; |
|
|
char *r = malloc(len); |
|
|
r[0] = '\0'; |
|
|
if (regnr >= 0 && regnr <= 31) { |
|
|
add_response_word(cpu, r, |
|
|
cpu->cd.mips.gpr[regnr], len, wlen); |
|
|
} else if (regnr == 0x20) { |
|
|
add_response_word(cpu, r, cpu->cd.mips.coproc[0]-> |
|
|
reg[COP0_STATUS], len, wlen); |
|
|
} else if (regnr == 0x21) { |
|
|
add_response_word(cpu, r, cpu->cd.mips.lo, len, wlen); |
|
|
} else if (regnr == 0x22) { |
|
|
add_response_word(cpu, r, cpu->cd.mips.hi, len, wlen); |
|
|
} else if (regnr == 0x23) { |
|
|
add_response_word(cpu, r, cpu->cd.mips.coproc[0]-> |
|
|
reg[COP0_BADVADDR], len, wlen); |
|
|
} else if (regnr == 0x24) { |
|
|
add_response_word(cpu, r, cpu->cd.mips.coproc[0]-> |
|
|
reg[COP0_CAUSE], len, wlen); |
|
|
} else if (regnr == 0x25) { |
|
|
add_response_word(cpu, r, cpu->pc, len, wlen); |
|
|
} else if (regnr >= 0x26 && regnr <= 0x45 && |
|
|
cpu->cd.mips.coproc[1] != NULL) { |
|
|
add_response_word(cpu, r, cpu->cd.mips.coproc[1]-> |
|
|
reg[regnr - 0x26], len, wlen); |
|
|
} else if (regnr == 0x46) { |
|
|
add_response_word(cpu, r, cpu->cd.mips.coproc[1]-> |
|
|
fcr[MIPS_FPU_FCSR], len, wlen); |
|
|
} else if (regnr == 0x47) { |
|
|
add_response_word(cpu, r, cpu->cd.mips.coproc[1]-> |
|
|
fcr[MIPS_FPU_FCIR], len, wlen); |
|
|
} else { |
|
|
/* Unimplemented: */ |
|
|
add_response_word(cpu, r, 0xcc000 + regnr, len, wlen); |
|
|
} |
|
|
return r; |
|
|
} |
|
|
|
|
|
fatal("mips_cpu_gdb_stub(): cmd='%s' TODO\n", cmd); |
|
|
return NULL; |
|
1718 |
} |
} |
1719 |
|
void mips_cpu_interrupt_deassert(struct interrupt *interrupt) |
|
|
|
|
/* |
|
|
* mips_cpu_interrupt(): |
|
|
* |
|
|
* Cause an interrupt. If irq_nr is 2..7, then it is a MIPS hardware |
|
|
* interrupt. 0 and 1 are ignored (software interrupts). |
|
|
* |
|
|
* If irq_nr is >= 8, then this function calls md_interrupt(). |
|
|
*/ |
|
|
int mips_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr) |
|
|
{ |
|
|
if (irq_nr >= 8) { |
|
|
if (cpu->machine->md_interrupt != NULL) |
|
|
cpu->machine->md_interrupt(cpu->machine, |
|
|
cpu, irq_nr, 1); |
|
|
else |
|
|
fatal("mips_cpu_interrupt(): irq_nr = %i, " |
|
|
"but md_interrupt = NULL ?\n", irq_nr); |
|
|
return 1; |
|
|
} |
|
|
|
|
|
if (irq_nr < 2) |
|
|
return 0; |
|
|
|
|
|
cpu->cd.mips.coproc[0]->reg[COP0_CAUSE] |= |
|
|
((1 << irq_nr) << STATUS_IM_SHIFT); |
|
|
|
|
|
return 1; |
|
|
} |
|
|
|
|
|
|
|
|
/* |
|
|
* mips_cpu_interrupt_ack(): |
|
|
* |
|
|
* Acknowledge an interrupt. If irq_nr is 2..7, then it is a MIPS hardware |
|
|
* interrupt. Interrupts 0..1 are ignored (software interrupts). |
|
|
* |
|
|
* If irq_nr is >= 8, then it is machine dependent, and md_interrupt() is |
|
|
* called. |
|
|
*/ |
|
|
int mips_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr) |
|
1720 |
{ |
{ |
1721 |
if (irq_nr >= 8) { |
struct cpu *cpu = interrupt->extra; |
1722 |
if (cpu->machine->md_interrupt != NULL) |
cpu->cd.mips.coproc[0]->reg[COP0_CAUSE] &= ~interrupt->line; |
|
cpu->machine->md_interrupt(cpu->machine, cpu, |
|
|
irq_nr, 0); |
|
|
else |
|
|
fatal("mips_cpu_interrupt_ack(): irq_nr = %i, " |
|
|
"but md_interrupt = NULL ?\n", irq_nr); |
|
|
return 1; |
|
|
} |
|
|
|
|
|
if (irq_nr < 2) |
|
|
return 0; |
|
|
|
|
|
cpu->cd.mips.coproc[0]->reg[COP0_CAUSE] &= |
|
|
~((1 << irq_nr) << STATUS_IM_SHIFT); |
|
|
|
|
|
return 1; |
|
1723 |
} |
} |
1724 |
|
|
1725 |
|
|