1 |
/* |
2 |
* Copyright (C) 2003-2006 Anders Gavare. All rights reserved. |
3 |
* |
4 |
* Redistribution and use in source and binary forms, with or without |
5 |
* modification, are permitted provided that the following conditions are met: |
6 |
* |
7 |
* 1. Redistributions of source code must retain the above copyright |
8 |
* notice, this list of conditions and the following disclaimer. |
9 |
* 2. Redistributions in binary form must reproduce the above copyright |
10 |
* notice, this list of conditions and the following disclaimer in the |
11 |
* documentation and/or other materials provided with the distribution. |
12 |
* 3. The name of the author may not be used to endorse or promote products |
13 |
* derived from this software without specific prior written permission. |
14 |
* |
15 |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
16 |
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
17 |
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
18 |
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
19 |
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
20 |
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
21 |
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
22 |
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
23 |
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
24 |
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
25 |
* SUCH DAMAGE. |
26 |
* |
27 |
* |
28 |
* $Id: cpu_mips.c,v 1.58 2006/06/24 21:47:23 debug Exp $ |
29 |
* |
30 |
* MIPS core CPU emulation. |
31 |
*/ |
32 |
|
33 |
#include <stdio.h> |
34 |
#include <stdlib.h> |
35 |
#include <string.h> |
36 |
#include <sys/types.h> |
37 |
#include <ctype.h> |
38 |
|
39 |
#include "../../config.h" |
40 |
|
41 |
#include "arcbios.h" |
42 |
#include "cop0.h" |
43 |
#include "cpu.h" |
44 |
#include "cpu_mips.h" |
45 |
#include "debugger.h" |
46 |
#include "devices.h" |
47 |
#include "emul.h" |
48 |
#include "machine.h" |
49 |
#include "memory.h" |
50 |
#include "mips_cpu_types.h" |
51 |
#include "opcodes_mips.h" |
52 |
#include "symbol.h" |
53 |
|
54 |
|
55 |
extern volatile int single_step; |
56 |
|
57 |
static char *exception_names[] = EXCEPTION_NAMES; |
58 |
|
59 |
static char *hi6_names[] = HI6_NAMES; |
60 |
static char *regimm_names[] = REGIMM_NAMES; |
61 |
static char *special_names[] = SPECIAL_NAMES; |
62 |
static char *special2_names[] = SPECIAL2_NAMES; |
63 |
static char *mmi_names[] = MMI_NAMES; |
64 |
static char *mmi0_names[] = MMI0_NAMES; |
65 |
static char *mmi1_names[] = MMI1_NAMES; |
66 |
static char *mmi2_names[] = MMI2_NAMES; |
67 |
static char *mmi3_names[] = MMI3_NAMES; |
68 |
static char *special3_names[] = SPECIAL3_NAMES; |
69 |
|
70 |
static char *regnames[] = MIPS_REGISTER_NAMES; |
71 |
static char *cop0_names[] = COP0_NAMES; |
72 |
|
73 |
|
74 |
#define DYNTRANS_DUALMODE_32 |
75 |
#define DYNTRANS_DELAYSLOT |
76 |
#include "tmp_mips_head.c" |
77 |
|
78 |
void mips_pc_to_pointers(struct cpu *); |
79 |
void mips32_pc_to_pointers(struct cpu *); |
80 |
|
81 |
|
82 |
/* |
83 |
* regname(): |
84 |
* |
85 |
* Convert a register number into either 'r0', 'r31' etc, or a symbolic |
86 |
* name, depending on machine->show_symbolic_register_names. |
87 |
* |
88 |
* NOTE: _NOT_ reentrant. |
89 |
*/ |
90 |
static char *regname(struct machine *machine, int r) |
91 |
{ |
92 |
static char ch[4]; |
93 |
ch[3] = ch[2] = '\0'; |
94 |
|
95 |
if (r<0 || r>=32) |
96 |
strlcpy(ch, "xx", sizeof(ch)); |
97 |
else if (machine->show_symbolic_register_names) |
98 |
strlcpy(ch, regnames[r], sizeof(ch)); |
99 |
else |
100 |
snprintf(ch, sizeof(ch), "r%i", r); |
101 |
|
102 |
return ch; |
103 |
} |
104 |
|
105 |
|
106 |
/* |
107 |
* mips_cpu_new(): |
108 |
* |
109 |
* Create a new MIPS cpu object. |
110 |
* |
111 |
* Returns 1 on success, 0 if there was no valid MIPS processor with |
112 |
* a matching name. |
113 |
*/ |
114 |
int mips_cpu_new(struct cpu *cpu, struct memory *mem, struct machine *machine, |
115 |
int cpu_id, char *cpu_type_name) |
116 |
{ |
117 |
int i, found, j, tags_size, n_cache_lines, size_per_cache_line; |
118 |
struct mips_cpu_type_def cpu_type_defs[] = MIPS_CPU_TYPE_DEFS; |
119 |
int64_t secondary_cache_size; |
120 |
int x, linesize; |
121 |
|
122 |
/* Scan the cpu_type_defs list for this cpu type: */ |
123 |
i = 0; |
124 |
found = -1; |
125 |
while (i >= 0 && cpu_type_defs[i].name != NULL) { |
126 |
if (strcasecmp(cpu_type_defs[i].name, cpu_type_name) == 0) { |
127 |
found = i; |
128 |
break; |
129 |
} |
130 |
i++; |
131 |
} |
132 |
|
133 |
if (found == -1) |
134 |
return 0; |
135 |
|
136 |
cpu->memory_rw = mips_memory_rw; |
137 |
cpu->cd.mips.cpu_type = cpu_type_defs[found]; |
138 |
cpu->name = cpu->cd.mips.cpu_type.name; |
139 |
cpu->byte_order = EMUL_LITTLE_ENDIAN; |
140 |
cpu->cd.mips.gpr[MIPS_GPR_SP] = INITIAL_STACK_POINTER; |
141 |
|
142 |
if (cpu->cd.mips.cpu_type.isa_level <= 2 || |
143 |
cpu->cd.mips.cpu_type.isa_level == 32) |
144 |
cpu->is_32bit = 1; |
145 |
|
146 |
if (cpu->is_32bit) { |
147 |
cpu->update_translation_table = mips32_update_translation_table; |
148 |
cpu->invalidate_translation_caches = |
149 |
mips32_invalidate_translation_caches; |
150 |
cpu->invalidate_code_translation = |
151 |
mips32_invalidate_code_translation; |
152 |
} else { |
153 |
cpu->update_translation_table = mips_update_translation_table; |
154 |
cpu->invalidate_translation_caches = |
155 |
mips_invalidate_translation_caches; |
156 |
cpu->invalidate_code_translation = |
157 |
mips_invalidate_code_translation; |
158 |
} |
159 |
|
160 |
cpu->instruction_has_delayslot = mips_cpu_instruction_has_delayslot; |
161 |
|
162 |
if (cpu_id == 0) |
163 |
debug("%s", cpu->cd.mips.cpu_type.name); |
164 |
|
165 |
/* |
166 |
* CACHES: |
167 |
* |
168 |
* 1) Use DEFAULT_PCACHE_SIZE and DEFAULT_PCACHE_LINESIZE etc. |
169 |
* 2) If there are specific values defined for this type of cpu, |
170 |
* in its cpu_type substruct, then let's use those. |
171 |
* 3) Values in the emul struct override both of the above. |
172 |
* |
173 |
* Once we've decided which values to use, they are stored in |
174 |
* the emul struct so they can be used from src/machine.c etc. |
175 |
*/ |
176 |
|
177 |
x = DEFAULT_PCACHE_SIZE; |
178 |
if (cpu->cd.mips.cpu_type.pdcache) |
179 |
x = cpu->cd.mips.cpu_type.pdcache; |
180 |
if (machine->cache_pdcache == 0) |
181 |
machine->cache_pdcache = x; |
182 |
|
183 |
x = DEFAULT_PCACHE_SIZE; |
184 |
if (cpu->cd.mips.cpu_type.picache) |
185 |
x = cpu->cd.mips.cpu_type.picache; |
186 |
if (machine->cache_picache == 0) |
187 |
machine->cache_picache = x; |
188 |
|
189 |
if (machine->cache_secondary == 0) |
190 |
machine->cache_secondary = cpu->cd.mips.cpu_type.scache; |
191 |
|
192 |
linesize = DEFAULT_PCACHE_LINESIZE; |
193 |
if (cpu->cd.mips.cpu_type.pdlinesize) |
194 |
linesize = cpu->cd.mips.cpu_type.pdlinesize; |
195 |
if (machine->cache_pdcache_linesize == 0) |
196 |
machine->cache_pdcache_linesize = linesize; |
197 |
|
198 |
linesize = DEFAULT_PCACHE_LINESIZE; |
199 |
if (cpu->cd.mips.cpu_type.pilinesize) |
200 |
linesize = cpu->cd.mips.cpu_type.pilinesize; |
201 |
if (machine->cache_picache_linesize == 0) |
202 |
machine->cache_picache_linesize = linesize; |
203 |
|
204 |
linesize = 0; |
205 |
if (cpu->cd.mips.cpu_type.slinesize) |
206 |
linesize = cpu->cd.mips.cpu_type.slinesize; |
207 |
if (machine->cache_secondary_linesize == 0) |
208 |
machine->cache_secondary_linesize = linesize; |
209 |
|
210 |
|
211 |
/* |
212 |
* Primary Data and Instruction caches: |
213 |
*/ |
214 |
for (i=CACHE_DATA; i<=CACHE_INSTRUCTION; i++) { |
215 |
switch (i) { |
216 |
case CACHE_DATA: |
217 |
x = 1 << machine->cache_pdcache; |
218 |
linesize = 1 << machine->cache_pdcache_linesize; |
219 |
break; |
220 |
case CACHE_INSTRUCTION: |
221 |
x = 1 << machine->cache_picache; |
222 |
linesize = 1 << machine->cache_picache_linesize; |
223 |
break; |
224 |
} |
225 |
|
226 |
/* Primary cache size and linesize: */ |
227 |
cpu->cd.mips.cache_size[i] = x; |
228 |
cpu->cd.mips.cache_linesize[i] = linesize; |
229 |
|
230 |
switch (cpu->cd.mips.cpu_type.rev) { |
231 |
case MIPS_R2000: |
232 |
case MIPS_R3000: |
233 |
size_per_cache_line = sizeof(struct r3000_cache_line); |
234 |
break; |
235 |
default: |
236 |
size_per_cache_line = sizeof(struct r4000_cache_line); |
237 |
} |
238 |
|
239 |
cpu->cd.mips.cache_mask[i] = cpu->cd.mips.cache_size[i] - 1; |
240 |
cpu->cd.mips.cache_miss_penalty[i] = 10; /* TODO ? */ |
241 |
|
242 |
cpu->cd.mips.cache[i] = malloc(cpu->cd.mips.cache_size[i]); |
243 |
if (cpu->cd.mips.cache[i] == NULL) { |
244 |
fprintf(stderr, "out of memory\n"); |
245 |
} |
246 |
|
247 |
n_cache_lines = cpu->cd.mips.cache_size[i] / |
248 |
cpu->cd.mips.cache_linesize[i]; |
249 |
tags_size = n_cache_lines * size_per_cache_line; |
250 |
|
251 |
cpu->cd.mips.cache_tags[i] = malloc(tags_size); |
252 |
if (cpu->cd.mips.cache_tags[i] == NULL) { |
253 |
fprintf(stderr, "out of memory\n"); |
254 |
} |
255 |
|
256 |
/* Initialize the cache tags: */ |
257 |
switch (cpu->cd.mips.cpu_type.rev) { |
258 |
case MIPS_R2000: |
259 |
case MIPS_R3000: |
260 |
for (j=0; j<n_cache_lines; j++) { |
261 |
struct r3000_cache_line *rp; |
262 |
rp = (struct r3000_cache_line *) |
263 |
cpu->cd.mips.cache_tags[i]; |
264 |
rp[j].tag_paddr = 0; |
265 |
rp[j].tag_valid = 0; |
266 |
} |
267 |
break; |
268 |
default: |
269 |
; |
270 |
} |
271 |
|
272 |
/* Set cache_last_paddr to something "impossible": */ |
273 |
cpu->cd.mips.cache_last_paddr[i] = IMPOSSIBLE_PADDR; |
274 |
} |
275 |
|
276 |
/* |
277 |
* Secondary cache: |
278 |
*/ |
279 |
secondary_cache_size = 0; |
280 |
if (machine->cache_secondary) |
281 |
secondary_cache_size = 1 << machine->cache_secondary; |
282 |
/* TODO: linesize... */ |
283 |
|
284 |
if (cpu_id == 0) { |
285 |
debug(" (I+D = %i+%i KB", |
286 |
(int)(cpu->cd.mips.cache_size[CACHE_INSTRUCTION] / 1024), |
287 |
(int)(cpu->cd.mips.cache_size[CACHE_DATA] / 1024)); |
288 |
|
289 |
if (secondary_cache_size != 0) { |
290 |
debug(", L2 = "); |
291 |
if (secondary_cache_size >= 1048576) |
292 |
debug("%i MB", (int) |
293 |
(secondary_cache_size / 1048576)); |
294 |
else |
295 |
debug("%i KB", (int) |
296 |
(secondary_cache_size / 1024)); |
297 |
} |
298 |
|
299 |
debug(")"); |
300 |
} |
301 |
|
302 |
/* System coprocessor (0), and FPU (1): */ |
303 |
cpu->cd.mips.coproc[0] = mips_coproc_new(cpu, 0); |
304 |
cpu->cd.mips.coproc[1] = mips_coproc_new(cpu, 1); |
305 |
|
306 |
switch (cpu->cd.mips.cpu_type.mmu_model) { |
307 |
case MMU3K: |
308 |
cpu->translate_v2p = translate_v2p_mmu3k; |
309 |
break; |
310 |
case MMU8K: |
311 |
cpu->translate_v2p = translate_v2p_mmu8k; |
312 |
break; |
313 |
case MMU10K: |
314 |
cpu->translate_v2p = translate_v2p_mmu10k; |
315 |
break; |
316 |
default: |
317 |
if (cpu->cd.mips.cpu_type.rev == MIPS_R4100) |
318 |
cpu->translate_v2p = translate_v2p_mmu4100; |
319 |
else |
320 |
cpu->translate_v2p = translate_v2p_generic; |
321 |
} |
322 |
|
323 |
return 1; |
324 |
} |
325 |
|
326 |
|
327 |
/* |
328 |
* mips_cpu_dumpinfo(): |
329 |
* |
330 |
* Debug dump of MIPS-specific CPU data for specific CPU. |
331 |
*/ |
332 |
void mips_cpu_dumpinfo(struct cpu *cpu) |
333 |
{ |
334 |
int iadd = DEBUG_INDENTATION; |
335 |
struct mips_cpu_type_def *ct = &cpu->cd.mips.cpu_type; |
336 |
|
337 |
debug_indentation(iadd); |
338 |
|
339 |
debug("\n%i-bit %s-endian (MIPS", |
340 |
cpu->is_32bit? 32 : 64, |
341 |
cpu->byte_order == EMUL_BIG_ENDIAN? "Big" : "Little"); |
342 |
|
343 |
switch (ct->isa_level) { |
344 |
case 1: debug(" ISA I"); break; |
345 |
case 2: debug(" ISA II"); break; |
346 |
case 3: debug(" ISA III"); break; |
347 |
case 4: debug(" ISA IV"); break; |
348 |
case 5: debug(" ISA V"); break; |
349 |
case 32: |
350 |
case 64:debug("%i, revision %i", ct->isa_level, ct->isa_revision); |
351 |
break; |
352 |
default:debug(" ISA level %i", ct->isa_level); |
353 |
} |
354 |
|
355 |
debug("), "); |
356 |
if (ct->nr_of_tlb_entries) |
357 |
debug("%i TLB entries", ct->nr_of_tlb_entries); |
358 |
else |
359 |
debug("no TLB"); |
360 |
debug("\n"); |
361 |
|
362 |
if (ct->picache) { |
363 |
debug("L1 I-cache: %i KB", (1 << ct->picache) / 1024); |
364 |
if (ct->pilinesize) |
365 |
debug(", %i bytes per line", 1 << ct->pilinesize); |
366 |
if (ct->piways > 1) |
367 |
debug(", %i-way", ct->piways); |
368 |
else |
369 |
debug(", direct-mapped"); |
370 |
debug("\n"); |
371 |
} |
372 |
|
373 |
if (ct->pdcache) { |
374 |
debug("L1 D-cache: %i KB", (1 << ct->pdcache) / 1024); |
375 |
if (ct->pdlinesize) |
376 |
debug(", %i bytes per line", 1 << ct->pdlinesize); |
377 |
if (ct->pdways > 1) |
378 |
debug(", %i-way", ct->pdways); |
379 |
else |
380 |
debug(", direct-mapped"); |
381 |
debug("\n"); |
382 |
} |
383 |
|
384 |
if (ct->scache) { |
385 |
int kb = (1 << ct->scache) / 1024; |
386 |
debug("L2 cache: %i %s", |
387 |
kb >= 1024? kb / 1024 : kb, kb >= 1024? "MB":"KB"); |
388 |
if (ct->slinesize) |
389 |
debug(", %i bytes per line", 1 << ct->slinesize); |
390 |
if (ct->sways > 1) |
391 |
debug(", %i-way", ct->sways); |
392 |
else |
393 |
debug(", direct-mapped"); |
394 |
debug("\n"); |
395 |
} |
396 |
|
397 |
debug_indentation(-iadd); |
398 |
} |
399 |
|
400 |
|
401 |
/* |
402 |
* mips_cpu_list_available_types(): |
403 |
* |
404 |
* Print a list of available MIPS CPU types. |
405 |
*/ |
406 |
void mips_cpu_list_available_types(void) |
407 |
{ |
408 |
int i, j; |
409 |
struct mips_cpu_type_def cpu_type_defs[] = MIPS_CPU_TYPE_DEFS; |
410 |
|
411 |
i = 0; |
412 |
while (cpu_type_defs[i].name != NULL) { |
413 |
debug("%s", cpu_type_defs[i].name); |
414 |
for (j=10 - strlen(cpu_type_defs[i].name); j>0; j--) |
415 |
debug(" "); |
416 |
i++; |
417 |
if ((i % 6) == 0 || cpu_type_defs[i].name == NULL) |
418 |
debug("\n"); |
419 |
} |
420 |
} |
421 |
|
422 |
|
423 |
/* |
424 |
* mips_cpu_instruction_has_delayslot(): |
425 |
* |
426 |
* Return 1 if an opcode is a branch, 0 otherwise. |
427 |
*/ |
428 |
int mips_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib) |
429 |
{ |
430 |
uint32_t iword = *((uint32_t *)&ib[0]); |
431 |
|
432 |
if (cpu->byte_order == EMUL_LITTLE_ENDIAN) |
433 |
iword = LE32_TO_HOST(iword); |
434 |
else |
435 |
iword = BE32_TO_HOST(iword); |
436 |
|
437 |
switch (iword >> 26) { |
438 |
case HI6_SPECIAL: |
439 |
switch (iword & 0x3f) { |
440 |
case SPECIAL_JR: |
441 |
case SPECIAL_JALR: |
442 |
return 1; |
443 |
} |
444 |
break; |
445 |
case HI6_REGIMM: |
446 |
switch ((iword >> 16) & 0x1f) { |
447 |
case REGIMM_BLTZ: |
448 |
case REGIMM_BGEZ: |
449 |
case REGIMM_BLTZL: |
450 |
case REGIMM_BGEZL: |
451 |
case REGIMM_BLTZAL: |
452 |
case REGIMM_BLTZALL: |
453 |
case REGIMM_BGEZAL: |
454 |
case REGIMM_BGEZALL: |
455 |
return 1; |
456 |
} |
457 |
break; |
458 |
case HI6_BEQ: |
459 |
case HI6_BEQL: |
460 |
case HI6_BNE: |
461 |
case HI6_BNEL: |
462 |
case HI6_BGTZ: |
463 |
case HI6_BGTZL: |
464 |
case HI6_BLEZ: |
465 |
case HI6_BLEZL: |
466 |
case HI6_J: |
467 |
case HI6_JAL: |
468 |
return 1; |
469 |
} |
470 |
|
471 |
return 0; |
472 |
} |
473 |
|
474 |
|
475 |
/* |
476 |
* mips_cpu_tlbdump(): |
477 |
* |
478 |
* Called from the debugger to dump the TLB in a readable format. |
479 |
* x is the cpu number to dump, or -1 to dump all CPUs. |
480 |
* |
481 |
* If rawflag is nonzero, then the TLB contents isn't formated nicely, |
482 |
* just dumped. |
483 |
*/ |
484 |
void mips_cpu_tlbdump(struct machine *m, int x, int rawflag) |
485 |
{ |
486 |
int i, j; |
487 |
|
488 |
/* Raw output: */ |
489 |
if (rawflag) { |
490 |
for (i=0; i<m->ncpus; i++) { |
491 |
if (x >= 0 && i != x) |
492 |
continue; |
493 |
|
494 |
/* Print index, random, and wired: */ |
495 |
printf("cpu%i: (", i); |
496 |
|
497 |
if (m->cpus[i]->is_32bit) |
498 |
printf("index=0x%08x random=0x%08x", (int)m-> |
499 |
cpus[i]->cd.mips.coproc[0]->reg[COP0_INDEX], |
500 |
(int)m->cpus[i]->cd.mips.coproc[0]->reg |
501 |
[COP0_RANDOM]); |
502 |
else |
503 |
printf("index=0x%016"PRIx64 |
504 |
" random=0x%016"PRIx64, |
505 |
(uint64_t)m->cpus[i]->cd.mips.coproc[0]-> |
506 |
reg[COP0_INDEX], (uint64_t)m->cpus[i]-> |
507 |
cd.mips.coproc[0]->reg[COP0_RANDOM]); |
508 |
|
509 |
if (m->cpus[i]->cd.mips.cpu_type.isa_level >= 3) |
510 |
printf(" wired=0x%"PRIx64, (uint64_t) m->cpus |
511 |
[i]->cd.mips.coproc[0]->reg[COP0_WIRED]); |
512 |
|
513 |
printf(")\n"); |
514 |
|
515 |
for (j=0; j<m->cpus[i]->cd.mips.cpu_type. |
516 |
nr_of_tlb_entries; j++) { |
517 |
if (m->cpus[i]->cd.mips.cpu_type.mmu_model == |
518 |
MMU3K) |
519 |
printf("%3i: hi=0x%08x lo=0x%08x\n", j, |
520 |
(int)m->cpus[i]->cd.mips.coproc[0]->tlbs[j].hi, |
521 |
(int)m->cpus[i]->cd.mips.coproc[0]->tlbs[j].lo0); |
522 |
else if (m->cpus[i]->is_32bit) |
523 |
printf("%3i: hi=0x%08x mask=0x%08x " |
524 |
"lo0=0x%08x lo1=0x%08x\n", j, |
525 |
(int)m->cpus[i]->cd.mips.coproc[0]->tlbs[j].hi, |
526 |
(int)m->cpus[i]->cd.mips.coproc[0]->tlbs[j].mask, |
527 |
(int)m->cpus[i]->cd.mips.coproc[0]->tlbs[j].lo0, |
528 |
(int)m->cpus[i]->cd.mips.coproc[0]->tlbs[j].lo1); |
529 |
else |
530 |
printf("%3i: hi=0x%016"PRIx64" mask=0x%016"PRIx64" " |
531 |
"lo0=0x%016"PRIx64" lo1=0x%016"PRIx64"\n", j, |
532 |
(uint64_t)m->cpus[i]->cd.mips.coproc[0]->tlbs[j].hi, |
533 |
(uint64_t)m->cpus[i]->cd.mips.coproc[0]->tlbs[j].mask, |
534 |
(uint64_t)m->cpus[i]->cd.mips.coproc[0]->tlbs[j].lo0, |
535 |
(uint64_t)m->cpus[i]->cd.mips.coproc[0]->tlbs[j].lo1); |
536 |
} |
537 |
} |
538 |
return; |
539 |
} |
540 |
|
541 |
/* Nicely formatted output: */ |
542 |
for (i=0; i<m->ncpus; i++) { |
543 |
int pageshift = 12; |
544 |
|
545 |
if (x >= 0 && i != x) |
546 |
continue; |
547 |
|
548 |
if (m->cpus[i]->cd.mips.cpu_type.rev == MIPS_R4100) |
549 |
pageshift = 10; |
550 |
|
551 |
/* Print index, random, and wired: */ |
552 |
printf("cpu%i: (", i); |
553 |
switch (m->cpus[i]->cd.mips.cpu_type.isa_level) { |
554 |
case 1: |
555 |
case 2: printf("index=0x%x random=0x%x", |
556 |
(int) ((m->cpus[i]->cd.mips.coproc[0]-> |
557 |
reg[COP0_INDEX] & R2K3K_INDEX_MASK) |
558 |
>> R2K3K_INDEX_SHIFT), |
559 |
(int) ((m->cpus[i]->cd.mips.coproc[0]-> |
560 |
reg[COP0_RANDOM] & R2K3K_RANDOM_MASK) |
561 |
>> R2K3K_RANDOM_SHIFT)); |
562 |
break; |
563 |
default:printf("index=0x%x random=0x%x", |
564 |
(int) (m->cpus[i]->cd.mips.coproc[0]-> |
565 |
reg[COP0_INDEX] & INDEX_MASK), |
566 |
(int) (m->cpus[i]->cd.mips.coproc[0]-> |
567 |
reg[COP0_RANDOM] & RANDOM_MASK)); |
568 |
printf(" wired=0x%"PRIx64, (uint64_t) |
569 |
m->cpus[i]->cd.mips.coproc[0]->reg[COP0_WIRED]); |
570 |
} |
571 |
|
572 |
printf(")\n"); |
573 |
|
574 |
for (j=0; j<m->cpus[i]->cd.mips.cpu_type. |
575 |
nr_of_tlb_entries; j++) { |
576 |
uint64_t hi,lo0,lo1,mask; |
577 |
hi = m->cpus[i]->cd.mips.coproc[0]->tlbs[j].hi; |
578 |
lo0 = m->cpus[i]->cd.mips.coproc[0]->tlbs[j].lo0; |
579 |
lo1 = m->cpus[i]->cd.mips.coproc[0]->tlbs[j].lo1; |
580 |
mask = m->cpus[i]->cd.mips.coproc[0]->tlbs[j].mask; |
581 |
|
582 |
printf("%3i: ", j); |
583 |
switch (m->cpus[i]->cd.mips.cpu_type.mmu_model) { |
584 |
case MMU3K: |
585 |
if (!(lo0 & R2K3K_ENTRYLO_V)) { |
586 |
printf("(invalid)\n"); |
587 |
continue; |
588 |
} |
589 |
printf("vaddr=0x%08x ", |
590 |
(int) (hi&R2K3K_ENTRYHI_VPN_MASK)); |
591 |
if (lo0 & R2K3K_ENTRYLO_G) |
592 |
printf("(global), "); |
593 |
else |
594 |
printf("(asid %02x),", (int) ((hi & |
595 |
R2K3K_ENTRYHI_ASID_MASK) |
596 |
>> R2K3K_ENTRYHI_ASID_SHIFT)); |
597 |
printf(" paddr=0x%08x ", |
598 |
(int) (lo0&R2K3K_ENTRYLO_PFN_MASK)); |
599 |
if (lo0 & R2K3K_ENTRYLO_N) |
600 |
printf("N"); |
601 |
if (lo0 & R2K3K_ENTRYLO_D) |
602 |
printf("D"); |
603 |
printf("\n"); |
604 |
break; |
605 |
default:switch (m->cpus[i]->cd.mips.cpu_type.mmu_model){ |
606 |
case MMU10K: |
607 |
printf("vaddr=0x%1x..%011"PRIx64" ", |
608 |
(int) (hi >> 60), (uint64_t) |
609 |
(hi&ENTRYHI_VPN2_MASK_R10K)); |
610 |
break; |
611 |
case MMU32: |
612 |
printf("vaddr=0x%08"PRIx32" ", |
613 |
(uint32_t)(hi&ENTRYHI_VPN2_MASK)); |
614 |
break; |
615 |
default:/* R4000 etc. */ |
616 |
printf("vaddr=0x%1x..%010"PRIx64" ", |
617 |
(int) (hi >> 60), |
618 |
(uint64_t) (hi&ENTRYHI_VPN2_MASK)); |
619 |
} |
620 |
if (hi & TLB_G) |
621 |
printf("(global): "); |
622 |
else |
623 |
printf("(asid %02x):", |
624 |
(int) (hi & ENTRYHI_ASID)); |
625 |
|
626 |
/* TODO: Coherency bits */ |
627 |
|
628 |
if (!(lo0 & ENTRYLO_V)) |
629 |
printf(" p0=(invalid) "); |
630 |
else |
631 |
printf(" p0=0x%09"PRIx64" ", (uint64_t) |
632 |
(((lo0&ENTRYLO_PFN_MASK) >> |
633 |
ENTRYLO_PFN_SHIFT) << pageshift)); |
634 |
printf(lo0 & ENTRYLO_D? "D" : " "); |
635 |
|
636 |
if (!(lo1 & ENTRYLO_V)) |
637 |
printf(" p1=(invalid) "); |
638 |
else |
639 |
printf(" p1=0x%09"PRIx64" ", (uint64_t) |
640 |
(((lo1&ENTRYLO_PFN_MASK) >> |
641 |
ENTRYLO_PFN_SHIFT) << pageshift)); |
642 |
printf(lo1 & ENTRYLO_D? "D" : " "); |
643 |
mask |= (1 << (pageshift+1)) - 1; |
644 |
switch (mask) { |
645 |
case 0x7ff: printf(" (1KB)"); break; |
646 |
case 0x1fff: printf(" (4KB)"); break; |
647 |
case 0x7fff: printf(" (16KB)"); break; |
648 |
case 0x1ffff: printf(" (64KB)"); break; |
649 |
case 0x7ffff: printf(" (256KB)"); break; |
650 |
case 0x1fffff: printf(" (1MB)"); break; |
651 |
case 0x7fffff: printf(" (4MB)"); break; |
652 |
case 0x1ffffff: printf(" (16MB)"); break; |
653 |
case 0x7ffffff: printf(" (64MB)"); break; |
654 |
default:printf(" (mask=%08x?)", (int)mask); |
655 |
} |
656 |
printf("\n"); |
657 |
} |
658 |
} |
659 |
} |
660 |
} |
661 |
|
662 |
|
663 |
/* |
664 |
* mips_cpu_register_match(): |
665 |
*/ |
666 |
void mips_cpu_register_match(struct machine *m, char *name, |
667 |
int writeflag, uint64_t *valuep, int *match_register) |
668 |
{ |
669 |
int cpunr = 0; |
670 |
|
671 |
/* CPU number: */ |
672 |
|
673 |
/* TODO */ |
674 |
|
675 |
/* Register name: */ |
676 |
if (strcasecmp(name, "pc") == 0) { |
677 |
if (writeflag) { |
678 |
m->cpus[cpunr]->pc = *valuep; |
679 |
if (m->cpus[cpunr]->delay_slot) { |
680 |
printf("NOTE: Clearing the delay slot" |
681 |
" flag! (It was set before.)\n"); |
682 |
m->cpus[cpunr]->delay_slot = 0; |
683 |
} |
684 |
if (m->cpus[cpunr]->cd.mips.nullify_next) { |
685 |
printf("NOTE: Clearing the nullify-ne" |
686 |
"xt flag! (It was set before.)\n"); |
687 |
m->cpus[cpunr]->cd.mips.nullify_next = 0; |
688 |
} |
689 |
} else |
690 |
*valuep = m->cpus[cpunr]->pc; |
691 |
*match_register = 1; |
692 |
} else if (strcasecmp(name, "hi") == 0) { |
693 |
if (writeflag) |
694 |
m->cpus[cpunr]->cd.mips.hi = *valuep; |
695 |
else |
696 |
*valuep = m->cpus[cpunr]->cd.mips.hi; |
697 |
*match_register = 1; |
698 |
} else if (strcasecmp(name, "lo") == 0) { |
699 |
if (writeflag) |
700 |
m->cpus[cpunr]->cd.mips.lo = *valuep; |
701 |
else |
702 |
*valuep = m->cpus[cpunr]->cd.mips.lo; |
703 |
*match_register = 1; |
704 |
} else if (name[0] == 'r' && isdigit((int)name[1])) { |
705 |
int nr = atoi(name + 1); |
706 |
if (nr >= 0 && nr < N_MIPS_GPRS) { |
707 |
if (writeflag) { |
708 |
if (nr != 0) |
709 |
m->cpus[cpunr]->cd.mips.gpr[nr] = *valuep; |
710 |
else |
711 |
printf("WARNING: Attempt to modify r0.\n"); |
712 |
} else |
713 |
*valuep = m->cpus[cpunr]->cd.mips.gpr[nr]; |
714 |
*match_register = 1; |
715 |
} |
716 |
} else { |
717 |
/* Check for a symbolic name such as "t6" or "at": */ |
718 |
int nr; |
719 |
for (nr=0; nr<N_MIPS_GPRS; nr++) |
720 |
if (strcmp(name, regnames[nr]) == 0) { |
721 |
if (writeflag) { |
722 |
if (nr != 0) |
723 |
m->cpus[cpunr]->cd.mips.gpr[nr] = *valuep; |
724 |
else |
725 |
printf("WARNING: Attempt to modify r0.\n"); |
726 |
} else |
727 |
*valuep = m->cpus[cpunr]->cd.mips.gpr[nr]; |
728 |
*match_register = 1; |
729 |
} |
730 |
} |
731 |
|
732 |
if (!(*match_register)) { |
733 |
/* Check for a symbolic coproc0 name: */ |
734 |
int nr; |
735 |
for (nr=0; nr<32; nr++) |
736 |
if (strcmp(name, cop0_names[nr]) == 0) { |
737 |
if (writeflag) { |
738 |
coproc_register_write(m->cpus[cpunr], |
739 |
m->cpus[cpunr]->cd.mips.coproc[0], nr, |
740 |
valuep, 1, 0); |
741 |
} else { |
742 |
/* TODO: Use coproc_register_read instead? */ |
743 |
*valuep = m->cpus[cpunr]->cd.mips.coproc[0]->reg[nr]; |
744 |
} |
745 |
*match_register = 1; |
746 |
} |
747 |
} |
748 |
|
749 |
/* TODO: Coprocessor 1,2,3 registers. */ |
750 |
} |
751 |
|
752 |
|
753 |
/* |
754 |
* cpu_flags(): |
755 |
* |
756 |
* Returns a pointer to a string containing "(d)" "(j)" "(dj)" or "", |
757 |
* depending on the cpu's current delay_slot and last_was_jumptoself |
758 |
* flags. |
759 |
*/ |
760 |
static const char *cpu_flags(struct cpu *cpu) |
761 |
{ |
762 |
if (cpu->delay_slot) { |
763 |
if (cpu->cd.mips.last_was_jumptoself) |
764 |
return " (dj)"; |
765 |
else |
766 |
return " (d)"; |
767 |
} else { |
768 |
if (cpu->cd.mips.last_was_jumptoself) |
769 |
return " (j)"; |
770 |
else |
771 |
return ""; |
772 |
} |
773 |
} |
774 |
|
775 |
|
776 |
/* |
777 |
* mips_cpu_disassemble_instr(): |
778 |
* |
779 |
* Convert an instruction word into human readable format, for instruction |
780 |
* tracing. |
781 |
* |
782 |
* If running is 1, cpu->pc should be the address of the instruction. |
783 |
* |
784 |
* If running is 0, things that depend on the runtime environment (eg. |
785 |
* register contents) will not be shown, and addr will be used instead of |
786 |
* cpu->pc for relative addresses. |
787 |
* |
788 |
* NOTE 2: coprocessor instructions are not decoded nicely yet (TODO) |
789 |
*/ |
790 |
int mips_cpu_disassemble_instr(struct cpu *cpu, unsigned char *originstr, |
791 |
int running, uint64_t dumpaddr) |
792 |
{ |
793 |
int hi6, special6, regimm5; |
794 |
int rt, rd, rs, sa, imm, copz, cache_op, which_cache, showtag; |
795 |
uint64_t addr, offset; |
796 |
uint32_t instrword; |
797 |
unsigned char instr[4]; |
798 |
char *symbol; |
799 |
|
800 |
if (running) |
801 |
dumpaddr = cpu->pc; |
802 |
|
803 |
if ((dumpaddr & 3) != 0) |
804 |
printf("WARNING: Unaligned address!\n"); |
805 |
|
806 |
symbol = get_symbol_name(&cpu->machine->symbol_context, |
807 |
dumpaddr, &offset); |
808 |
if (symbol != NULL && offset==0) |
809 |
debug("<%s>\n", symbol); |
810 |
|
811 |
if (cpu->machine->ncpus > 1 && running) |
812 |
debug("cpu%i: ", cpu->cpu_id); |
813 |
|
814 |
if (cpu->is_32bit) |
815 |
debug("%08"PRIx32, (uint32_t)dumpaddr); |
816 |
else |
817 |
debug("%016"PRIx64, (uint64_t)dumpaddr); |
818 |
|
819 |
*((uint32_t *)&instr[0]) = *((uint32_t *)&originstr[0]); |
820 |
|
821 |
/* |
822 |
* The rest of the code is written for little endian, |
823 |
* so swap if necessary: |
824 |
*/ |
825 |
if (cpu->byte_order == EMUL_BIG_ENDIAN) { |
826 |
int tmp = instr[0]; instr[0] = instr[3]; |
827 |
instr[3] = tmp; |
828 |
tmp = instr[1]; instr[1] = instr[2]; |
829 |
instr[2] = tmp; |
830 |
} |
831 |
|
832 |
debug(": %02x%02x%02x%02x", |
833 |
instr[3], instr[2], instr[1], instr[0]); |
834 |
|
835 |
if (running) |
836 |
debug("%s", cpu_flags(cpu)); |
837 |
|
838 |
debug("\t"); |
839 |
|
840 |
/* |
841 |
* Decode the instruction: |
842 |
*/ |
843 |
|
844 |
if (cpu->cd.mips.nullify_next && running) { |
845 |
debug("(nullified)"); |
846 |
goto disasm_ret; |
847 |
} |
848 |
|
849 |
hi6 = (instr[3] >> 2) & 0x3f; |
850 |
|
851 |
switch (hi6) { |
852 |
case HI6_SPECIAL: |
853 |
special6 = instr[0] & 0x3f; |
854 |
switch (special6) { |
855 |
case SPECIAL_SLL: |
856 |
case SPECIAL_SRL: |
857 |
case SPECIAL_SRA: |
858 |
case SPECIAL_DSLL: |
859 |
case SPECIAL_DSRL: |
860 |
case SPECIAL_DSRA: |
861 |
case SPECIAL_DSLL32: |
862 |
case SPECIAL_DSRL32: |
863 |
case SPECIAL_DSRA32: |
864 |
rt = instr[2] & 31; |
865 |
rd = (instr[1] >> 3) & 31; |
866 |
sa = ((instr[1] & 7) << 2) + ((instr[0] >> 6) & 3); |
867 |
|
868 |
if (rd == 0 && special6 == SPECIAL_SLL) { |
869 |
if (sa == 0) |
870 |
debug("nop"); |
871 |
else if (sa == 1) |
872 |
debug("ssnop"); |
873 |
else if (sa == 3) |
874 |
debug("ehb"); |
875 |
else |
876 |
debug("nop (weird, sa=%i)", sa); |
877 |
goto disasm_ret; |
878 |
} else |
879 |
debug("%s\t%s,", |
880 |
special_names[special6], |
881 |
regname(cpu->machine, rd)); |
882 |
debug("%s,%i", regname(cpu->machine, rt), sa); |
883 |
break; |
884 |
case SPECIAL_DSRLV: |
885 |
case SPECIAL_DSRAV: |
886 |
case SPECIAL_DSLLV: |
887 |
case SPECIAL_SLLV: |
888 |
case SPECIAL_SRAV: |
889 |
case SPECIAL_SRLV: |
890 |
rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7); |
891 |
rt = instr[2] & 31; |
892 |
rd = (instr[1] >> 3) & 31; |
893 |
debug("%s\t%s", |
894 |
special_names[special6], regname(cpu->machine, rd)); |
895 |
debug(",%s", regname(cpu->machine, rt)); |
896 |
debug(",%s", regname(cpu->machine, rs)); |
897 |
break; |
898 |
case SPECIAL_JR: |
899 |
rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7); |
900 |
symbol = get_symbol_name(&cpu->machine->symbol_context, |
901 |
cpu->cd.mips.gpr[rs], &offset); |
902 |
debug("jr\t%s", regname(cpu->machine, rs)); |
903 |
if (running && symbol != NULL) |
904 |
debug("\t<%s>", symbol); |
905 |
break; |
906 |
case SPECIAL_JALR: |
907 |
rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7); |
908 |
rd = (instr[1] >> 3) & 31; |
909 |
symbol = get_symbol_name(&cpu->machine->symbol_context, |
910 |
cpu->cd.mips.gpr[rs], &offset); |
911 |
debug("jalr\t%s", regname(cpu->machine, rd)); |
912 |
debug(",%s", regname(cpu->machine, rs)); |
913 |
if (running && symbol != NULL) |
914 |
debug("\t<%s>", symbol); |
915 |
break; |
916 |
case SPECIAL_MFHI: |
917 |
case SPECIAL_MFLO: |
918 |
rd = (instr[1] >> 3) & 31; |
919 |
debug("%s\t%s", special_names[special6], |
920 |
regname(cpu->machine, rd)); |
921 |
break; |
922 |
case SPECIAL_MTLO: |
923 |
case SPECIAL_MTHI: |
924 |
rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7); |
925 |
debug("%s\t%s", special_names[special6], |
926 |
regname(cpu->machine, rs)); |
927 |
break; |
928 |
case SPECIAL_ADD: |
929 |
case SPECIAL_ADDU: |
930 |
case SPECIAL_SUB: |
931 |
case SPECIAL_SUBU: |
932 |
case SPECIAL_AND: |
933 |
case SPECIAL_OR: |
934 |
case SPECIAL_XOR: |
935 |
case SPECIAL_NOR: |
936 |
case SPECIAL_SLT: |
937 |
case SPECIAL_SLTU: |
938 |
case SPECIAL_DADD: |
939 |
case SPECIAL_DADDU: |
940 |
case SPECIAL_DSUB: |
941 |
case SPECIAL_DSUBU: |
942 |
case SPECIAL_MOVZ: |
943 |
case SPECIAL_MOVN: |
944 |
rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7); |
945 |
rt = instr[2] & 31; |
946 |
rd = (instr[1] >> 3) & 31; |
947 |
if (cpu->is_32bit && (special6 == SPECIAL_ADDU || |
948 |
special6 == SPECIAL_SUBU) && rt == 0) { |
949 |
/* Special case 1: addu/subu with |
950 |
rt = the zero register ==> move */ |
951 |
debug("move\t%s", regname(cpu->machine, rd)); |
952 |
debug(",%s", regname(cpu->machine, rs)); |
953 |
} else if (special6 == SPECIAL_ADDU && cpu->is_32bit |
954 |
&& rs == 0) { |
955 |
/* Special case 2: addu with |
956 |
rs = the zero register ==> move */ |
957 |
debug("move\t%s", regname(cpu->machine, rd)); |
958 |
debug(",%s", regname(cpu->machine, rt)); |
959 |
} else { |
960 |
debug("%s\t%s", special_names[special6], |
961 |
regname(cpu->machine, rd)); |
962 |
debug(",%s", regname(cpu->machine, rs)); |
963 |
debug(",%s", regname(cpu->machine, rt)); |
964 |
} |
965 |
break; |
966 |
case SPECIAL_MULT: |
967 |
case SPECIAL_MULTU: |
968 |
case SPECIAL_DMULT: |
969 |
case SPECIAL_DMULTU: |
970 |
case SPECIAL_DIV: |
971 |
case SPECIAL_DIVU: |
972 |
case SPECIAL_DDIV: |
973 |
case SPECIAL_DDIVU: |
974 |
case SPECIAL_TGE: |
975 |
case SPECIAL_TGEU: |
976 |
case SPECIAL_TLT: |
977 |
case SPECIAL_TLTU: |
978 |
case SPECIAL_TEQ: |
979 |
case SPECIAL_TNE: |
980 |
rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7); |
981 |
rt = instr[2] & 31; |
982 |
rd = (instr[1] >> 3) & 31; |
983 |
debug("%s\t", special_names[special6]); |
984 |
if (rd != 0) { |
985 |
if (cpu->cd.mips.cpu_type.rev == MIPS_R5900) { |
986 |
if (special6 == SPECIAL_MULT || |
987 |
special6 == SPECIAL_MULTU) |
988 |
debug("%s,", |
989 |
regname(cpu->machine, rd)); |
990 |
else |
991 |
debug("WEIRD_R5900_RD,"); |
992 |
} else { |
993 |
debug("WEIRD_RD_NONZERO,"); |
994 |
} |
995 |
} |
996 |
debug("%s", regname(cpu->machine, rs)); |
997 |
debug(",%s", regname(cpu->machine, rt)); |
998 |
break; |
999 |
case SPECIAL_SYNC: |
1000 |
imm = ((instr[1] & 7) << 2) + (instr[0] >> 6); |
1001 |
debug("sync\t0x%02x", imm); |
1002 |
break; |
1003 |
case SPECIAL_SYSCALL: |
1004 |
imm = (((instr[3] << 24) + (instr[2] << 16) + |
1005 |
(instr[1] << 8) + instr[0]) >> 6) & 0xfffff; |
1006 |
if (imm != 0) |
1007 |
debug("syscall\t0x%05x", imm); |
1008 |
else |
1009 |
debug("syscall"); |
1010 |
break; |
1011 |
case SPECIAL_BREAK: |
1012 |
imm = (((instr[3] << 24) + (instr[2] << 16) + |
1013 |
(instr[1] << 8) + instr[0]) >> 6) & 0xfffff; |
1014 |
if (imm != 0) |
1015 |
debug("break\t0x%05x", imm); |
1016 |
else |
1017 |
debug("break"); |
1018 |
break; |
1019 |
case SPECIAL_MFSA: |
1020 |
if (cpu->cd.mips.cpu_type.rev == MIPS_R5900) { |
1021 |
rd = (instr[1] >> 3) & 31; |
1022 |
debug("mfsa\t%s", regname(cpu->machine, rd)); |
1023 |
} else { |
1024 |
debug("unimplemented special 0x28"); |
1025 |
} |
1026 |
break; |
1027 |
case SPECIAL_MTSA: |
1028 |
if (cpu->cd.mips.cpu_type.rev == MIPS_R5900) { |
1029 |
rs = ((instr[3] & 3) << 3) + |
1030 |
((instr[2] >> 5) & 7); |
1031 |
debug("mtsa\t%s", regname(cpu->machine, rs)); |
1032 |
} else { |
1033 |
debug("unimplemented special 0x29"); |
1034 |
} |
1035 |
break; |
1036 |
default: |
1037 |
debug("%s\t= UNIMPLEMENTED", special_names[special6]); |
1038 |
} |
1039 |
break; |
1040 |
case HI6_BEQ: |
1041 |
case HI6_BEQL: |
1042 |
case HI6_BNE: |
1043 |
case HI6_BNEL: |
1044 |
case HI6_BGTZ: |
1045 |
case HI6_BGTZL: |
1046 |
case HI6_BLEZ: |
1047 |
case HI6_BLEZL: |
1048 |
rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7); |
1049 |
rt = instr[2] & 31; |
1050 |
imm = (instr[1] << 8) + instr[0]; |
1051 |
if (imm >= 32768) |
1052 |
imm -= 65536; |
1053 |
addr = (dumpaddr + 4) + (imm << 2); |
1054 |
|
1055 |
if (hi6 == HI6_BEQ && rt == MIPS_GPR_ZERO && |
1056 |
rs == MIPS_GPR_ZERO) |
1057 |
debug("b\t"); |
1058 |
else { |
1059 |
debug("%s\t", hi6_names[hi6]); |
1060 |
switch (hi6) { |
1061 |
case HI6_BEQ: |
1062 |
case HI6_BEQL: |
1063 |
case HI6_BNE: |
1064 |
case HI6_BNEL: |
1065 |
debug("%s,", regname(cpu->machine, rt)); |
1066 |
} |
1067 |
debug("%s,", regname(cpu->machine, rs)); |
1068 |
} |
1069 |
|
1070 |
if (cpu->is_32bit) |
1071 |
debug("0x%08"PRIx32, (uint32_t)addr); |
1072 |
else |
1073 |
debug("0x%016"PRIx64, (uint64_t)addr); |
1074 |
|
1075 |
symbol = get_symbol_name(&cpu->machine->symbol_context, |
1076 |
addr, &offset); |
1077 |
if (symbol != NULL && offset != addr) |
1078 |
debug("\t<%s>", symbol); |
1079 |
break; |
1080 |
case HI6_ADDI: |
1081 |
case HI6_ADDIU: |
1082 |
case HI6_DADDI: |
1083 |
case HI6_DADDIU: |
1084 |
case HI6_SLTI: |
1085 |
case HI6_SLTIU: |
1086 |
case HI6_ANDI: |
1087 |
case HI6_ORI: |
1088 |
case HI6_XORI: |
1089 |
rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7); |
1090 |
rt = instr[2] & 31; |
1091 |
imm = (instr[1] << 8) + instr[0]; |
1092 |
if (imm >= 32768) |
1093 |
imm -= 65536; |
1094 |
debug("%s\t%s,", hi6_names[hi6], regname(cpu->machine, rt)); |
1095 |
debug("%s,", regname(cpu->machine, rs)); |
1096 |
if (hi6 == HI6_ANDI || hi6 == HI6_ORI || hi6 == HI6_XORI) |
1097 |
debug("0x%04x", imm & 0xffff); |
1098 |
else |
1099 |
debug("%i", imm); |
1100 |
break; |
1101 |
case HI6_LUI: |
1102 |
rt = instr[2] & 31; |
1103 |
imm = (instr[1] << 8) + instr[0]; |
1104 |
debug("lui\t%s,0x%x", regname(cpu->machine, rt), imm); |
1105 |
break; |
1106 |
case HI6_LB: |
1107 |
case HI6_LBU: |
1108 |
case HI6_LH: |
1109 |
case HI6_LHU: |
1110 |
case HI6_LW: |
1111 |
case HI6_LWU: |
1112 |
case HI6_LD: |
1113 |
case HI6_LQ_MDMX: |
1114 |
case HI6_LWC1: |
1115 |
case HI6_LWC2: |
1116 |
case HI6_LWC3: |
1117 |
case HI6_LDC1: |
1118 |
case HI6_LDC2: |
1119 |
case HI6_LL: |
1120 |
case HI6_LLD: |
1121 |
case HI6_SB: |
1122 |
case HI6_SH: |
1123 |
case HI6_SW: |
1124 |
case HI6_SD: |
1125 |
case HI6_SQ_SPECIAL3: |
1126 |
case HI6_SC: |
1127 |
case HI6_SCD: |
1128 |
case HI6_SWC1: |
1129 |
case HI6_SWC2: |
1130 |
case HI6_SWC3: |
1131 |
case HI6_SDC1: |
1132 |
case HI6_SDC2: |
1133 |
case HI6_LWL: |
1134 |
case HI6_LWR: |
1135 |
case HI6_LDL: |
1136 |
case HI6_LDR: |
1137 |
case HI6_SWL: |
1138 |
case HI6_SWR: |
1139 |
case HI6_SDL: |
1140 |
case HI6_SDR: |
1141 |
if (hi6 == HI6_LQ_MDMX && |
1142 |
cpu->cd.mips.cpu_type.rev != MIPS_R5900) { |
1143 |
debug("mdmx\t(UNIMPLEMENTED)"); |
1144 |
break; |
1145 |
} |
1146 |
if (hi6 == HI6_SQ_SPECIAL3 && |
1147 |
cpu->cd.mips.cpu_type.rev != MIPS_R5900) { |
1148 |
special6 = instr[0] & 0x3f; |
1149 |
debug("%s", special3_names[special6]); |
1150 |
rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7); |
1151 |
rt = instr[2] & 31; |
1152 |
rd = (instr[1] >> 3) & 31; |
1153 |
|
1154 |
switch (special6) { |
1155 |
|
1156 |
case SPECIAL3_RDHWR: |
1157 |
debug("\t%s", regname(cpu->machine, rt)); |
1158 |
debug(",hwr%i", rd); |
1159 |
break; |
1160 |
|
1161 |
default: |
1162 |
debug("\t(UNIMPLEMENTED)"); |
1163 |
} |
1164 |
break; |
1165 |
} |
1166 |
|
1167 |
rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7); |
1168 |
rt = instr[2] & 31; |
1169 |
imm = (instr[1] << 8) + instr[0]; |
1170 |
if (imm >= 32768) |
1171 |
imm -= 65536; |
1172 |
symbol = get_symbol_name(&cpu->machine->symbol_context, |
1173 |
cpu->cd.mips.gpr[rs] + imm, &offset); |
1174 |
|
1175 |
/* LWC3 is PREF in the newer ISA levels: */ |
1176 |
/* TODO: Which ISAs? IV? V? 32? 64? */ |
1177 |
if (cpu->cd.mips.cpu_type.isa_level >= 4 && hi6 == HI6_LWC3) { |
1178 |
debug("pref\t0x%x,%i(%s)", |
1179 |
rt, imm, regname(cpu->machine, rs)); |
1180 |
|
1181 |
if (running) { |
1182 |
debug("\t[0x%016"PRIx64" = %s]", |
1183 |
(uint64_t)(cpu->cd.mips.gpr[rs] + imm)); |
1184 |
if (symbol != NULL) |
1185 |
debug(" = %s", symbol); |
1186 |
debug("]"); |
1187 |
} |
1188 |
goto disasm_ret; |
1189 |
} |
1190 |
|
1191 |
debug("%s\t", hi6_names[hi6]); |
1192 |
|
1193 |
if (hi6 == HI6_SWC1 || hi6 == HI6_SWC2 || hi6 == HI6_SWC3 || |
1194 |
hi6 == HI6_SDC1 || hi6 == HI6_SDC2 || |
1195 |
hi6 == HI6_LWC1 || hi6 == HI6_LWC2 || hi6 == HI6_LWC3 || |
1196 |
hi6 == HI6_LDC1 || hi6 == HI6_LDC2) |
1197 |
debug("r%i", rt); |
1198 |
else |
1199 |
debug("%s", regname(cpu->machine, rt)); |
1200 |
|
1201 |
debug(",%i(%s)", imm, regname(cpu->machine, rs)); |
1202 |
|
1203 |
if (running) { |
1204 |
debug("\t["); |
1205 |
|
1206 |
if (cpu->is_32bit) |
1207 |
debug("0x%08"PRIx32, |
1208 |
(uint32_t) (cpu->cd.mips.gpr[rs] + imm)); |
1209 |
else |
1210 |
debug("0x%016"PRIx64, |
1211 |
(uint64_t) (cpu->cd.mips.gpr[rs] + imm)); |
1212 |
|
1213 |
if (symbol != NULL) |
1214 |
debug(" = %s", symbol); |
1215 |
|
1216 |
/* TODO: In some cases, it is possible to peek into |
1217 |
memory, and display that data here, like for the |
1218 |
other emulation modes. */ |
1219 |
|
1220 |
debug("]"); |
1221 |
} |
1222 |
break; |
1223 |
|
1224 |
case HI6_J: |
1225 |
case HI6_JAL: |
1226 |
imm = (((instr[3] & 3) << 24) + (instr[2] << 16) + |
1227 |
(instr[1] << 8) + instr[0]) << 2; |
1228 |
addr = (dumpaddr + 4) & ~((1 << 28) - 1); |
1229 |
addr |= imm; |
1230 |
symbol = get_symbol_name(&cpu->machine->symbol_context, |
1231 |
addr, &offset); |
1232 |
debug("%s\t0x", hi6_names[hi6]); |
1233 |
if (cpu->is_32bit) |
1234 |
debug("%08"PRIx32, (uint32_t) addr); |
1235 |
else |
1236 |
debug("%016"PRIx64, (uint64_t) addr); |
1237 |
if (symbol != NULL) |
1238 |
debug("\t<%s>", symbol); |
1239 |
break; |
1240 |
|
1241 |
case HI6_COP0: |
1242 |
case HI6_COP1: |
1243 |
case HI6_COP2: |
1244 |
case HI6_COP3: |
1245 |
imm = (instr[3] << 24) + (instr[2] << 16) + |
1246 |
(instr[1] << 8) + instr[0]; |
1247 |
imm &= ((1 << 26) - 1); |
1248 |
|
1249 |
/* Call coproc_function(), but ONLY disassembly, no exec: */ |
1250 |
coproc_function(cpu, cpu->cd.mips.coproc[hi6 - HI6_COP0], |
1251 |
hi6 - HI6_COP0, imm, 1, running); |
1252 |
return sizeof(instrword); |
1253 |
|
1254 |
case HI6_CACHE: |
1255 |
rt = ((instr[3] & 3) << 3) + (instr[2] >> 5); /* base */ |
1256 |
copz = instr[2] & 31; |
1257 |
imm = (instr[1] << 8) + instr[0]; |
1258 |
cache_op = copz >> 2; |
1259 |
which_cache = copz & 3; |
1260 |
showtag = 0; |
1261 |
debug("cache\t0x%02x,0x%04x(%s)", copz, imm, |
1262 |
regname(cpu->machine, rt)); |
1263 |
if (which_cache==0) debug(" [ primary I-cache"); |
1264 |
if (which_cache==1) debug(" [ primary D-cache"); |
1265 |
if (which_cache==2) debug(" [ secondary I-cache"); |
1266 |
if (which_cache==3) debug(" [ secondary D-cache"); |
1267 |
debug(", "); |
1268 |
if (cache_op==0) debug("index invalidate"); |
1269 |
if (cache_op==1) debug("index load tag"); |
1270 |
if (cache_op==2) debug("index store tag"), showtag=1; |
1271 |
if (cache_op==3) debug("create dirty exclusive"); |
1272 |
if (cache_op==4) debug("hit invalidate"); |
1273 |
if (cache_op==5) debug("fill OR hit writeback invalidate"); |
1274 |
if (cache_op==6) debug("hit writeback"); |
1275 |
if (cache_op==7) debug("hit set virtual"); |
1276 |
if (running) |
1277 |
debug(", addr 0x%016"PRIx64, |
1278 |
(uint64_t)(cpu->cd.mips.gpr[rt] + imm)); |
1279 |
if (showtag) |
1280 |
debug(", taghi=%08lx lo=%08lx", |
1281 |
(long)cpu->cd.mips.coproc[0]->reg[COP0_TAGDATA_HI], |
1282 |
(long)cpu->cd.mips.coproc[0]->reg[COP0_TAGDATA_LO]); |
1283 |
debug(" ]"); |
1284 |
break; |
1285 |
|
1286 |
case HI6_SPECIAL2: |
1287 |
special6 = instr[0] & 0x3f; |
1288 |
instrword = (instr[3] << 24) + (instr[2] << 16) + |
1289 |
(instr[1] << 8) + instr[0]; |
1290 |
rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7); |
1291 |
rt = instr[2] & 31; |
1292 |
rd = (instr[1] >> 3) & 31; |
1293 |
|
1294 |
if (cpu->cd.mips.cpu_type.rev == MIPS_R5900) { |
1295 |
int c790mmifunc = (instrword >> 6) & 0x1f; |
1296 |
if (special6 != MMI_MMI0 && special6 != MMI_MMI1 && |
1297 |
special6 != MMI_MMI2 && special6 != MMI_MMI3) |
1298 |
debug("%s\t", mmi_names[special6]); |
1299 |
|
1300 |
switch (special6) { |
1301 |
|
1302 |
case MMI_MADD: |
1303 |
case MMI_MADDU: |
1304 |
if (rd != MIPS_GPR_ZERO) { |
1305 |
debug("%s,", regname(cpu->machine, rd)); |
1306 |
} |
1307 |
debug("%s", regname(cpu->machine, rs)); |
1308 |
debug(",%s", regname(cpu->machine, rt)); |
1309 |
break; |
1310 |
|
1311 |
case MMI_MMI0: |
1312 |
debug("%s\t", mmi0_names[c790mmifunc]); |
1313 |
switch (c790mmifunc) { |
1314 |
|
1315 |
case MMI0_PEXTLB: |
1316 |
case MMI0_PEXTLH: |
1317 |
case MMI0_PEXTLW: |
1318 |
case MMI0_PMAXH: |
1319 |
case MMI0_PMAXW: |
1320 |
case MMI0_PPACB: |
1321 |
case MMI0_PPACH: |
1322 |
case MMI0_PPACW: |
1323 |
debug("%s", regname(cpu->machine, rd)); |
1324 |
debug(",%s", regname(cpu->machine, rs)); |
1325 |
debug(",%s", regname(cpu->machine, rt)); |
1326 |
break; |
1327 |
|
1328 |
default:debug("(UNIMPLEMENTED)"); |
1329 |
} |
1330 |
break; |
1331 |
|
1332 |
case MMI_MMI1: |
1333 |
debug("%s\t", mmi1_names[c790mmifunc]); |
1334 |
switch (c790mmifunc) { |
1335 |
|
1336 |
case MMI1_PEXTUB: |
1337 |
case MMI1_PEXTUH: |
1338 |
case MMI1_PEXTUW: |
1339 |
case MMI1_PMINH: |
1340 |
case MMI1_PMINW: |
1341 |
debug("%s", regname(cpu->machine, rd)); |
1342 |
debug(",%s", regname(cpu->machine, rs)); |
1343 |
debug(",%s", regname(cpu->machine, rt)); |
1344 |
break; |
1345 |
|
1346 |
default:debug("(UNIMPLEMENTED)"); |
1347 |
} |
1348 |
break; |
1349 |
|
1350 |
case MMI_MMI2: |
1351 |
debug("%s\t", mmi2_names[c790mmifunc]); |
1352 |
switch (c790mmifunc) { |
1353 |
|
1354 |
case MMI2_PMFHI: |
1355 |
case MMI2_PMFLO: |
1356 |
debug("%s", regname(cpu->machine, rd)); |
1357 |
break; |
1358 |
|
1359 |
case MMI2_PHMADH: |
1360 |
case MMI2_PHMSBH: |
1361 |
case MMI2_PINTH: |
1362 |
case MMI2_PMADDH: |
1363 |
case MMI2_PMADDW: |
1364 |
case MMI2_PMSUBH: |
1365 |
case MMI2_PMSUBW: |
1366 |
case MMI2_PMULTH: |
1367 |
case MMI2_PMULTW: |
1368 |
case MMI2_PSLLVW: |
1369 |
debug("%s", regname(cpu->machine, rd)); |
1370 |
debug(",%s", regname(cpu->machine, rs)); |
1371 |
debug(",%s", regname(cpu->machine, rt)); |
1372 |
break; |
1373 |
|
1374 |
default:debug("(UNIMPLEMENTED)"); |
1375 |
} |
1376 |
break; |
1377 |
|
1378 |
case MMI_MMI3: |
1379 |
debug("%s\t", mmi3_names[c790mmifunc]); |
1380 |
switch (c790mmifunc) { |
1381 |
|
1382 |
case MMI3_PMTHI: |
1383 |
case MMI3_PMTLO: |
1384 |
debug("%s", regname(cpu->machine, rs)); |
1385 |
break; |
1386 |
|
1387 |
case MMI3_PINTEH: |
1388 |
case MMI3_PMADDUW: |
1389 |
case MMI3_PMULTUW: |
1390 |
case MMI3_PNOR: |
1391 |
case MMI3_POR: |
1392 |
case MMI3_PSRAVW: |
1393 |
debug("%s", regname(cpu->machine, rd)); |
1394 |
debug(",%s", regname(cpu->machine, rs)); |
1395 |
debug(",%s", regname(cpu->machine, rt)); |
1396 |
break; |
1397 |
|
1398 |
default:debug("(UNIMPLEMENTED)"); |
1399 |
} |
1400 |
break; |
1401 |
|
1402 |
default:debug("(UNIMPLEMENTED)"); |
1403 |
} |
1404 |
break; |
1405 |
} |
1406 |
|
1407 |
/* SPECIAL2: */ |
1408 |
debug("%s\t", special2_names[special6]); |
1409 |
|
1410 |
switch (special6) { |
1411 |
|
1412 |
case SPECIAL2_MADD: |
1413 |
case SPECIAL2_MADDU: |
1414 |
case SPECIAL2_MSUB: |
1415 |
case SPECIAL2_MSUBU: |
1416 |
if (rd != MIPS_GPR_ZERO) { |
1417 |
debug("WEIRD_NONZERO_RD(%s),", |
1418 |
regname(cpu->machine, rd)); |
1419 |
} |
1420 |
debug("%s", regname(cpu->machine, rs)); |
1421 |
debug(",%s", regname(cpu->machine, rt)); |
1422 |
break; |
1423 |
|
1424 |
case SPECIAL2_MUL: |
1425 |
/* Apparently used both on R5900 and MIPS32: */ |
1426 |
debug("%s", regname(cpu->machine, rd)); |
1427 |
debug(",%s", regname(cpu->machine, rs)); |
1428 |
debug(",%s", regname(cpu->machine, rt)); |
1429 |
break; |
1430 |
|
1431 |
case SPECIAL2_CLZ: |
1432 |
case SPECIAL2_CLO: |
1433 |
case SPECIAL2_DCLZ: |
1434 |
case SPECIAL2_DCLO: |
1435 |
debug("%s", regname(cpu->machine, rd)); |
1436 |
debug(",%s", regname(cpu->machine, rs)); |
1437 |
break; |
1438 |
|
1439 |
default: |
1440 |
debug("(UNIMPLEMENTED)"); |
1441 |
} |
1442 |
break; |
1443 |
|
1444 |
case HI6_REGIMM: |
1445 |
regimm5 = instr[2] & 0x1f; |
1446 |
switch (regimm5) { |
1447 |
case REGIMM_BLTZ: |
1448 |
case REGIMM_BGEZ: |
1449 |
case REGIMM_BLTZL: |
1450 |
case REGIMM_BGEZL: |
1451 |
case REGIMM_BLTZAL: |
1452 |
case REGIMM_BLTZALL: |
1453 |
case REGIMM_BGEZAL: |
1454 |
case REGIMM_BGEZALL: |
1455 |
rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7); |
1456 |
imm = (instr[1] << 8) + instr[0]; |
1457 |
if (imm >= 32768) |
1458 |
imm -= 65536; |
1459 |
|
1460 |
debug("%s\t%s,", regimm_names[regimm5], |
1461 |
regname(cpu->machine, rs)); |
1462 |
|
1463 |
addr = (dumpaddr + 4) + (imm << 2); |
1464 |
|
1465 |
if (cpu->is_32bit) |
1466 |
debug("0x%08"PRIx32, (uint32_t) addr); |
1467 |
else |
1468 |
debug("0x%016"PRIx64, (uint64_t) addr); |
1469 |
break; |
1470 |
default: |
1471 |
debug("unimplemented regimm5 = 0x%02x", regimm5); |
1472 |
} |
1473 |
break; |
1474 |
default: |
1475 |
debug("unimplemented hi6 = 0x%02x", hi6); |
1476 |
} |
1477 |
|
1478 |
disasm_ret: |
1479 |
debug("\n"); |
1480 |
return sizeof(instrword); |
1481 |
} |
1482 |
|
1483 |
|
1484 |
/* |
1485 |
* mips_cpu_register_dump(): |
1486 |
* |
1487 |
* Dump cpu registers in a relatively readable format. |
1488 |
* |
1489 |
* gprs: set to non-zero to dump GPRs and hi/lo/pc |
1490 |
* coprocs: set bit 0..3 to dump registers in coproc 0..3. |
1491 |
*/ |
1492 |
void mips_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs) |
1493 |
{ |
1494 |
int coprocnr, i, bits32; |
1495 |
uint64_t offset; |
1496 |
char *symbol; |
1497 |
int bits128 = cpu->cd.mips.cpu_type.rev == MIPS_R5900; |
1498 |
|
1499 |
bits32 = cpu->is_32bit; |
1500 |
|
1501 |
if (gprs) { |
1502 |
/* Special registers (pc, hi/lo) first: */ |
1503 |
symbol = get_symbol_name(&cpu->machine->symbol_context, |
1504 |
cpu->pc, &offset); |
1505 |
|
1506 |
if (bits32) |
1507 |
debug("cpu%i: pc = %08"PRIx32, |
1508 |
cpu->cpu_id, (uint32_t) cpu->pc); |
1509 |
else if (bits128) |
1510 |
debug("cpu%i: pc=%016"PRIx64, |
1511 |
cpu->cpu_id, (uint64_t) cpu->pc); |
1512 |
else |
1513 |
debug("cpu%i: pc = 0x%016"PRIx64, |
1514 |
cpu->cpu_id, (uint64_t) cpu->pc); |
1515 |
|
1516 |
debug(" <%s>\n", symbol != NULL? symbol : |
1517 |
" no symbol "); |
1518 |
|
1519 |
if (bits32) |
1520 |
debug("cpu%i: hi = %08"PRIx32" lo = %08"PRIx32"\n", |
1521 |
cpu->cpu_id, (uint32_t) cpu->cd.mips.hi, |
1522 |
(uint32_t) cpu->cd.mips.lo); |
1523 |
else if (bits128) { |
1524 |
debug("cpu%i: hi=%016"PRIx64"%016"PRIx64" lo=" |
1525 |
"%016"PRIx64"%016"PRIx64"\n", cpu->cpu_id, |
1526 |
cpu->cd.mips.hi1, cpu->cd.mips.hi, |
1527 |
cpu->cd.mips.lo1, cpu->cd.mips.lo); |
1528 |
} else { |
1529 |
debug("cpu%i: hi = 0x%016"PRIx64" lo = 0x%016" |
1530 |
PRIx64"\n", cpu->cpu_id, |
1531 |
(uint64_t) cpu->cd.mips.hi, |
1532 |
(uint64_t) cpu->cd.mips.lo); |
1533 |
} |
1534 |
|
1535 |
/* General registers: */ |
1536 |
if (bits128) { |
1537 |
/* 128-bit: */ |
1538 |
for (i=0; i<32; i++) { |
1539 |
int r = (i >> 1) + ((i & 1) << 4); |
1540 |
if ((i & 1) == 0) |
1541 |
debug("cpu%i:", cpu->cpu_id); |
1542 |
if (r == MIPS_GPR_ZERO) |
1543 |
debug(" " |
1544 |
" "); |
1545 |
else |
1546 |
debug(" %3s=%016"PRIx64"%016"PRIx64, |
1547 |
regname(cpu->machine, r), |
1548 |
(uint64_t)cpu->cd.mips.gpr_quadhi[r], |
1549 |
(uint64_t)cpu->cd.mips.gpr[r]); |
1550 |
if ((i & 1) == 1) |
1551 |
debug("\n"); |
1552 |
} |
1553 |
} else if (bits32) { |
1554 |
/* 32-bit: */ |
1555 |
for (i=0; i<32; i++) { |
1556 |
if ((i & 3) == 0) |
1557 |
debug("cpu%i:", cpu->cpu_id); |
1558 |
if (i == MIPS_GPR_ZERO) |
1559 |
debug(" "); |
1560 |
else |
1561 |
debug(" %3s = %08"PRIx32, |
1562 |
regname(cpu->machine, i), |
1563 |
(uint32_t)cpu->cd.mips.gpr[i]); |
1564 |
if ((i & 3) == 3) |
1565 |
debug("\n"); |
1566 |
} |
1567 |
} else { |
1568 |
/* 64-bit: */ |
1569 |
for (i=0; i<32; i++) { |
1570 |
int r = (i >> 1) + ((i & 1) << 4); |
1571 |
if ((i & 1) == 0) |
1572 |
debug("cpu%i:", cpu->cpu_id); |
1573 |
if (r == MIPS_GPR_ZERO) |
1574 |
debug(" "); |
1575 |
else |
1576 |
debug(" %3s = 0x%016"PRIx64, |
1577 |
regname(cpu->machine, r), |
1578 |
(uint64_t)cpu->cd.mips.gpr[r]); |
1579 |
if ((i & 1) == 1) |
1580 |
debug("\n"); |
1581 |
} |
1582 |
} |
1583 |
} |
1584 |
|
1585 |
for (coprocnr=0; coprocnr<4; coprocnr++) { |
1586 |
int nm1 = 1; |
1587 |
|
1588 |
if (bits32) |
1589 |
nm1 = 3; |
1590 |
|
1591 |
if (!(coprocs & (1<<coprocnr))) |
1592 |
continue; |
1593 |
if (cpu->cd.mips.coproc[coprocnr] == NULL) { |
1594 |
debug("cpu%i: no coprocessor %i\n", |
1595 |
cpu->cpu_id, coprocnr); |
1596 |
continue; |
1597 |
} |
1598 |
|
1599 |
/* Coprocessor registers: */ |
1600 |
/* TODO: multiple selections per register? */ |
1601 |
for (i=0; i<32; i++) { |
1602 |
/* 32-bit: */ |
1603 |
if ((i & nm1) == 0) |
1604 |
debug("cpu%i:", cpu->cpu_id); |
1605 |
|
1606 |
if (cpu->machine->show_symbolic_register_names && |
1607 |
coprocnr == 0) |
1608 |
debug(" %8s", cop0_names[i]); |
1609 |
else |
1610 |
debug(" c%i,%02i", coprocnr, i); |
1611 |
|
1612 |
if (bits32) |
1613 |
debug("=%08x", (int)cpu->cd.mips.coproc[coprocnr]->reg[i]); |
1614 |
else { |
1615 |
if (coprocnr == 0 && (i == COP0_COUNT |
1616 |
|| i == COP0_COMPARE || i == COP0_INDEX |
1617 |
|| i == COP0_RANDOM || i == COP0_WIRED)) |
1618 |
debug(" = 0x%08x", (int)cpu->cd.mips.coproc[coprocnr]->reg[i]); |
1619 |
else |
1620 |
debug(" = 0x%016"PRIx64, (uint64_t) |
1621 |
cpu->cd.mips.coproc[coprocnr]->reg[i]); |
1622 |
} |
1623 |
|
1624 |
if ((i & nm1) == nm1) |
1625 |
debug("\n"); |
1626 |
|
1627 |
/* Skip the last 16 cop0 registers on R3000 etc. */ |
1628 |
if (coprocnr == 0 && cpu->cd.mips.cpu_type.isa_level < 3 |
1629 |
&& i == 15) |
1630 |
i = 31; |
1631 |
} |
1632 |
|
1633 |
if (coprocnr == 0 && cpu->cd.mips.cpu_type.isa_level >= 32) { |
1634 |
debug("cpu%i: ", cpu->cpu_id); |
1635 |
debug("config_select1 = 0x"); |
1636 |
if (cpu->is_32bit) |
1637 |
debug("%08"PRIx32, (uint32_t)cpu->cd.mips.cop0_config_select1); |
1638 |
else |
1639 |
debug("%016"PRIx64, (uint64_t)cpu->cd.mips.cop0_config_select1); |
1640 |
debug("\n"); |
1641 |
} |
1642 |
|
1643 |
/* Floating point control registers: */ |
1644 |
if (coprocnr == 1) { |
1645 |
for (i=0; i<32; i++) |
1646 |
switch (i) { |
1647 |
case MIPS_FPU_FCIR: |
1648 |
printf("cpu%i: fcr0 (fcir) = 0x%08x\n", |
1649 |
cpu->cpu_id, (int)cpu->cd.mips. |
1650 |
coproc[coprocnr]->fcr[i]); |
1651 |
break; |
1652 |
case MIPS_FPU_FCCR: |
1653 |
printf("cpu%i: fcr25 (fccr) = 0x%08x\n", |
1654 |
cpu->cpu_id, (int)cpu->cd.mips. |
1655 |
coproc[coprocnr]->fcr[i]); |
1656 |
break; |
1657 |
case MIPS_FPU_FCSR: |
1658 |
printf("cpu%i: fcr31 (fcsr) = 0x%08x\n", |
1659 |
cpu->cpu_id, (int)cpu->cd.mips. |
1660 |
coproc[coprocnr]->fcr[i]); |
1661 |
break; |
1662 |
} |
1663 |
} |
1664 |
} |
1665 |
|
1666 |
if (cpu->cd.mips.rmw) { |
1667 |
printf("cpu%i: Read-Modify-Write in progress, address " |
1668 |
"0x%016"PRIx64"\n", cpu->cpu_id, cpu->cd.mips.rmw_addr); |
1669 |
} |
1670 |
} |
1671 |
|
1672 |
|
1673 |
static void add_response_word(struct cpu *cpu, char *r, uint64_t value, |
1674 |
size_t maxlen, int len) |
1675 |
{ |
1676 |
char *format = (len == 4)? "%08"PRIx64 : "%016"PRIx64; |
1677 |
if (len == 4) |
1678 |
value &= 0xffffffffULL; |
1679 |
if (cpu->byte_order == EMUL_LITTLE_ENDIAN) { |
1680 |
if (len == 4) { |
1681 |
value = ((value & 0xff) << 24) + |
1682 |
((value & 0xff00) << 8) + |
1683 |
((value & 0xff0000) >> 8) + |
1684 |
((value & 0xff000000) >> 24); |
1685 |
} else { |
1686 |
value = ((value & 0xff) << 56) + |
1687 |
((value & 0xff00) << 40) + |
1688 |
((value & 0xff0000) << 24) + |
1689 |
((value & 0xff000000ULL) << 8) + |
1690 |
((value & 0xff00000000ULL) >> 8) + |
1691 |
((value & 0xff0000000000ULL) >> 24) + |
1692 |
((value & 0xff000000000000ULL) >> 40) + |
1693 |
((value & 0xff00000000000000ULL) >> 56); |
1694 |
} |
1695 |
} |
1696 |
snprintf(r + strlen(r), maxlen - strlen(r), format, (uint64_t)value); |
1697 |
} |
1698 |
|
1699 |
|
1700 |
/* |
1701 |
* mips_cpu_gdb_stub(): |
1702 |
* |
1703 |
* Execute a "remote GDB" command. Returns 1 on success, 0 on error. |
1704 |
*/ |
1705 |
char *mips_cpu_gdb_stub(struct cpu *cpu, char *cmd) |
1706 |
{ |
1707 |
if (strcmp(cmd, "g") == 0) { |
1708 |
/* 76 registers: gprs, sr, lo, hi, badvaddr, cause, pc, |
1709 |
fprs, fsr, fir, fp. */ |
1710 |
int i; |
1711 |
char *r; |
1712 |
size_t wlen = cpu->is_32bit? |
1713 |
sizeof(uint32_t) : sizeof(uint64_t); |
1714 |
size_t len = 1 + 76 * wlen; |
1715 |
r = malloc(len); |
1716 |
if (r == NULL) { |
1717 |
fprintf(stderr, "out of memory\n"); |
1718 |
exit(1); |
1719 |
} |
1720 |
r[0] = '\0'; |
1721 |
for (i=0; i<32; i++) |
1722 |
add_response_word(cpu, r, cpu->cd.mips.gpr[i], |
1723 |
len, wlen); |
1724 |
add_response_word(cpu, r, |
1725 |
cpu->cd.mips.coproc[0]->reg[COP0_STATUS], len, wlen); |
1726 |
add_response_word(cpu, r, cpu->cd.mips.lo, len, wlen); |
1727 |
add_response_word(cpu, r, cpu->cd.mips.hi, len, wlen); |
1728 |
add_response_word(cpu, r, |
1729 |
cpu->cd.mips.coproc[0]->reg[COP0_BADVADDR], len, wlen); |
1730 |
add_response_word(cpu, r, |
1731 |
cpu->cd.mips.coproc[0]->reg[COP0_CAUSE], len, wlen); |
1732 |
add_response_word(cpu, r, cpu->pc, len, wlen); |
1733 |
for (i=0; i<32; i++) |
1734 |
add_response_word(cpu, r, |
1735 |
cpu->cd.mips.coproc[1]->reg[i], len, wlen); |
1736 |
add_response_word(cpu, r, |
1737 |
cpu->cd.mips.coproc[1]->reg[31] /* fcsr */, len, wlen); |
1738 |
add_response_word(cpu, r, |
1739 |
cpu->cd.mips.coproc[1]->reg[0] /* fcir */, len, wlen); |
1740 |
|
1741 |
/* TODO: fp = gpr 30? */ |
1742 |
add_response_word(cpu, r, cpu->cd.mips.gpr[30], len, wlen); |
1743 |
|
1744 |
return r; |
1745 |
} |
1746 |
|
1747 |
if (cmd[0] == 'p') { |
1748 |
int regnr = strtol(cmd + 1, NULL, 16); |
1749 |
size_t wlen = cpu->is_32bit? sizeof(uint32_t):sizeof(uint64_t); |
1750 |
size_t len = 2 * wlen + 1; |
1751 |
char *r = malloc(len); |
1752 |
r[0] = '\0'; |
1753 |
if (regnr >= 0 && regnr <= 31) { |
1754 |
add_response_word(cpu, r, |
1755 |
cpu->cd.mips.gpr[regnr], len, wlen); |
1756 |
} else if (regnr == 0x20) { |
1757 |
add_response_word(cpu, r, cpu->cd.mips.coproc[0]-> |
1758 |
reg[COP0_STATUS], len, wlen); |
1759 |
} else if (regnr == 0x21) { |
1760 |
add_response_word(cpu, r, cpu->cd.mips.lo, len, wlen); |
1761 |
} else if (regnr == 0x22) { |
1762 |
add_response_word(cpu, r, cpu->cd.mips.hi, len, wlen); |
1763 |
} else if (regnr == 0x23) { |
1764 |
add_response_word(cpu, r, cpu->cd.mips.coproc[0]-> |
1765 |
reg[COP0_BADVADDR], len, wlen); |
1766 |
} else if (regnr == 0x24) { |
1767 |
add_response_word(cpu, r, cpu->cd.mips.coproc[0]-> |
1768 |
reg[COP0_CAUSE], len, wlen); |
1769 |
} else if (regnr == 0x25) { |
1770 |
add_response_word(cpu, r, cpu->pc, len, wlen); |
1771 |
} else if (regnr >= 0x26 && regnr <= 0x45 && |
1772 |
cpu->cd.mips.coproc[1] != NULL) { |
1773 |
add_response_word(cpu, r, cpu->cd.mips.coproc[1]-> |
1774 |
reg[regnr - 0x26], len, wlen); |
1775 |
} else if (regnr == 0x46) { |
1776 |
add_response_word(cpu, r, cpu->cd.mips.coproc[1]-> |
1777 |
fcr[MIPS_FPU_FCSR], len, wlen); |
1778 |
} else if (regnr == 0x47) { |
1779 |
add_response_word(cpu, r, cpu->cd.mips.coproc[1]-> |
1780 |
fcr[MIPS_FPU_FCIR], len, wlen); |
1781 |
} else { |
1782 |
/* Unimplemented: */ |
1783 |
add_response_word(cpu, r, 0xcc000 + regnr, len, wlen); |
1784 |
} |
1785 |
return r; |
1786 |
} |
1787 |
|
1788 |
fatal("mips_cpu_gdb_stub(): cmd='%s' TODO\n", cmd); |
1789 |
return NULL; |
1790 |
} |
1791 |
|
1792 |
|
1793 |
/* |
1794 |
* mips_cpu_interrupt(): |
1795 |
* |
1796 |
* Cause an interrupt. If irq_nr is 2..7, then it is a MIPS hardware |
1797 |
* interrupt. 0 and 1 are ignored (software interrupts). |
1798 |
* |
1799 |
* If irq_nr is >= 8, then this function calls md_interrupt(). |
1800 |
*/ |
1801 |
int mips_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr) |
1802 |
{ |
1803 |
if (irq_nr >= 8) { |
1804 |
if (cpu->machine->md_interrupt != NULL) |
1805 |
cpu->machine->md_interrupt(cpu->machine, |
1806 |
cpu, irq_nr, 1); |
1807 |
else |
1808 |
fatal("mips_cpu_interrupt(): irq_nr = %i, " |
1809 |
"but md_interrupt = NULL ?\n", irq_nr); |
1810 |
return 1; |
1811 |
} |
1812 |
|
1813 |
if (irq_nr < 2) |
1814 |
return 0; |
1815 |
|
1816 |
cpu->cd.mips.coproc[0]->reg[COP0_CAUSE] |= |
1817 |
((1 << irq_nr) << STATUS_IM_SHIFT); |
1818 |
|
1819 |
return 1; |
1820 |
} |
1821 |
|
1822 |
|
1823 |
/* |
1824 |
* mips_cpu_interrupt_ack(): |
1825 |
* |
1826 |
* Acknowledge an interrupt. If irq_nr is 2..7, then it is a MIPS hardware |
1827 |
* interrupt. Interrupts 0..1 are ignored (software interrupts). |
1828 |
* |
1829 |
* If irq_nr is >= 8, then it is machine dependent, and md_interrupt() is |
1830 |
* called. |
1831 |
*/ |
1832 |
int mips_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr) |
1833 |
{ |
1834 |
if (irq_nr >= 8) { |
1835 |
if (cpu->machine->md_interrupt != NULL) |
1836 |
cpu->machine->md_interrupt(cpu->machine, cpu, |
1837 |
irq_nr, 0); |
1838 |
else |
1839 |
fatal("mips_cpu_interrupt_ack(): irq_nr = %i, " |
1840 |
"but md_interrupt = NULL ?\n", irq_nr); |
1841 |
return 1; |
1842 |
} |
1843 |
|
1844 |
if (irq_nr < 2) |
1845 |
return 0; |
1846 |
|
1847 |
cpu->cd.mips.coproc[0]->reg[COP0_CAUSE] &= |
1848 |
~((1 << irq_nr) << STATUS_IM_SHIFT); |
1849 |
|
1850 |
return 1; |
1851 |
} |
1852 |
|
1853 |
|
1854 |
/* |
1855 |
* mips_cpu_exception(): |
1856 |
* |
1857 |
* Cause an exception in a CPU. This sets a couple of coprocessor 0 |
1858 |
* registers, and the program counter. |
1859 |
* |
1860 |
* exccode the exception code |
1861 |
* tlb set to non-zero if the exception handler at |
1862 |
* 0x80000000 should be used. (normal = 0x80000180) |
1863 |
* vaddr virtual address (for some exceptions) |
1864 |
* coproc_nr coprocessor number (for some exceptions) |
1865 |
* vaddr_vpn2 vpn2 (for some exceptions) |
1866 |
* vaddr_asid asid (for some exceptions) |
1867 |
* x_64 non-zero for 64-bit mode for R4000-style tlb misses |
1868 |
*/ |
1869 |
void mips_cpu_exception(struct cpu *cpu, int exccode, int tlb, uint64_t vaddr, |
1870 |
int coproc_nr, uint64_t vaddr_vpn2, int vaddr_asid, int x_64) |
1871 |
{ |
1872 |
uint64_t base; |
1873 |
uint64_t *reg = &cpu->cd.mips.coproc[0]->reg[0]; |
1874 |
int exc_model = cpu->cd.mips.cpu_type.exc_model; |
1875 |
|
1876 |
if (!quiet_mode) { |
1877 |
uint64_t offset; |
1878 |
int x; |
1879 |
char *symbol = get_symbol_name(&cpu->machine->symbol_context, |
1880 |
cpu->pc, &offset); |
1881 |
|
1882 |
debug("[ "); |
1883 |
if (cpu->machine->ncpus > 1) |
1884 |
debug("cpu%i: ", cpu->cpu_id); |
1885 |
|
1886 |
debug("exception %s%s", |
1887 |
exception_names[exccode], tlb? " <tlb>" : ""); |
1888 |
|
1889 |
switch (exccode) { |
1890 |
|
1891 |
case EXCEPTION_INT: |
1892 |
debug(" cause_im=0x%02x", (int)((reg[COP0_CAUSE] & CAUSE_IP_MASK) >> CAUSE_IP_SHIFT)); |
1893 |
break; |
1894 |
|
1895 |
case EXCEPTION_SYS: |
1896 |
debug(" v0=%i", (int)cpu->cd.mips.gpr[MIPS_GPR_V0]); |
1897 |
for (x=0; x<4; x++) { |
1898 |
int64_t d = cpu->cd.mips.gpr[MIPS_GPR_A0 + x]; |
1899 |
char strbuf[30]; |
1900 |
|
1901 |
if (d > -256 && d < 256) { |
1902 |
debug(" a%i=%i", x, (int)d); |
1903 |
} else if (memory_points_to_string(cpu, |
1904 |
cpu->mem, d, 1)) { |
1905 |
debug(" a%i=\"%s\"", x, |
1906 |
memory_conv_to_string(cpu, cpu->mem, |
1907 |
d, strbuf, sizeof(strbuf))); |
1908 |
} else { |
1909 |
if (cpu->is_32bit) |
1910 |
debug(" a%i=0x%"PRIx32, x, |
1911 |
(uint32_t)d); |
1912 |
else |
1913 |
debug(" a%i=0x%"PRIx64, x, |
1914 |
(uint64_t)d); |
1915 |
} |
1916 |
} |
1917 |
break; |
1918 |
|
1919 |
case EXCEPTION_CPU: |
1920 |
debug(" coproc_nr=%i", coproc_nr); |
1921 |
break; |
1922 |
|
1923 |
default: |
1924 |
if (cpu->is_32bit) |
1925 |
debug(" vaddr=0x%08x", (int)vaddr); |
1926 |
else |
1927 |
debug(" vaddr=0x%016"PRIx64, (uint64_t)vaddr); |
1928 |
} |
1929 |
|
1930 |
if (cpu->is_32bit) |
1931 |
debug(" pc=0x%08"PRIx32" ", (uint32_t)cpu->pc); |
1932 |
else |
1933 |
debug(" pc=0x%016"PRIx64" ", (uint64_t)cpu->pc); |
1934 |
|
1935 |
if (symbol != NULL) |
1936 |
debug("<%s> ]\n", symbol); |
1937 |
else |
1938 |
debug("]\n"); |
1939 |
} |
1940 |
|
1941 |
if (tlb && vaddr < 0x1000) { |
1942 |
uint64_t offset; |
1943 |
char *symbol = get_symbol_name(&cpu->machine->symbol_context, |
1944 |
cpu->pc, &offset); |
1945 |
fatal("[ "); |
1946 |
if (cpu->machine->ncpus > 1) |
1947 |
fatal("cpu%i: ", cpu->cpu_id); |
1948 |
fatal("warning: LOW reference: vaddr="); |
1949 |
if (cpu->is_32bit) |
1950 |
fatal("0x%08"PRIx32, (uint32_t) vaddr); |
1951 |
else |
1952 |
fatal("0x%016"PRIx64, (uint64_t) vaddr); |
1953 |
fatal(", exception %s, pc=", exception_names[exccode]); |
1954 |
if (cpu->is_32bit) |
1955 |
fatal("0x%08"PRIx32, (uint32_t) cpu->pc); |
1956 |
else |
1957 |
fatal("0x%016"PRIx64, (uint64_t)cpu->pc); |
1958 |
fatal(" <%s> ]\n", symbol? symbol : "(no symbol)"); |
1959 |
} |
1960 |
|
1961 |
/* Clear the exception code bits of the cause register... */ |
1962 |
if (exc_model == EXC3K) |
1963 |
reg[COP0_CAUSE] &= ~R2K3K_CAUSE_EXCCODE_MASK; |
1964 |
else |
1965 |
reg[COP0_CAUSE] &= ~CAUSE_EXCCODE_MASK; |
1966 |
|
1967 |
/* ... and OR in the exception code: */ |
1968 |
reg[COP0_CAUSE] |= (exccode << CAUSE_EXCCODE_SHIFT); |
1969 |
|
1970 |
/* Always set CE (according to the R5000 manual): */ |
1971 |
reg[COP0_CAUSE] &= ~CAUSE_CE_MASK; |
1972 |
reg[COP0_CAUSE] |= (coproc_nr << CAUSE_CE_SHIFT); |
1973 |
|
1974 |
if (tlb || (exccode >= EXCEPTION_MOD && exccode <= EXCEPTION_ADES) || |
1975 |
exccode == EXCEPTION_VCEI || exccode == EXCEPTION_VCED) { |
1976 |
reg[COP0_BADVADDR] = vaddr; |
1977 |
if (cpu->is_32bit) |
1978 |
reg[COP0_BADVADDR] = (int32_t)reg[COP0_BADVADDR]; |
1979 |
|
1980 |
if (exc_model == EXC3K) { |
1981 |
reg[COP0_CONTEXT] &= ~R2K3K_CONTEXT_BADVPN_MASK; |
1982 |
reg[COP0_CONTEXT] |= ((vaddr_vpn2 << R2K3K_CONTEXT_BADVPN_SHIFT) & R2K3K_CONTEXT_BADVPN_MASK); |
1983 |
|
1984 |
reg[COP0_ENTRYHI] = (vaddr & R2K3K_ENTRYHI_VPN_MASK) |
1985 |
| (vaddr_asid << R2K3K_ENTRYHI_ASID_SHIFT); |
1986 |
|
1987 |
/* Sign-extend: */ |
1988 |
reg[COP0_CONTEXT] = (int64_t)(int32_t)reg[COP0_CONTEXT]; |
1989 |
reg[COP0_ENTRYHI] = (int64_t)(int32_t)reg[COP0_ENTRYHI]; |
1990 |
} else { |
1991 |
if (cpu->cd.mips.cpu_type.rev == MIPS_R4100) { |
1992 |
reg[COP0_CONTEXT] &= ~CONTEXT_BADVPN2_MASK_R4100; |
1993 |
reg[COP0_CONTEXT] |= ((vaddr_vpn2 << CONTEXT_BADVPN2_SHIFT) & CONTEXT_BADVPN2_MASK_R4100); |
1994 |
|
1995 |
/* TODO: fix these */ |
1996 |
reg[COP0_XCONTEXT] &= ~XCONTEXT_R_MASK; |
1997 |
reg[COP0_XCONTEXT] &= ~XCONTEXT_BADVPN2_MASK; |
1998 |
reg[COP0_XCONTEXT] |= (vaddr_vpn2 << XCONTEXT_BADVPN2_SHIFT) & XCONTEXT_BADVPN2_MASK; |
1999 |
reg[COP0_XCONTEXT] |= ((vaddr >> 62) & 0x3) << XCONTEXT_R_SHIFT; |
2000 |
|
2001 |
/* reg[COP0_PAGEMASK] = cpu->cd.mips.coproc[0]->tlbs[0].mask & PAGEMASK_MASK; */ |
2002 |
|
2003 |
reg[COP0_ENTRYHI] = (vaddr & (ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK | 0x1800)) | vaddr_asid; |
2004 |
} else { |
2005 |
reg[COP0_CONTEXT] &= ~CONTEXT_BADVPN2_MASK; |
2006 |
reg[COP0_CONTEXT] |= ((vaddr_vpn2 << CONTEXT_BADVPN2_SHIFT) & CONTEXT_BADVPN2_MASK); |
2007 |
|
2008 |
reg[COP0_XCONTEXT] &= ~XCONTEXT_R_MASK; |
2009 |
reg[COP0_XCONTEXT] &= ~XCONTEXT_BADVPN2_MASK; |
2010 |
reg[COP0_XCONTEXT] |= (vaddr_vpn2 << XCONTEXT_BADVPN2_SHIFT) & XCONTEXT_BADVPN2_MASK; |
2011 |
reg[COP0_XCONTEXT] |= ((vaddr >> 62) & 0x3) << XCONTEXT_R_SHIFT; |
2012 |
|
2013 |
/* reg[COP0_PAGEMASK] = cpu->cd.mips.coproc[0]->tlbs[0].mask & PAGEMASK_MASK; */ |
2014 |
|
2015 |
if (cpu->cd.mips.cpu_type.mmu_model == MMU10K) |
2016 |
reg[COP0_ENTRYHI] = (vaddr & (ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK_R10K)) | vaddr_asid; |
2017 |
else |
2018 |
reg[COP0_ENTRYHI] = (vaddr & (ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK)) | vaddr_asid; |
2019 |
} |
2020 |
} |
2021 |
} |
2022 |
|
2023 |
if (exc_model != EXC3K && reg[COP0_STATUS] & STATUS_EXL) { |
2024 |
/* |
2025 |
* Don't set EPC if STATUS_EXL is set, for R4000 and up. |
2026 |
* This actually happens when running IRIX and Ultrix, when |
2027 |
* they handle interrupts and/or tlb updates, I think, so |
2028 |
* printing this with debug() looks better than with fatal(). |
2029 |
*/ |
2030 |
/* debug("[ warning: cpu%i exception while EXL is set," |
2031 |
" not setting EPC ]\n", cpu->cpu_id); */ |
2032 |
} else { |
2033 |
if (cpu->delay_slot || cpu->cd.mips.nullify_next) { |
2034 |
reg[COP0_EPC] = cpu->pc - 4; |
2035 |
reg[COP0_CAUSE] |= CAUSE_BD; |
2036 |
|
2037 |
/* TODO: Should the BD flag actually be set |
2038 |
on nullified slots? */ |
2039 |
} else { |
2040 |
reg[COP0_EPC] = cpu->pc; |
2041 |
reg[COP0_CAUSE] &= ~CAUSE_BD; |
2042 |
} |
2043 |
} |
2044 |
|
2045 |
if (cpu->delay_slot) |
2046 |
cpu->delay_slot = EXCEPTION_IN_DELAY_SLOT; |
2047 |
else |
2048 |
cpu->delay_slot = NOT_DELAYED; |
2049 |
|
2050 |
cpu->cd.mips.nullify_next = 0; |
2051 |
|
2052 |
/* TODO: This is true for MIPS64, but how about others? */ |
2053 |
if (reg[COP0_STATUS] & STATUS_BEV) |
2054 |
base = 0xffffffffbfc00200ULL; |
2055 |
else |
2056 |
base = 0xffffffff80000000ULL; |
2057 |
|
2058 |
switch (exc_model) { |
2059 |
case EXC3K: |
2060 |
/* Userspace tlb, vs others: */ |
2061 |
if (tlb && !(vaddr & 0x80000000ULL) && |
2062 |
(exccode == EXCEPTION_TLBL || exccode == EXCEPTION_TLBS) ) |
2063 |
cpu->pc = base + 0x000; |
2064 |
else |
2065 |
cpu->pc = base + 0x080; |
2066 |
break; |
2067 |
default: |
2068 |
/* |
2069 |
* These offsets are according to the MIPS64 manual, but |
2070 |
* should work with R4000 and the rest too (I hope). |
2071 |
* |
2072 |
* 0x000 TLB refill, if EXL=0 |
2073 |
* 0x080 64-bit XTLB refill, if EXL=0 |
2074 |
* 0x100 cache error (not implemented yet) |
2075 |
* 0x180 general exception |
2076 |
* 0x200 interrupt (if CAUSE_IV is set) |
2077 |
*/ |
2078 |
if (tlb && (exccode == EXCEPTION_TLBL || |
2079 |
exccode == EXCEPTION_TLBS) && |
2080 |
!(reg[COP0_STATUS] & STATUS_EXL)) { |
2081 |
if (x_64) |
2082 |
cpu->pc = base + 0x080; |
2083 |
else |
2084 |
cpu->pc = base + 0x000; |
2085 |
} else { |
2086 |
if (exccode == EXCEPTION_INT && |
2087 |
(reg[COP0_CAUSE] & CAUSE_IV)) |
2088 |
cpu->pc = base + 0x200; |
2089 |
else |
2090 |
cpu->pc = base + 0x180; |
2091 |
} |
2092 |
} |
2093 |
|
2094 |
if (exc_model == EXC3K) { |
2095 |
/* R{2,3}000: Shift the lowest 6 bits to the left two steps:*/ |
2096 |
reg[COP0_STATUS] = (reg[COP0_STATUS] & ~0x3f) + |
2097 |
((reg[COP0_STATUS] & 0xf) << 2); |
2098 |
} else { |
2099 |
/* R4000: */ |
2100 |
reg[COP0_STATUS] |= STATUS_EXL; |
2101 |
} |
2102 |
|
2103 |
/* Sign-extend: */ |
2104 |
reg[COP0_CAUSE] = (int64_t)(int32_t)reg[COP0_CAUSE]; |
2105 |
reg[COP0_STATUS] = (int64_t)(int32_t)reg[COP0_STATUS]; |
2106 |
|
2107 |
if (cpu->is_32bit) { |
2108 |
reg[COP0_EPC] = (int64_t)(int32_t)reg[COP0_EPC]; |
2109 |
mips32_pc_to_pointers(cpu); |
2110 |
} else { |
2111 |
mips_pc_to_pointers(cpu); |
2112 |
} |
2113 |
} |
2114 |
|
2115 |
|
2116 |
#include "memory_mips.c" |
2117 |
|
2118 |
|
2119 |
#include "tmp_mips_tail.c" |
2120 |
|