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/* |
/* |
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* Copyright (C) 2003-2005 Anders Gavare. All rights reserved. |
* Copyright (C) 2003-2006 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: cpu_mips.c,v 1.4 2005/10/07 23:13:51 debug Exp $ |
* $Id: cpu_mips.c,v 1.56 2006/06/22 13:22:41 debug Exp $ |
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* |
* |
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* MIPS core CPU emulation. |
* MIPS core CPU emulation. |
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*/ |
*/ |
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#include "../../config.h" |
#include "../../config.h" |
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#ifndef ENABLE_MIPS |
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#include "cpu_mips.h" |
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/* |
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* mips_cpu_family_init(): |
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* |
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* Bogus function. |
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*/ |
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int mips_cpu_family_init(struct cpu_family *fp) |
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{ |
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return 0; |
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} |
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/* TODO: Maybe it isn't very nice to have these global like this... */ |
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void mips_cpu_exception(struct cpu *cpu, int exccode, int tlb, uint64_t vaddr, |
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int coproc_nr, uint64_t vaddr_vpn2, int vaddr_asid, int x_64) { } |
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#else /* ENABLE_MIPS */ |
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#include "arcbios.h" |
#include "arcbios.h" |
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#include "bintrans.h" |
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#include "cop0.h" |
#include "cop0.h" |
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#include "cpu.h" |
#include "cpu.h" |
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#include "cpu_mips.h" |
#include "cpu_mips.h" |
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extern volatile int single_step; |
extern volatile int single_step; |
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extern int show_opcode_statistics; |
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extern int old_show_trace_tree; |
extern int old_show_trace_tree; |
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extern int old_instruction_trace; |
extern int old_instruction_trace; |
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extern int old_quiet_mode; |
extern int old_quiet_mode; |
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static char *regimm_names[] = REGIMM_NAMES; |
static char *regimm_names[] = REGIMM_NAMES; |
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static char *special_names[] = SPECIAL_NAMES; |
static char *special_names[] = SPECIAL_NAMES; |
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static char *special2_names[] = SPECIAL2_NAMES; |
static char *special2_names[] = SPECIAL2_NAMES; |
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static char *mmi_names[] = MMI_NAMES; |
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static char *mmi0_names[] = MMI0_NAMES; |
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static char *mmi1_names[] = MMI1_NAMES; |
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static char *mmi2_names[] = MMI2_NAMES; |
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static char *mmi3_names[] = MMI3_NAMES; |
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static char *special3_names[] = SPECIAL3_NAMES; |
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static char *regnames[] = MIPS_REGISTER_NAMES; |
static char *regnames[] = MIPS_REGISTER_NAMES; |
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static char *cop0_names[] = COP0_NAMES; |
static char *cop0_names[] = COP0_NAMES; |
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#include "cpu_mips16.c" |
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#define DYNTRANS_DUALMODE_32 |
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#define DYNTRANS_DELAYSLOT |
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#include "tmp_mips_head.c" |
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void mips_pc_to_pointers(struct cpu *); |
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void mips32_pc_to_pointers(struct cpu *); |
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/* |
/* |
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if (found == -1) |
if (found == -1) |
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return 0; |
return 0; |
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cpu->memory_rw = mips_memory_rw; |
cpu->memory_rw = mips_memory_rw; |
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cpu->cd.mips.cpu_type = cpu_type_defs[found]; |
cpu->cd.mips.cpu_type = cpu_type_defs[found]; |
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cpu->name = cpu->cd.mips.cpu_type.name; |
cpu->name = cpu->cd.mips.cpu_type.name; |
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cpu->byte_order = EMUL_LITTLE_ENDIAN; |
cpu->byte_order = EMUL_LITTLE_ENDIAN; |
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cpu->cd.mips.gpr[MIPS_GPR_SP] = INITIAL_STACK_POINTER; |
cpu->cd.mips.gpr[MIPS_GPR_SP] = INITIAL_STACK_POINTER; |
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cpu->update_translation_table = mips_update_translation_table; |
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cpu->invalidate_translation_caches_paddr = |
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mips_invalidate_translation_caches_paddr; |
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if (cpu->cd.mips.cpu_type.isa_level <= 2 || |
if (cpu->cd.mips.cpu_type.isa_level <= 2 || |
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cpu->cd.mips.cpu_type.isa_level == 32) |
cpu->cd.mips.cpu_type.isa_level == 32) |
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cpu->is_32bit = 1; |
cpu->is_32bit = 1; |
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if (cpu->is_32bit) { |
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cpu->update_translation_table = mips32_update_translation_table; |
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cpu->invalidate_translation_caches = |
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mips32_invalidate_translation_caches; |
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cpu->invalidate_code_translation = |
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mips32_invalidate_code_translation; |
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} else { |
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cpu->update_translation_table = mips_update_translation_table; |
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cpu->invalidate_translation_caches = |
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mips_invalidate_translation_caches; |
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cpu->invalidate_code_translation = |
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mips_invalidate_code_translation; |
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} |
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cpu->instruction_has_delayslot = mips_cpu_instruction_has_delayslot; |
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if (cpu_id == 0) |
if (cpu_id == 0) |
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debug("%s", cpu->cd.mips.cpu_type.name); |
debug("%s", cpu->cd.mips.cpu_type.name); |
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cpu->cd.mips.coproc[0] = mips_coproc_new(cpu, 0); |
cpu->cd.mips.coproc[0] = mips_coproc_new(cpu, 0); |
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cpu->cd.mips.coproc[1] = mips_coproc_new(cpu, 1); |
cpu->cd.mips.coproc[1] = mips_coproc_new(cpu, 1); |
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/* |
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* Initialize the cpu->cd.mips.pc_last_* cache (a 1-entry cache of the |
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* last program counter value). For pc_last_virtual_page, any |
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* "impossible" value will do. The pc should never ever get this |
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* value. (The other pc_last* variables do not need initialization, |
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* as they are not used before pc_last_virtual_page.) |
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*/ |
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cpu->cd.mips.pc_last_virtual_page = PC_LAST_PAGE_IMPOSSIBLE_VALUE; |
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switch (cpu->cd.mips.cpu_type.mmu_model) { |
switch (cpu->cd.mips.cpu_type.mmu_model) { |
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case MMU3K: |
case MMU3K: |
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cpu->translate_address = translate_address_mmu3k; |
cpu->translate_address = translate_address_mmu3k; |
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cpu->translate_address = translate_address_generic; |
cpu->translate_address = translate_address_generic; |
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} |
} |
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/* Testing: */ |
mips_init_64bit_dummy_tables(cpu); |
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cpu->cd.mips.host_load = zeroed_alloc(1048576 * |
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sizeof(unsigned char *)); |
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cpu->cd.mips.host_store = zeroed_alloc(1048576 * |
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sizeof(unsigned char *)); |
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cpu->cd.mips.host_load_orig = cpu->cd.mips.host_load; |
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cpu->cd.mips.host_store_orig = cpu->cd.mips.host_store; |
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return 1; |
return 1; |
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} |
} |
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/* |
/* |
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* mips_cpu_show_full_statistics(): |
* mips_cpu_dumpinfo(): |
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* |
* |
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* Show detailed statistics on opcode usage on each cpu. |
* Debug dump of MIPS-specific CPU data for specific CPU. |
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*/ |
*/ |
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void mips_cpu_show_full_statistics(struct machine *m) |
void mips_cpu_dumpinfo(struct cpu *cpu) |
339 |
{ |
{ |
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int i, s1, s2, iadd = 4; |
int iadd = DEBUG_INDENTATION; |
341 |
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struct mips_cpu_type_def *ct = &cpu->cd.mips.cpu_type; |
342 |
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343 |
if (m->bintrans_enable) |
debug_indentation(iadd); |
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fatal("NOTE: Dynamic binary translation is used; this list" |
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" of opcode usage\n only includes instructions that" |
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" were interpreted manually!\n"); |
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for (i=0; i<m->ncpus; i++) { |
debug("\n%i-bit %s-endian (MIPS", |
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fatal("cpu%i opcode statistics:\n", i); |
cpu->is_32bit? 32 : 64, |
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debug_indentation(iadd); |
cpu->byte_order == EMUL_BIG_ENDIAN? "Big" : "Little"); |
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for (s1=0; s1<N_HI6; s1++) { |
switch (ct->isa_level) { |
350 |
if (m->cpus[i]->cd.mips.stats_opcode[s1] > 0) |
case 1: debug(" ISA I"); break; |
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fatal("opcode %02x (%7s): %li\n", s1, |
case 2: debug(" ISA II"); break; |
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hi6_names[s1], |
case 3: debug(" ISA III"); break; |
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m->cpus[i]->cd.mips.stats_opcode[s1]); |
case 4: debug(" ISA IV"); break; |
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case 5: debug(" ISA V"); break; |
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debug_indentation(iadd); |
case 32: |
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if (s1 == HI6_SPECIAL) |
case 64:debug("%i, revision %i", ct->isa_level, ct->isa_revision); |
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for (s2=0; s2<N_SPECIAL; s2++) |
break; |
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if (m->cpus[i]->cd.mips.stats__special[ |
default:debug(" ISA level %i", ct->isa_level); |
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s2] > 0) |
} |
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fatal("special %02x (%7s): " |
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"%li\n", s2, special_names[ |
debug("), "); |
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s2], m->cpus[i]->cd.mips. |
if (ct->nr_of_tlb_entries) |
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stats__special[s2]); |
debug("%i TLB entries", ct->nr_of_tlb_entries); |
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if (s1 == HI6_REGIMM) |
else |
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for (s2=0; s2<N_REGIMM; s2++) |
debug("no TLB"); |
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if (m->cpus[i]->cd.mips.stats__regimm[ |
debug("\n"); |
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s2] > 0) |
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fatal("regimm %02x (%7s): " |
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"%li\n", s2, regimm_names[ |
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s2], m->cpus[i]->cd.mips. |
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stats__regimm[s2]); |
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if (s1 == HI6_SPECIAL2) |
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for (s2=0; s2<N_SPECIAL; s2++) |
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if (m->cpus[i]->cd.mips.stats__special2 |
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[s2] > 0) |
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fatal("special2 %02x (%7s): " |
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"%li\n", s2, |
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special2_names[s2], m-> |
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cpus[i]->cd.mips. |
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stats__special2[s2]); |
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debug_indentation(-iadd); |
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} |
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debug_indentation(-iadd); |
if (ct->picache) { |
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debug("L1 I-cache: %i KB", (1 << ct->picache) / 1024); |
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if (ct->pilinesize) |
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debug(", %i bytes per line", 1 << ct->pilinesize); |
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if (ct->piways > 1) |
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debug(", %i-way", ct->piways); |
374 |
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else |
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debug(", direct-mapped"); |
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debug("\n"); |
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} |
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379 |
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if (ct->pdcache) { |
380 |
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debug("L1 D-cache: %i KB", (1 << ct->pdcache) / 1024); |
381 |
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if (ct->pdlinesize) |
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debug(", %i bytes per line", 1 << ct->pdlinesize); |
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if (ct->pdways > 1) |
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debug(", %i-way", ct->pdways); |
385 |
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else |
386 |
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debug(", direct-mapped"); |
387 |
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debug("\n"); |
388 |
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} |
389 |
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390 |
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if (ct->scache) { |
391 |
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int kb = (1 << ct->scache) / 1024; |
392 |
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debug("L2 cache: %i %s", |
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kb >= 1024? kb / 1024 : kb, kb >= 1024? "MB":"KB"); |
394 |
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if (ct->slinesize) |
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debug(", %i bytes per line", 1 << ct->slinesize); |
396 |
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if (ct->sways > 1) |
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debug(", %i-way", ct->sways); |
398 |
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else |
399 |
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debug(", direct-mapped"); |
400 |
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debug("\n"); |
401 |
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} |
402 |
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403 |
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debug_indentation(-iadd); |
404 |
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} |
405 |
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406 |
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/* |
408 |
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* mips_cpu_list_available_types(): |
409 |
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* |
410 |
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* Print a list of available MIPS CPU types. |
411 |
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*/ |
412 |
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void mips_cpu_list_available_types(void) |
413 |
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{ |
414 |
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int i, j; |
415 |
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struct mips_cpu_type_def cpu_type_defs[] = MIPS_CPU_TYPE_DEFS; |
416 |
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417 |
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i = 0; |
418 |
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while (cpu_type_defs[i].name != NULL) { |
419 |
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debug("%s", cpu_type_defs[i].name); |
420 |
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for (j=10 - strlen(cpu_type_defs[i].name); j>0; j--) |
421 |
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debug(" "); |
422 |
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i++; |
423 |
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if ((i % 6) == 0 || cpu_type_defs[i].name == NULL) |
424 |
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debug("\n"); |
425 |
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} |
426 |
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} |
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428 |
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429 |
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/* |
430 |
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* mips_cpu_instruction_has_delayslot(): |
431 |
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* |
432 |
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* Return 1 if an opcode is a branch, 0 otherwise. |
433 |
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*/ |
434 |
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int mips_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib) |
435 |
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{ |
436 |
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uint32_t iword = *((uint32_t *)&ib[0]); |
437 |
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438 |
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if (cpu->byte_order == EMUL_LITTLE_ENDIAN) |
439 |
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iword = LE32_TO_HOST(iword); |
440 |
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else |
441 |
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iword = BE32_TO_HOST(iword); |
442 |
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443 |
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switch (iword >> 26) { |
444 |
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case HI6_SPECIAL: |
445 |
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switch (iword & 0x3f) { |
446 |
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case SPECIAL_JR: |
447 |
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case SPECIAL_JALR: |
448 |
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return 1; |
449 |
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} |
450 |
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break; |
451 |
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case HI6_REGIMM: |
452 |
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switch ((iword >> 16) & 0x1f) { |
453 |
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case REGIMM_BLTZ: |
454 |
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case REGIMM_BGEZ: |
455 |
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case REGIMM_BLTZL: |
456 |
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case REGIMM_BGEZL: |
457 |
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case REGIMM_BLTZAL: |
458 |
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case REGIMM_BLTZALL: |
459 |
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case REGIMM_BGEZAL: |
460 |
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case REGIMM_BGEZALL: |
461 |
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return 1; |
462 |
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} |
463 |
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break; |
464 |
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case HI6_BEQ: |
465 |
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case HI6_BEQL: |
466 |
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case HI6_BNE: |
467 |
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case HI6_BNEL: |
468 |
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case HI6_BGTZ: |
469 |
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case HI6_BGTZL: |
470 |
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case HI6_BLEZ: |
471 |
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case HI6_BLEZL: |
472 |
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case HI6_J: |
473 |
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case HI6_JAL: |
474 |
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return 1; |
475 |
} |
} |
476 |
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477 |
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return 0; |
478 |
} |
} |
479 |
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480 |
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{ |
{ |
492 |
int i, j; |
int i, j; |
493 |
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494 |
/* Nicely formatted output: */ |
/* Raw output: */ |
495 |
if (!rawflag) { |
if (rawflag) { |
496 |
for (i=0; i<m->ncpus; i++) { |
for (i=0; i<m->ncpus; i++) { |
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int pageshift = 12; |
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497 |
if (x >= 0 && i != x) |
if (x >= 0 && i != x) |
498 |
continue; |
continue; |
499 |
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if (m->cpus[i]->cd.mips.cpu_type.rev == MIPS_R4100) |
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pageshift = 10; |
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500 |
/* Print index, random, and wired: */ |
/* Print index, random, and wired: */ |
501 |
printf("cpu%i: (", i); |
printf("cpu%i: (", i); |
502 |
switch (m->cpus[i]->cd.mips.cpu_type.isa_level) { |
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503 |
case 1: |
if (m->cpus[i]->is_32bit) |
504 |
case 2: |
printf("index=0x%08x random=0x%08x", (int)m-> |
505 |
printf("index=0x%x random=0x%x", |
cpus[i]->cd.mips.coproc[0]->reg[COP0_INDEX], |
506 |
(int) ((m->cpus[i]->cd.mips.coproc[0]-> |
(int)m->cpus[i]->cd.mips.coproc[0]->reg |
507 |
reg[COP0_INDEX] & R2K3K_INDEX_MASK) |
[COP0_RANDOM]); |
508 |
>> R2K3K_INDEX_SHIFT), |
else |
509 |
(int) ((m->cpus[i]->cd.mips.coproc[0]-> |
printf("index=0x%016"PRIx64 |
510 |
reg[COP0_RANDOM] & R2K3K_RANDOM_MASK) |
" random=0x%016"PRIx64, |
511 |
>> R2K3K_RANDOM_SHIFT)); |
(uint64_t)m->cpus[i]->cd.mips.coproc[0]-> |
512 |
break; |
reg[COP0_INDEX], (uint64_t)m->cpus[i]-> |
513 |
default: |
cd.mips.coproc[0]->reg[COP0_RANDOM]); |
514 |
printf("index=0x%x random=0x%x", |
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515 |
(int) (m->cpus[i]->cd.mips.coproc[0]-> |
if (m->cpus[i]->cd.mips.cpu_type.isa_level >= 3) |
516 |
reg[COP0_INDEX] & INDEX_MASK), |
printf(" wired=0x%"PRIx64, (uint64_t) m->cpus |
517 |
(int) (m->cpus[i]->cd.mips.coproc[0]-> |
[i]->cd.mips.coproc[0]->reg[COP0_WIRED]); |
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reg[COP0_RANDOM] & RANDOM_MASK)); |
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printf(" wired=0x%llx", (long long) |
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m->cpus[i]->cd.mips.coproc[0]-> |
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reg[COP0_WIRED]); |
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} |
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518 |
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519 |
printf(")\n"); |
printf(")\n"); |
520 |
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521 |
for (j=0; j<m->cpus[i]->cd.mips.cpu_type. |
for (j=0; j<m->cpus[i]->cd.mips.cpu_type. |
522 |
nr_of_tlb_entries; j++) { |
nr_of_tlb_entries; j++) { |
523 |
uint64_t hi,lo0,lo1,mask; |
if (m->cpus[i]->cd.mips.cpu_type.mmu_model == |
524 |
hi = m->cpus[i]->cd.mips.coproc[0]->tlbs[j].hi; |
MMU3K) |
525 |
lo0 = m->cpus[i]->cd.mips.coproc[0]->tlbs[j].lo0; |
printf("%3i: hi=0x%08x lo=0x%08x\n", j, |
526 |
lo1 = m->cpus[i]->cd.mips.coproc[0]->tlbs[j].lo1; |
(int)m->cpus[i]->cd.mips.coproc[0]->tlbs[j].hi, |
527 |
mask = m->cpus[i]->cd.mips.coproc[0]->tlbs[j].mask; |
(int)m->cpus[i]->cd.mips.coproc[0]->tlbs[j].lo0); |
528 |
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else if (m->cpus[i]->is_32bit) |
529 |
printf("%3i: ", j); |
printf("%3i: hi=0x%08x mask=0x%08x " |
530 |
switch (m->cpus[i]->cd.mips.cpu_type.mmu_model) { |
"lo0=0x%08x lo1=0x%08x\n", j, |
531 |
case MMU3K: |
(int)m->cpus[i]->cd.mips.coproc[0]->tlbs[j].hi, |
532 |
if (!(lo0 & R2K3K_ENTRYLO_V)) { |
(int)m->cpus[i]->cd.mips.coproc[0]->tlbs[j].mask, |
533 |
printf("(invalid)\n"); |
(int)m->cpus[i]->cd.mips.coproc[0]->tlbs[j].lo0, |
534 |
continue; |
(int)m->cpus[i]->cd.mips.coproc[0]->tlbs[j].lo1); |
535 |
} |
else |
536 |
printf("vaddr=0x%08x ", |
printf("%3i: hi=0x%016"PRIx64" mask=0x%016"PRIx64" " |
537 |
(int) (hi&R2K3K_ENTRYHI_VPN_MASK)); |
"lo0=0x%016"PRIx64" lo1=0x%016"PRIx64"\n", j, |
538 |
if (lo0 & R2K3K_ENTRYLO_G) |
(uint64_t)m->cpus[i]->cd.mips.coproc[0]->tlbs[j].hi, |
539 |
printf("(global), "); |
(uint64_t)m->cpus[i]->cd.mips.coproc[0]->tlbs[j].mask, |
540 |
else |
(uint64_t)m->cpus[i]->cd.mips.coproc[0]->tlbs[j].lo0, |
541 |
printf("(asid %02x),", |
(uint64_t)m->cpus[i]->cd.mips.coproc[0]->tlbs[j].lo1); |
|
(int) ((hi & R2K3K_ENTRYHI_ASID_MASK) |
|
|
>> R2K3K_ENTRYHI_ASID_SHIFT)); |
|
|
printf(" paddr=0x%08x ", |
|
|
(int) (lo0&R2K3K_ENTRYLO_PFN_MASK)); |
|
|
if (lo0 & R2K3K_ENTRYLO_N) |
|
|
printf("N"); |
|
|
if (lo0 & R2K3K_ENTRYLO_D) |
|
|
printf("D"); |
|
|
printf("\n"); |
|
|
break; |
|
|
default: |
|
|
switch (m->cpus[i]->cd.mips.cpu_type.mmu_model) { |
|
|
case MMU10K: |
|
|
printf("vaddr=0x%1x..%011llx ", |
|
|
(int) (hi >> 60), |
|
|
(long long) (hi&ENTRYHI_VPN2_MASK_R10K)); |
|
|
break; |
|
|
case MMU32: |
|
|
printf("vaddr=0x%08x ", (int)(hi&ENTRYHI_VPN2_MASK)); |
|
|
break; |
|
|
default:/* R4000 etc. */ |
|
|
printf("vaddr=0x%1x..%010llx ", |
|
|
(int) (hi >> 60), |
|
|
(long long) (hi&ENTRYHI_VPN2_MASK)); |
|
|
} |
|
|
if (hi & TLB_G) |
|
|
printf("(global): "); |
|
|
else |
|
|
printf("(asid %02x):", |
|
|
(int) (hi & ENTRYHI_ASID)); |
|
|
|
|
|
/* TODO: Coherency bits */ |
|
|
|
|
|
if (!(lo0 & ENTRYLO_V)) |
|
|
printf(" p0=(invalid) "); |
|
|
else |
|
|
printf(" p0=0x%09llx ", (long long) |
|
|
(((lo0&ENTRYLO_PFN_MASK) >> ENTRYLO_PFN_SHIFT) << pageshift)); |
|
|
printf(lo0 & ENTRYLO_D? "D" : " "); |
|
|
|
|
|
if (!(lo1 & ENTRYLO_V)) |
|
|
printf(" p1=(invalid) "); |
|
|
else |
|
|
printf(" p1=0x%09llx ", (long long) |
|
|
(((lo1&ENTRYLO_PFN_MASK) >> ENTRYLO_PFN_SHIFT) << pageshift)); |
|
|
printf(lo1 & ENTRYLO_D? "D" : " "); |
|
|
mask |= (1 << (pageshift+1)) - 1; |
|
|
switch (mask) { |
|
|
case 0x7ff: printf(" (1KB)"); break; |
|
|
case 0x1fff: printf(" (4KB)"); break; |
|
|
case 0x7fff: printf(" (16KB)"); break; |
|
|
case 0x1ffff: printf(" (64KB)"); break; |
|
|
case 0x7ffff: printf(" (256KB)"); break; |
|
|
case 0x1fffff: printf(" (1MB)"); break; |
|
|
case 0x7fffff: printf(" (4MB)"); break; |
|
|
case 0x1ffffff: printf(" (16MB)"); break; |
|
|
case 0x7ffffff: printf(" (64MB)"); break; |
|
|
default: |
|
|
printf(" (mask=%08x?)", (int)mask); |
|
|
} |
|
|
printf("\n"); |
|
|
} |
|
542 |
} |
} |
543 |
} |
} |
|
|
|
544 |
return; |
return; |
545 |
} |
} |
546 |
|
|
547 |
/* Raw output: */ |
/* Nicely formatted output: */ |
548 |
for (i=0; i<m->ncpus; i++) { |
for (i=0; i<m->ncpus; i++) { |
549 |
|
int pageshift = 12; |
550 |
|
|
551 |
if (x >= 0 && i != x) |
if (x >= 0 && i != x) |
552 |
continue; |
continue; |
553 |
|
|
554 |
|
if (m->cpus[i]->cd.mips.cpu_type.rev == MIPS_R4100) |
555 |
|
pageshift = 10; |
556 |
|
|
557 |
/* Print index, random, and wired: */ |
/* Print index, random, and wired: */ |
558 |
printf("cpu%i: (", i); |
printf("cpu%i: (", i); |
559 |
|
switch (m->cpus[i]->cd.mips.cpu_type.isa_level) { |
560 |
if (m->cpus[i]->is_32bit) |
case 1: |
561 |
printf("index=0x%08x random=0x%08x", |
case 2: printf("index=0x%x random=0x%x", |
562 |
(int)m->cpus[i]->cd.mips.coproc[0]->reg[COP0_INDEX], |
(int) ((m->cpus[i]->cd.mips.coproc[0]-> |
563 |
(int)m->cpus[i]->cd.mips.coproc[0]->reg[COP0_RANDOM]); |
reg[COP0_INDEX] & R2K3K_INDEX_MASK) |
564 |
else |
>> R2K3K_INDEX_SHIFT), |
565 |
printf("index=0x%016llx random=0x%016llx", (long long) |
(int) ((m->cpus[i]->cd.mips.coproc[0]-> |
566 |
m->cpus[i]->cd.mips.coproc[0]->reg[COP0_INDEX], |
reg[COP0_RANDOM] & R2K3K_RANDOM_MASK) |
567 |
(long long)m->cpus[i]->cd.mips.coproc[0]->reg |
>> R2K3K_RANDOM_SHIFT)); |
568 |
[COP0_RANDOM]); |
break; |
569 |
|
default:printf("index=0x%x random=0x%x", |
570 |
if (m->cpus[i]->cd.mips.cpu_type.isa_level >= 3) |
(int) (m->cpus[i]->cd.mips.coproc[0]-> |
571 |
printf(" wired=0x%llx", (long long) |
reg[COP0_INDEX] & INDEX_MASK), |
572 |
|
(int) (m->cpus[i]->cd.mips.coproc[0]-> |
573 |
|
reg[COP0_RANDOM] & RANDOM_MASK)); |
574 |
|
printf(" wired=0x%"PRIx64, (uint64_t) |
575 |
m->cpus[i]->cd.mips.coproc[0]->reg[COP0_WIRED]); |
m->cpus[i]->cd.mips.coproc[0]->reg[COP0_WIRED]); |
576 |
|
} |
577 |
|
|
578 |
printf(")\n"); |
printf(")\n"); |
579 |
|
|
580 |
for (j=0; j<m->cpus[i]->cd.mips.cpu_type.nr_of_tlb_entries; j++) { |
for (j=0; j<m->cpus[i]->cd.mips.cpu_type. |
581 |
if (m->cpus[i]->cd.mips.cpu_type.mmu_model == MMU3K) |
nr_of_tlb_entries; j++) { |
582 |
printf("%3i: hi=0x%08x lo=0x%08x\n", |
uint64_t hi,lo0,lo1,mask; |
583 |
j, |
hi = m->cpus[i]->cd.mips.coproc[0]->tlbs[j].hi; |
584 |
(int)m->cpus[i]->cd.mips.coproc[0]->tlbs[j].hi, |
lo0 = m->cpus[i]->cd.mips.coproc[0]->tlbs[j].lo0; |
585 |
(int)m->cpus[i]->cd.mips.coproc[0]->tlbs[j].lo0); |
lo1 = m->cpus[i]->cd.mips.coproc[0]->tlbs[j].lo1; |
586 |
else if (m->cpus[i]->is_32bit) |
mask = m->cpus[i]->cd.mips.coproc[0]->tlbs[j].mask; |
587 |
printf("%3i: hi=0x%08x mask=0x%08x " |
|
588 |
"lo0=0x%08x lo1=0x%08x\n", j, |
printf("%3i: ", j); |
589 |
(int)m->cpus[i]->cd.mips.coproc[0]->tlbs[j].hi, |
switch (m->cpus[i]->cd.mips.cpu_type.mmu_model) { |
590 |
(int)m->cpus[i]->cd.mips.coproc[0]->tlbs[j].mask, |
case MMU3K: |
591 |
(int)m->cpus[i]->cd.mips.coproc[0]->tlbs[j].lo0, |
if (!(lo0 & R2K3K_ENTRYLO_V)) { |
592 |
(int)m->cpus[i]->cd.mips.coproc[0]->tlbs[j].lo1); |
printf("(invalid)\n"); |
593 |
else |
continue; |
594 |
printf("%3i: hi=0x%016llx mask=0x%016llx " |
} |
595 |
"lo0=0x%016llx lo1=0x%016llx\n", j, |
printf("vaddr=0x%08x ", |
596 |
(long long)m->cpus[i]->cd.mips.coproc[0]->tlbs[j].hi, |
(int) (hi&R2K3K_ENTRYHI_VPN_MASK)); |
597 |
(long long)m->cpus[i]->cd.mips.coproc[0]->tlbs[j].mask, |
if (lo0 & R2K3K_ENTRYLO_G) |
598 |
(long long)m->cpus[i]->cd.mips.coproc[0]->tlbs[j].lo0, |
printf("(global), "); |
599 |
(long long)m->cpus[i]->cd.mips.coproc[0]->tlbs[j].lo1); |
else |
600 |
|
printf("(asid %02x),", (int) ((hi & |
601 |
|
R2K3K_ENTRYHI_ASID_MASK) |
602 |
|
>> R2K3K_ENTRYHI_ASID_SHIFT)); |
603 |
|
printf(" paddr=0x%08x ", |
604 |
|
(int) (lo0&R2K3K_ENTRYLO_PFN_MASK)); |
605 |
|
if (lo0 & R2K3K_ENTRYLO_N) |
606 |
|
printf("N"); |
607 |
|
if (lo0 & R2K3K_ENTRYLO_D) |
608 |
|
printf("D"); |
609 |
|
printf("\n"); |
610 |
|
break; |
611 |
|
default:switch (m->cpus[i]->cd.mips.cpu_type.mmu_model){ |
612 |
|
case MMU10K: |
613 |
|
printf("vaddr=0x%1x..%011"PRIx64" ", |
614 |
|
(int) (hi >> 60), (uint64_t) |
615 |
|
(hi&ENTRYHI_VPN2_MASK_R10K)); |
616 |
|
break; |
617 |
|
case MMU32: |
618 |
|
printf("vaddr=0x%08"PRIx32" ", |
619 |
|
(uint32_t)(hi&ENTRYHI_VPN2_MASK)); |
620 |
|
break; |
621 |
|
default:/* R4000 etc. */ |
622 |
|
printf("vaddr=0x%1x..%010"PRIx64" ", |
623 |
|
(int) (hi >> 60), |
624 |
|
(uint64_t) (hi&ENTRYHI_VPN2_MASK)); |
625 |
|
} |
626 |
|
if (hi & TLB_G) |
627 |
|
printf("(global): "); |
628 |
|
else |
629 |
|
printf("(asid %02x):", |
630 |
|
(int) (hi & ENTRYHI_ASID)); |
631 |
|
|
632 |
|
/* TODO: Coherency bits */ |
633 |
|
|
634 |
|
if (!(lo0 & ENTRYLO_V)) |
635 |
|
printf(" p0=(invalid) "); |
636 |
|
else |
637 |
|
printf(" p0=0x%09"PRIx64" ", (uint64_t) |
638 |
|
(((lo0&ENTRYLO_PFN_MASK) >> |
639 |
|
ENTRYLO_PFN_SHIFT) << pageshift)); |
640 |
|
printf(lo0 & ENTRYLO_D? "D" : " "); |
641 |
|
|
642 |
|
if (!(lo1 & ENTRYLO_V)) |
643 |
|
printf(" p1=(invalid) "); |
644 |
|
else |
645 |
|
printf(" p1=0x%09"PRIx64" ", (uint64_t) |
646 |
|
(((lo1&ENTRYLO_PFN_MASK) >> |
647 |
|
ENTRYLO_PFN_SHIFT) << pageshift)); |
648 |
|
printf(lo1 & ENTRYLO_D? "D" : " "); |
649 |
|
mask |= (1 << (pageshift+1)) - 1; |
650 |
|
switch (mask) { |
651 |
|
case 0x7ff: printf(" (1KB)"); break; |
652 |
|
case 0x1fff: printf(" (4KB)"); break; |
653 |
|
case 0x7fff: printf(" (16KB)"); break; |
654 |
|
case 0x1ffff: printf(" (64KB)"); break; |
655 |
|
case 0x7ffff: printf(" (256KB)"); break; |
656 |
|
case 0x1fffff: printf(" (1MB)"); break; |
657 |
|
case 0x7fffff: printf(" (4MB)"); break; |
658 |
|
case 0x1ffffff: printf(" (16MB)"); break; |
659 |
|
case 0x7ffffff: printf(" (64MB)"); break; |
660 |
|
default:printf(" (mask=%08x?)", (int)mask); |
661 |
|
} |
662 |
|
printf("\n"); |
663 |
|
} |
664 |
} |
} |
665 |
} |
} |
666 |
} |
} |
682 |
if (strcasecmp(name, "pc") == 0) { |
if (strcasecmp(name, "pc") == 0) { |
683 |
if (writeflag) { |
if (writeflag) { |
684 |
m->cpus[cpunr]->pc = *valuep; |
m->cpus[cpunr]->pc = *valuep; |
685 |
if (m->cpus[cpunr]->cd.mips.delay_slot) { |
if (m->cpus[cpunr]->delay_slot) { |
686 |
printf("NOTE: Clearing the delay slot" |
printf("NOTE: Clearing the delay slot" |
687 |
" flag! (It was set before.)\n"); |
" flag! (It was set before.)\n"); |
688 |
m->cpus[cpunr]->cd.mips.delay_slot = 0; |
m->cpus[cpunr]->delay_slot = 0; |
689 |
} |
} |
690 |
if (m->cpus[cpunr]->cd.mips.nullify_next) { |
if (m->cpus[cpunr]->cd.mips.nullify_next) { |
691 |
printf("NOTE: Clearing the nullify-ne" |
printf("NOTE: Clearing the nullify-ne" |
765 |
*/ |
*/ |
766 |
static const char *cpu_flags(struct cpu *cpu) |
static const char *cpu_flags(struct cpu *cpu) |
767 |
{ |
{ |
768 |
if (cpu->cd.mips.delay_slot) { |
if (cpu->delay_slot) { |
769 |
if (cpu->cd.mips.last_was_jumptoself) |
if (cpu->cd.mips.last_was_jumptoself) |
770 |
return " (dj)"; |
return " (dj)"; |
771 |
else |
else |
794 |
* NOTE 2: coprocessor instructions are not decoded nicely yet (TODO) |
* NOTE 2: coprocessor instructions are not decoded nicely yet (TODO) |
795 |
*/ |
*/ |
796 |
int mips_cpu_disassemble_instr(struct cpu *cpu, unsigned char *originstr, |
int mips_cpu_disassemble_instr(struct cpu *cpu, unsigned char *originstr, |
797 |
int running, uint64_t dumpaddr, int bintrans) |
int running, uint64_t dumpaddr) |
798 |
{ |
{ |
799 |
int hi6, special6, regimm5; |
int hi6, special6, regimm5; |
800 |
int rt, rd, rs, sa, imm, copz, cache_op, which_cache, showtag; |
int rt, rd, rs, sa, imm, copz, cache_op, which_cache, showtag; |
818 |
debug("cpu%i: ", cpu->cpu_id); |
debug("cpu%i: ", cpu->cpu_id); |
819 |
|
|
820 |
if (cpu->is_32bit) |
if (cpu->is_32bit) |
821 |
debug("%08x", (int)dumpaddr); |
debug("%08"PRIx32, (uint32_t)dumpaddr); |
822 |
else |
else |
823 |
debug("%016llx", (long long)dumpaddr); |
debug("%016"PRIx64, (uint64_t)dumpaddr); |
824 |
|
|
825 |
*((uint32_t *)&instr[0]) = *((uint32_t *)&originstr[0]); |
*((uint32_t *)&instr[0]) = *((uint32_t *)&originstr[0]); |
826 |
|
|
843 |
|
|
844 |
debug("\t"); |
debug("\t"); |
845 |
|
|
|
if (bintrans && running) { |
|
|
debug("(bintrans)"); |
|
|
goto disasm_ret; |
|
|
} |
|
|
|
|
846 |
/* |
/* |
847 |
* Decode the instruction: |
* Decode the instruction: |
848 |
*/ |
*/ |
876 |
debug("nop"); |
debug("nop"); |
877 |
else if (sa == 1) |
else if (sa == 1) |
878 |
debug("ssnop"); |
debug("ssnop"); |
879 |
|
else if (sa == 3) |
880 |
|
debug("ehb"); |
881 |
else |
else |
882 |
debug("nop (weird, sa=%i)", sa); |
debug("nop (weird, sa=%i)", sa); |
883 |
goto disasm_ret; |
goto disasm_ret; |
950 |
rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7); |
rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7); |
951 |
rt = instr[2] & 31; |
rt = instr[2] & 31; |
952 |
rd = (instr[1] >> 3) & 31; |
rd = (instr[1] >> 3) & 31; |
953 |
if ((special6 == SPECIAL_ADDU || |
if (cpu->is_32bit && (special6 == SPECIAL_ADDU || |
954 |
special6 == SPECIAL_DADDU || |
special6 == SPECIAL_SUBU) && rt == 0) { |
955 |
special6 == SPECIAL_SUBU || |
/* Special case 1: addu/subu with |
|
special6 == SPECIAL_DSUBU) && rt == 0) { |
|
|
/* Special case 1: addu/daddu/subu/dsubu with |
|
956 |
rt = the zero register ==> move */ |
rt = the zero register ==> move */ |
957 |
debug("move\t%s", regname(cpu->machine, rd)); |
debug("move\t%s", regname(cpu->machine, rd)); |
958 |
debug(",%s", regname(cpu->machine, rs)); |
debug(",%s", regname(cpu->machine, rs)); |
959 |
} else if ((special6 == SPECIAL_ADDU || |
} else if (special6 == SPECIAL_ADDU && cpu->is_32bit |
960 |
special6 == SPECIAL_DADDU) && rs == 0) { |
&& rs == 0) { |
961 |
/* Special case 2: addu/daddu with |
/* Special case 2: addu with |
962 |
rs = the zero register ==> move */ |
rs = the zero register ==> move */ |
963 |
debug("move\t%s", regname(cpu->machine, rd)); |
debug("move\t%s", regname(cpu->machine, rd)); |
964 |
debug(",%s", regname(cpu->machine, rt)); |
debug(",%s", regname(cpu->machine, rt)); |
986 |
rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7); |
rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7); |
987 |
rt = instr[2] & 31; |
rt = instr[2] & 31; |
988 |
rd = (instr[1] >> 3) & 31; |
rd = (instr[1] >> 3) & 31; |
989 |
if (special6 == SPECIAL_MULT) { |
debug("%s\t", special_names[special6]); |
990 |
if (rd != 0) { |
if (rd != 0) { |
991 |
debug("mult_xx\t%s", |
if (cpu->cd.mips.cpu_type.rev == MIPS_R5900) { |
992 |
regname(cpu->machine, rd)); |
if (special6 == SPECIAL_MULT || |
993 |
debug(",%s", regname(cpu->machine, rs)); |
special6 == SPECIAL_MULTU) |
994 |
debug(",%s", regname(cpu->machine, rt)); |
debug("%s,", |
995 |
goto disasm_ret; |
regname(cpu->machine, rd)); |
996 |
|
else |
997 |
|
debug("WEIRD_R5900_RD,"); |
998 |
|
} else { |
999 |
|
debug("WEIRD_RD_NONZERO,"); |
1000 |
} |
} |
1001 |
} |
} |
1002 |
debug("%s\t%s", special_names[special6], |
debug("%s", regname(cpu->machine, rs)); |
|
regname(cpu->machine, rs)); |
|
1003 |
debug(",%s", regname(cpu->machine, rt)); |
debug(",%s", regname(cpu->machine, rt)); |
1004 |
break; |
break; |
1005 |
case SPECIAL_SYNC: |
case SPECIAL_SYNC: |
1023 |
debug("break"); |
debug("break"); |
1024 |
break; |
break; |
1025 |
case SPECIAL_MFSA: |
case SPECIAL_MFSA: |
1026 |
rd = (instr[1] >> 3) & 31; |
if (cpu->cd.mips.cpu_type.rev == MIPS_R5900) { |
1027 |
debug("mfsa\t%s", regname(cpu->machine, rd)); |
rd = (instr[1] >> 3) & 31; |
1028 |
|
debug("mfsa\t%s", regname(cpu->machine, rd)); |
1029 |
|
} else { |
1030 |
|
debug("unimplemented special 0x28"); |
1031 |
|
} |
1032 |
break; |
break; |
1033 |
case SPECIAL_MTSA: |
case SPECIAL_MTSA: |
1034 |
rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7); |
if (cpu->cd.mips.cpu_type.rev == MIPS_R5900) { |
1035 |
debug("mtsa\t%s", regname(cpu->machine, rs)); |
rs = ((instr[3] & 3) << 3) + |
1036 |
|
((instr[2] >> 5) & 7); |
1037 |
|
debug("mtsa\t%s", regname(cpu->machine, rs)); |
1038 |
|
} else { |
1039 |
|
debug("unimplemented special 0x29"); |
1040 |
|
} |
1041 |
break; |
break; |
1042 |
default: |
default: |
1043 |
debug("unimplemented special6 = 0x%02x", special6); |
debug("%s\t= UNIMPLEMENTED", special_names[special6]); |
1044 |
} |
} |
1045 |
break; |
break; |
1046 |
case HI6_BEQ: |
case HI6_BEQ: |
1057 |
if (imm >= 32768) |
if (imm >= 32768) |
1058 |
imm -= 65536; |
imm -= 65536; |
1059 |
addr = (dumpaddr + 4) + (imm << 2); |
addr = (dumpaddr + 4) + (imm << 2); |
|
debug("%s\t", hi6_names[hi6]); |
|
1060 |
|
|
1061 |
switch (hi6) { |
if (hi6 == HI6_BEQ && rt == MIPS_GPR_ZERO && |
1062 |
case HI6_BEQ: |
rs == MIPS_GPR_ZERO) |
1063 |
case HI6_BEQL: |
debug("b\t"); |
1064 |
case HI6_BNE: |
else { |
1065 |
case HI6_BNEL: |
debug("%s\t", hi6_names[hi6]); |
1066 |
debug("%s,", regname(cpu->machine, rt)); |
switch (hi6) { |
1067 |
|
case HI6_BEQ: |
1068 |
|
case HI6_BEQL: |
1069 |
|
case HI6_BNE: |
1070 |
|
case HI6_BNEL: |
1071 |
|
debug("%s,", regname(cpu->machine, rt)); |
1072 |
|
} |
1073 |
|
debug("%s,", regname(cpu->machine, rs)); |
1074 |
} |
} |
1075 |
|
|
|
debug("%s,", regname(cpu->machine, rs)); |
|
|
|
|
1076 |
if (cpu->is_32bit) |
if (cpu->is_32bit) |
1077 |
debug("0x%08x", (int)addr); |
debug("0x%08"PRIx32, (uint32_t)addr); |
1078 |
else |
else |
1079 |
debug("0x%016llx", (long long)addr); |
debug("0x%016"PRIx64, (uint64_t)addr); |
1080 |
|
|
1081 |
symbol = get_symbol_name(&cpu->machine->symbol_context, |
symbol = get_symbol_name(&cpu->machine->symbol_context, |
1082 |
addr, &offset); |
addr, &offset); |
1128 |
case HI6_SH: |
case HI6_SH: |
1129 |
case HI6_SW: |
case HI6_SW: |
1130 |
case HI6_SD: |
case HI6_SD: |
1131 |
case HI6_SQ: |
case HI6_SQ_SPECIAL3: |
1132 |
case HI6_SC: |
case HI6_SC: |
1133 |
case HI6_SCD: |
case HI6_SCD: |
1134 |
case HI6_SWC1: |
case HI6_SWC1: |
1144 |
case HI6_SWR: |
case HI6_SWR: |
1145 |
case HI6_SDL: |
case HI6_SDL: |
1146 |
case HI6_SDR: |
case HI6_SDR: |
1147 |
|
if (hi6 == HI6_LQ_MDMX && |
1148 |
|
cpu->cd.mips.cpu_type.rev != MIPS_R5900) { |
1149 |
|
debug("mdmx\t(UNIMPLEMENTED)"); |
1150 |
|
break; |
1151 |
|
} |
1152 |
|
if (hi6 == HI6_SQ_SPECIAL3 && |
1153 |
|
cpu->cd.mips.cpu_type.rev != MIPS_R5900) { |
1154 |
|
special6 = instr[0] & 0x3f; |
1155 |
|
debug("%s", special3_names[special6]); |
1156 |
|
rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7); |
1157 |
|
rt = instr[2] & 31; |
1158 |
|
rd = (instr[1] >> 3) & 31; |
1159 |
|
|
1160 |
|
switch (special6) { |
1161 |
|
|
1162 |
|
case SPECIAL3_RDHWR: |
1163 |
|
debug("\t%s", regname(cpu->machine, rt)); |
1164 |
|
debug(",hwr%i", rd); |
1165 |
|
break; |
1166 |
|
|
1167 |
|
default: |
1168 |
|
debug("\t(UNIMPLEMENTED)"); |
1169 |
|
} |
1170 |
|
break; |
1171 |
|
} |
1172 |
|
|
1173 |
rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7); |
rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7); |
1174 |
rt = instr[2] & 31; |
rt = instr[2] & 31; |
1175 |
imm = (instr[1] << 8) + instr[0]; |
imm = (instr[1] << 8) + instr[0]; |
1185 |
rt, imm, regname(cpu->machine, rs)); |
rt, imm, regname(cpu->machine, rs)); |
1186 |
|
|
1187 |
if (running) { |
if (running) { |
1188 |
debug("\t[0x%016llx = %s]", |
debug("\t[0x%016"PRIx64" = %s]", |
1189 |
(long long)(cpu->cd.mips.gpr[rs] + imm)); |
(uint64_t)(cpu->cd.mips.gpr[rs] + imm)); |
1190 |
if (symbol != NULL) |
if (symbol != NULL) |
1191 |
debug(" = %s", symbol); |
debug(" = %s", symbol); |
1192 |
debug("]"); |
debug("]"); |
1210 |
debug("\t["); |
debug("\t["); |
1211 |
|
|
1212 |
if (cpu->is_32bit) |
if (cpu->is_32bit) |
1213 |
debug("0x%08x", (int)(cpu->cd.mips.gpr[rs] + imm)); |
debug("0x%08"PRIx32, |
1214 |
|
(uint32_t) (cpu->cd.mips.gpr[rs] + imm)); |
1215 |
else |
else |
1216 |
debug("0x%016llx", |
debug("0x%016"PRIx64, |
1217 |
(long long)(cpu->cd.mips.gpr[rs] + imm)); |
(uint64_t) (cpu->cd.mips.gpr[rs] + imm)); |
1218 |
|
|
1219 |
if (symbol != NULL) |
if (symbol != NULL) |
1220 |
debug(" = %s", symbol); |
debug(" = %s", symbol); |
1221 |
|
|
1222 |
debug(", data="); |
/* TODO: In some cases, it is possible to peek into |
1223 |
} else |
memory, and display that data here, like for the |
1224 |
break; |
other emulation modes. */ |
1225 |
/* NOTE: No break here (if we are running) as it is up |
|
1226 |
to the caller to print 'data'. */ |
debug("]"); |
1227 |
return sizeof(instrword); |
} |
1228 |
|
break; |
1229 |
|
|
1230 |
case HI6_J: |
case HI6_J: |
1231 |
case HI6_JAL: |
case HI6_JAL: |
1232 |
imm = (((instr[3] & 3) << 24) + (instr[2] << 16) + |
imm = (((instr[3] & 3) << 24) + (instr[2] << 16) + |
1237 |
addr, &offset); |
addr, &offset); |
1238 |
debug("%s\t0x", hi6_names[hi6]); |
debug("%s\t0x", hi6_names[hi6]); |
1239 |
if (cpu->is_32bit) |
if (cpu->is_32bit) |
1240 |
debug("%08x", (int)addr); |
debug("%08"PRIx32, (uint32_t) addr); |
1241 |
else |
else |
1242 |
debug("%016llx", (long long)addr); |
debug("%016"PRIx64, (uint64_t) addr); |
1243 |
if (symbol != NULL) |
if (symbol != NULL) |
1244 |
debug("\t<%s>", symbol); |
debug("\t<%s>", symbol); |
1245 |
break; |
break; |
1246 |
|
|
1247 |
case HI6_COP0: |
case HI6_COP0: |
1248 |
case HI6_COP1: |
case HI6_COP1: |
1249 |
case HI6_COP2: |
case HI6_COP2: |
1256 |
coproc_function(cpu, cpu->cd.mips.coproc[hi6 - HI6_COP0], |
coproc_function(cpu, cpu->cd.mips.coproc[hi6 - HI6_COP0], |
1257 |
hi6 - HI6_COP0, imm, 1, running); |
hi6 - HI6_COP0, imm, 1, running); |
1258 |
return sizeof(instrword); |
return sizeof(instrword); |
1259 |
|
|
1260 |
case HI6_CACHE: |
case HI6_CACHE: |
1261 |
rt = ((instr[3] & 3) << 3) + (instr[2] >> 5); /* base */ |
rt = ((instr[3] & 3) << 3) + (instr[2] >> 5); /* base */ |
1262 |
copz = instr[2] & 31; |
copz = instr[2] & 31; |
1280 |
if (cache_op==6) debug("hit writeback"); |
if (cache_op==6) debug("hit writeback"); |
1281 |
if (cache_op==7) debug("hit set virtual"); |
if (cache_op==7) debug("hit set virtual"); |
1282 |
if (running) |
if (running) |
1283 |
debug(", addr 0x%016llx", |
debug(", addr 0x%016"PRIx64, |
1284 |
(long long)(cpu->cd.mips.gpr[rt] + imm)); |
(uint64_t)(cpu->cd.mips.gpr[rt] + imm)); |
1285 |
if (showtag) |
if (showtag) |
1286 |
debug(", taghi=%08lx lo=%08lx", |
debug(", taghi=%08lx lo=%08lx", |
1287 |
(long)cpu->cd.mips.coproc[0]->reg[COP0_TAGDATA_HI], |
(long)cpu->cd.mips.coproc[0]->reg[COP0_TAGDATA_HI], |
1288 |
(long)cpu->cd.mips.coproc[0]->reg[COP0_TAGDATA_LO]); |
(long)cpu->cd.mips.coproc[0]->reg[COP0_TAGDATA_LO]); |
1289 |
debug(" ]"); |
debug(" ]"); |
1290 |
break; |
break; |
1291 |
|
|
1292 |
case HI6_SPECIAL2: |
case HI6_SPECIAL2: |
1293 |
special6 = instr[0] & 0x3f; |
special6 = instr[0] & 0x3f; |
1294 |
instrword = (instr[3] << 24) + (instr[2] << 16) + |
instrword = (instr[3] << 24) + (instr[2] << 16) + |
1296 |
rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7); |
rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7); |
1297 |
rt = instr[2] & 31; |
rt = instr[2] & 31; |
1298 |
rd = (instr[1] >> 3) & 31; |
rd = (instr[1] >> 3) & 31; |
1299 |
if ((instrword & 0xfc0007ffULL) == 0x70000000) { |
|
1300 |
debug("madd\t%s", regname(cpu->machine, rd)); |
if (cpu->cd.mips.cpu_type.rev == MIPS_R5900) { |
1301 |
debug(",%s", regname(cpu->machine, rs)); |
int c790mmifunc = (instrword >> 6) & 0x1f; |
1302 |
debug(",%s", regname(cpu->machine, rt)); |
if (special6 != MMI_MMI0 && special6 != MMI_MMI1 && |
1303 |
} else if (special6 == SPECIAL2_MUL) { |
special6 != MMI_MMI2 && special6 != MMI_MMI3) |
1304 |
/* TODO: this is just a guess, I don't have the |
debug("%s\t", mmi_names[special6]); |
1305 |
docs in front of me */ |
|
1306 |
debug("mul\t%s", regname(cpu->machine, rd)); |
switch (special6) { |
1307 |
debug(",%s", regname(cpu->machine, rs)); |
|
1308 |
debug(",%s", regname(cpu->machine, rt)); |
case MMI_MADD: |
1309 |
} else if (special6 == SPECIAL2_CLZ) { |
case MMI_MADDU: |
1310 |
debug("clz\t%s", regname(cpu->machine, rd)); |
if (rd != MIPS_GPR_ZERO) { |
1311 |
debug(",%s", regname(cpu->machine, rs)); |
debug("%s,", regname(cpu->machine, rd)); |
1312 |
} else if (special6 == SPECIAL2_CLO) { |
} |
1313 |
debug("clo\t%s", regname(cpu->machine, rd)); |
debug("%s", regname(cpu->machine, rs)); |
1314 |
debug(",%s", regname(cpu->machine, rs)); |
debug(",%s", regname(cpu->machine, rt)); |
1315 |
} else if (special6 == SPECIAL2_DCLZ) { |
break; |
1316 |
debug("dclz\t%s", regname(cpu->machine, rd)); |
|
1317 |
debug(",%s", regname(cpu->machine, rs)); |
case MMI_MMI0: |
1318 |
} else if (special6 == SPECIAL2_DCLO) { |
debug("%s\t", mmi0_names[c790mmifunc]); |
1319 |
debug("dclo\t%s", regname(cpu->machine, rd)); |
switch (c790mmifunc) { |
1320 |
debug(",%s", regname(cpu->machine, rs)); |
|
1321 |
} else if ((instrword & 0xffff07ffULL) == 0x70000209 |
case MMI0_PEXTLB: |
1322 |
|| (instrword & 0xffff07ffULL) == 0x70000249) { |
case MMI0_PEXTLH: |
1323 |
if (instr[0] == 0x49) { |
case MMI0_PEXTLW: |
1324 |
debug("pmflo\t%s", regname(cpu->machine, rd)); |
case MMI0_PMAXH: |
1325 |
debug(" (rs=%s)", regname(cpu->machine, rs)); |
case MMI0_PMAXW: |
1326 |
} else { |
case MMI0_PPACB: |
1327 |
debug("pmfhi\t%s", regname(cpu->machine, rd)); |
case MMI0_PPACH: |
1328 |
debug(" (rs=%s)", regname(cpu->machine, rs)); |
case MMI0_PPACW: |
1329 |
|
debug("%s", regname(cpu->machine, rd)); |
1330 |
|
debug(",%s", regname(cpu->machine, rs)); |
1331 |
|
debug(",%s", regname(cpu->machine, rt)); |
1332 |
|
break; |
1333 |
|
|
1334 |
|
default:debug("(UNIMPLEMENTED)"); |
1335 |
|
} |
1336 |
|
break; |
1337 |
|
|
1338 |
|
case MMI_MMI1: |
1339 |
|
debug("%s\t", mmi1_names[c790mmifunc]); |
1340 |
|
switch (c790mmifunc) { |
1341 |
|
|
1342 |
|
case MMI1_PEXTUB: |
1343 |
|
case MMI1_PEXTUH: |
1344 |
|
case MMI1_PEXTUW: |
1345 |
|
case MMI1_PMINH: |
1346 |
|
case MMI1_PMINW: |
1347 |
|
debug("%s", regname(cpu->machine, rd)); |
1348 |
|
debug(",%s", regname(cpu->machine, rs)); |
1349 |
|
debug(",%s", regname(cpu->machine, rt)); |
1350 |
|
break; |
1351 |
|
|
1352 |
|
default:debug("(UNIMPLEMENTED)"); |
1353 |
|
} |
1354 |
|
break; |
1355 |
|
|
1356 |
|
case MMI_MMI2: |
1357 |
|
debug("%s\t", mmi2_names[c790mmifunc]); |
1358 |
|
switch (c790mmifunc) { |
1359 |
|
|
1360 |
|
case MMI2_PMFHI: |
1361 |
|
case MMI2_PMFLO: |
1362 |
|
debug("%s", regname(cpu->machine, rd)); |
1363 |
|
break; |
1364 |
|
|
1365 |
|
case MMI2_PHMADH: |
1366 |
|
case MMI2_PHMSBH: |
1367 |
|
case MMI2_PINTH: |
1368 |
|
case MMI2_PMADDH: |
1369 |
|
case MMI2_PMADDW: |
1370 |
|
case MMI2_PMSUBH: |
1371 |
|
case MMI2_PMSUBW: |
1372 |
|
case MMI2_PMULTH: |
1373 |
|
case MMI2_PMULTW: |
1374 |
|
case MMI2_PSLLVW: |
1375 |
|
debug("%s", regname(cpu->machine, rd)); |
1376 |
|
debug(",%s", regname(cpu->machine, rs)); |
1377 |
|
debug(",%s", regname(cpu->machine, rt)); |
1378 |
|
break; |
1379 |
|
|
1380 |
|
default:debug("(UNIMPLEMENTED)"); |
1381 |
|
} |
1382 |
|
break; |
1383 |
|
|
1384 |
|
case MMI_MMI3: |
1385 |
|
debug("%s\t", mmi3_names[c790mmifunc]); |
1386 |
|
switch (c790mmifunc) { |
1387 |
|
|
1388 |
|
case MMI3_PMTHI: |
1389 |
|
case MMI3_PMTLO: |
1390 |
|
debug("%s", regname(cpu->machine, rs)); |
1391 |
|
break; |
1392 |
|
|
1393 |
|
case MMI3_PINTEH: |
1394 |
|
case MMI3_PMADDUW: |
1395 |
|
case MMI3_PMULTUW: |
1396 |
|
case MMI3_PNOR: |
1397 |
|
case MMI3_POR: |
1398 |
|
case MMI3_PSRAVW: |
1399 |
|
debug("%s", regname(cpu->machine, rd)); |
1400 |
|
debug(",%s", regname(cpu->machine, rs)); |
1401 |
|
debug(",%s", regname(cpu->machine, rt)); |
1402 |
|
break; |
1403 |
|
|
1404 |
|
default:debug("(UNIMPLEMENTED)"); |
1405 |
|
} |
1406 |
|
break; |
1407 |
|
|
1408 |
|
default:debug("(UNIMPLEMENTED)"); |
1409 |
} |
} |
1410 |
} else if ((instrword & 0xfc1fffff) == 0x70000269 |
break; |
1411 |
|| (instrword & 0xfc1fffff) == 0x70000229) { |
} |
1412 |
if (instr[0] == 0x69) { |
|
1413 |
debug("pmtlo\t%s", regname(cpu->machine, rs)); |
/* SPECIAL2: */ |
1414 |
} else { |
debug("%s\t", special2_names[special6]); |
1415 |
debug("pmthi\t%s", regname(cpu->machine, rs)); |
|
1416 |
} |
switch (special6) { |
1417 |
} else if ((instrword & 0xfc0007ff) == 0x700004a9) { |
|
1418 |
debug("por\t%s", regname(cpu->machine, rd)); |
case SPECIAL2_MADD: |
1419 |
debug(",%s", regname(cpu->machine, rs)); |
case SPECIAL2_MADDU: |
1420 |
|
case SPECIAL2_MSUB: |
1421 |
|
case SPECIAL2_MSUBU: |
1422 |
|
if (rd != MIPS_GPR_ZERO) { |
1423 |
|
debug("WEIRD_NONZERO_RD(%s),", |
1424 |
|
regname(cpu->machine, rd)); |
1425 |
|
} |
1426 |
|
debug("%s", regname(cpu->machine, rs)); |
1427 |
debug(",%s", regname(cpu->machine, rt)); |
debug(",%s", regname(cpu->machine, rt)); |
1428 |
} else if ((instrword & 0xfc0007ff) == 0x70000488) { |
break; |
1429 |
debug("pextlw\t%s", regname(cpu->machine, rd)); |
|
1430 |
|
case SPECIAL2_MUL: |
1431 |
|
/* Apparently used both on R5900 and MIPS32: */ |
1432 |
|
debug("%s", regname(cpu->machine, rd)); |
1433 |
debug(",%s", regname(cpu->machine, rs)); |
debug(",%s", regname(cpu->machine, rs)); |
1434 |
debug(",%s", regname(cpu->machine, rt)); |
debug(",%s", regname(cpu->machine, rt)); |
1435 |
} else { |
break; |
1436 |
debug("unimplemented special2 = 0x%02x", special6); |
|
1437 |
|
case SPECIAL2_CLZ: |
1438 |
|
case SPECIAL2_CLO: |
1439 |
|
case SPECIAL2_DCLZ: |
1440 |
|
case SPECIAL2_DCLO: |
1441 |
|
debug("%s", regname(cpu->machine, rd)); |
1442 |
|
debug(",%s", regname(cpu->machine, rs)); |
1443 |
|
break; |
1444 |
|
|
1445 |
|
default: |
1446 |
|
debug("(UNIMPLEMENTED)"); |
1447 |
} |
} |
1448 |
break; |
break; |
1449 |
|
|
1450 |
case HI6_REGIMM: |
case HI6_REGIMM: |
1451 |
regimm5 = instr[2] & 0x1f; |
regimm5 = instr[2] & 0x1f; |
1452 |
switch (regimm5) { |
switch (regimm5) { |
1469 |
addr = (dumpaddr + 4) + (imm << 2); |
addr = (dumpaddr + 4) + (imm << 2); |
1470 |
|
|
1471 |
if (cpu->is_32bit) |
if (cpu->is_32bit) |
1472 |
debug("0x%08x", (int)addr); |
debug("0x%08"PRIx32, (uint32_t) addr); |
1473 |
else |
else |
1474 |
debug("0x%016llx", (long long)addr); |
debug("0x%016"PRIx64, (uint64_t) addr); |
1475 |
break; |
break; |
1476 |
default: |
default: |
1477 |
debug("unimplemented regimm5 = 0x%02x", regimm5); |
debug("unimplemented regimm5 = 0x%02x", regimm5); |
1500 |
int coprocnr, i, bits32; |
int coprocnr, i, bits32; |
1501 |
uint64_t offset; |
uint64_t offset; |
1502 |
char *symbol; |
char *symbol; |
1503 |
|
int bits128 = cpu->cd.mips.cpu_type.rev == MIPS_R5900; |
1504 |
|
|
1505 |
bits32 = cpu->is_32bit; |
bits32 = cpu->is_32bit; |
1506 |
|
|
1510 |
cpu->pc, &offset); |
cpu->pc, &offset); |
1511 |
|
|
1512 |
if (bits32) |
if (bits32) |
1513 |
debug("cpu%i: pc = %08x", cpu->cpu_id, (int)cpu->pc); |
debug("cpu%i: pc = %08"PRIx32, |
1514 |
|
cpu->cpu_id, (uint32_t) cpu->pc); |
1515 |
|
else if (bits128) |
1516 |
|
debug("cpu%i: pc=%016"PRIx64, |
1517 |
|
cpu->cpu_id, (uint64_t) cpu->pc); |
1518 |
else |
else |
1519 |
debug("cpu%i: pc = 0x%016llx", |
debug("cpu%i: pc = 0x%016"PRIx64, |
1520 |
cpu->cpu_id, (long long)cpu->pc); |
cpu->cpu_id, (uint64_t) cpu->pc); |
1521 |
|
|
1522 |
debug(" <%s>\n", symbol != NULL? symbol : |
debug(" <%s>\n", symbol != NULL? symbol : |
1523 |
" no symbol "); |
" no symbol "); |
1524 |
|
|
1525 |
if (bits32) |
if (bits32) |
1526 |
debug("cpu%i: hi = %08x lo = %08x\n", |
debug("cpu%i: hi = %08"PRIx32" lo = %08"PRIx32"\n", |
1527 |
cpu->cpu_id, (int)cpu->cd.mips.hi, (int)cpu->cd.mips.lo); |
cpu->cpu_id, (uint32_t) cpu->cd.mips.hi, |
1528 |
else |
(uint32_t) cpu->cd.mips.lo); |
1529 |
debug("cpu%i: hi = 0x%016llx lo = 0x%016llx\n", |
else if (bits128) { |
1530 |
cpu->cpu_id, (long long)cpu->cd.mips.hi, |
debug("cpu%i: hi=%016"PRIx64"%016"PRIx64" lo=" |
1531 |
(long long)cpu->cd.mips.lo); |
"%016"PRIx64"%016"PRIx64"\n", cpu->cpu_id, |
1532 |
|
cpu->cd.mips.hi1, cpu->cd.mips.hi, |
1533 |
|
cpu->cd.mips.lo1, cpu->cd.mips.lo); |
1534 |
|
} else { |
1535 |
|
debug("cpu%i: hi = 0x%016"PRIx64" lo = 0x%016" |
1536 |
|
PRIx64"\n", cpu->cpu_id, |
1537 |
|
(uint64_t) cpu->cd.mips.hi, |
1538 |
|
(uint64_t) cpu->cd.mips.lo); |
1539 |
|
} |
1540 |
|
|
1541 |
/* General registers: */ |
/* General registers: */ |
1542 |
if (cpu->cd.mips.cpu_type.rev == MIPS_R5900) { |
if (bits128) { |
1543 |
/* 128-bit: */ |
/* 128-bit: */ |
1544 |
for (i=0; i<32; i++) { |
for (i=0; i<32; i++) { |
1545 |
|
int r = (i >> 1) + ((i & 1) << 4); |
1546 |
if ((i & 1) == 0) |
if ((i & 1) == 0) |
1547 |
debug("cpu%i:", cpu->cpu_id); |
debug("cpu%i:", cpu->cpu_id); |
1548 |
debug(" %3s=%016llx%016llx", |
if (r == MIPS_GPR_ZERO) |
1549 |
regname(cpu->machine, i), |
debug(" " |
1550 |
(long long)cpu->cd.mips.gpr_quadhi[i], |
" "); |
1551 |
(long long)cpu->cd.mips.gpr[i]); |
else |
1552 |
|
debug(" %3s=%016"PRIx64"%016"PRIx64, |
1553 |
|
regname(cpu->machine, r), |
1554 |
|
(uint64_t)cpu->cd.mips.gpr_quadhi[r], |
1555 |
|
(uint64_t)cpu->cd.mips.gpr[r]); |
1556 |
if ((i & 1) == 1) |
if ((i & 1) == 1) |
1557 |
debug("\n"); |
debug("\n"); |
1558 |
} |
} |
1564 |
if (i == MIPS_GPR_ZERO) |
if (i == MIPS_GPR_ZERO) |
1565 |
debug(" "); |
debug(" "); |
1566 |
else |
else |
1567 |
debug(" %3s = %08x", regname(cpu->machine, i), (int)cpu->cd.mips.gpr[i]); |
debug(" %3s = %08"PRIx32, |
1568 |
|
regname(cpu->machine, i), |
1569 |
|
(uint32_t)cpu->cd.mips.gpr[i]); |
1570 |
if ((i & 3) == 3) |
if ((i & 3) == 3) |
1571 |
debug("\n"); |
debug("\n"); |
1572 |
} |
} |
1579 |
if (r == MIPS_GPR_ZERO) |
if (r == MIPS_GPR_ZERO) |
1580 |
debug(" "); |
debug(" "); |
1581 |
else |
else |
1582 |
debug(" %3s = 0x%016llx", regname(cpu->machine, r), (long long)cpu->cd.mips.gpr[r]); |
debug(" %3s = 0x%016"PRIx64, |
1583 |
|
regname(cpu->machine, r), |
1584 |
|
(uint64_t)cpu->cd.mips.gpr[r]); |
1585 |
if ((i & 1) == 1) |
if ((i & 1) == 1) |
1586 |
debug("\n"); |
debug("\n"); |
1587 |
} |
} |
1623 |
|| i == COP0_RANDOM || i == COP0_WIRED)) |
|| i == COP0_RANDOM || i == COP0_WIRED)) |
1624 |
debug(" = 0x%08x", (int)cpu->cd.mips.coproc[coprocnr]->reg[i]); |
debug(" = 0x%08x", (int)cpu->cd.mips.coproc[coprocnr]->reg[i]); |
1625 |
else |
else |
1626 |
debug(" = 0x%016llx", (long long) |
debug(" = 0x%016"PRIx64, (uint64_t) |
1627 |
cpu->cd.mips.coproc[coprocnr]->reg[i]); |
cpu->cd.mips.coproc[coprocnr]->reg[i]); |
1628 |
} |
} |
1629 |
|
|
1640 |
debug("cpu%i: ", cpu->cpu_id); |
debug("cpu%i: ", cpu->cpu_id); |
1641 |
debug("config_select1 = 0x"); |
debug("config_select1 = 0x"); |
1642 |
if (cpu->is_32bit) |
if (cpu->is_32bit) |
1643 |
debug("%08x", (int)cpu->cd.mips.cop0_config_select1); |
debug("%08"PRIx32, (uint32_t)cpu->cd.mips.cop0_config_select1); |
1644 |
else |
else |
1645 |
debug("%016llx", (long long)cpu->cd.mips.cop0_config_select1); |
debug("%016"PRIx64, (uint64_t)cpu->cd.mips.cop0_config_select1); |
1646 |
debug("\n"); |
debug("\n"); |
1647 |
} |
} |
1648 |
|
|
1650 |
if (coprocnr == 1) { |
if (coprocnr == 1) { |
1651 |
for (i=0; i<32; i++) |
for (i=0; i<32; i++) |
1652 |
switch (i) { |
switch (i) { |
1653 |
case 0: printf("cpu%i: fcr0 (fcir) = 0x%08x\n", |
case MIPS_FPU_FCIR: |
1654 |
cpu->cpu_id, (int)cpu->cd.mips.coproc[coprocnr]->fcr[i]); |
printf("cpu%i: fcr0 (fcir) = 0x%08x\n", |
1655 |
|
cpu->cpu_id, (int)cpu->cd.mips. |
1656 |
|
coproc[coprocnr]->fcr[i]); |
1657 |
break; |
break; |
1658 |
case 25:printf("cpu%i: fcr25 (fccr) = 0x%08x\n", |
case MIPS_FPU_FCCR: |
1659 |
cpu->cpu_id, (int)cpu->cd.mips.coproc[coprocnr]->fcr[i]); |
printf("cpu%i: fcr25 (fccr) = 0x%08x\n", |
1660 |
|
cpu->cpu_id, (int)cpu->cd.mips. |
1661 |
|
coproc[coprocnr]->fcr[i]); |
1662 |
break; |
break; |
1663 |
case 31:printf("cpu%i: fcr31 (fcsr) = 0x%08x\n", |
case MIPS_FPU_FCSR: |
1664 |
cpu->cpu_id, (int)cpu->cd.mips.coproc[coprocnr]->fcr[i]); |
printf("cpu%i: fcr31 (fcsr) = 0x%08x\n", |
1665 |
|
cpu->cpu_id, (int)cpu->cd.mips. |
1666 |
|
coproc[coprocnr]->fcr[i]); |
1667 |
break; |
break; |
1668 |
} |
} |
1669 |
} |
} |
1670 |
} |
} |
1671 |
|
|
1672 |
|
if (cpu->cd.mips.rmw) { |
1673 |
|
printf("cpu%i: Read-Modify-Write in progress, address " |
1674 |
|
"0x%016"PRIx64"\n", cpu->cpu_id, cpu->cd.mips.rmw_addr); |
1675 |
|
} |
1676 |
} |
} |
1677 |
|
|
1678 |
|
|
1679 |
#define DYNTRANS_FUNCTION_TRACE mips_cpu_functioncall_trace |
static void add_response_word(struct cpu *cpu, char *r, uint64_t value, |
1680 |
#define DYNTRANS_MIPS |
size_t maxlen, int len) |
1681 |
#define DYNTRANS_ARCH mips |
{ |
1682 |
#include "cpu_dyntrans.c" |
char *format = (len == 4)? "%08"PRIx64 : "%016"PRIx64; |
1683 |
#undef DYNTRANS_MIPS |
if (len == 4) |
1684 |
#undef DYNTRANS_ARCH |
value &= 0xffffffffULL; |
1685 |
#undef DYNTRANS_FUNCTION_TRACE |
if (cpu->byte_order == EMUL_LITTLE_ENDIAN) { |
1686 |
|
if (len == 4) { |
1687 |
|
value = ((value & 0xff) << 24) + |
1688 |
|
((value & 0xff00) << 8) + |
1689 |
|
((value & 0xff0000) >> 8) + |
1690 |
|
((value & 0xff000000) >> 24); |
1691 |
|
} else { |
1692 |
|
value = ((value & 0xff) << 56) + |
1693 |
|
((value & 0xff00) << 40) + |
1694 |
|
((value & 0xff0000) << 24) + |
1695 |
|
((value & 0xff000000ULL) << 8) + |
1696 |
|
((value & 0xff00000000ULL) >> 8) + |
1697 |
|
((value & 0xff0000000000ULL) >> 24) + |
1698 |
|
((value & 0xff000000000000ULL) >> 40) + |
1699 |
|
((value & 0xff00000000000000ULL) >> 56); |
1700 |
|
} |
1701 |
|
} |
1702 |
|
snprintf(r + strlen(r), maxlen - strlen(r), format, (uint64_t)value); |
1703 |
|
} |
1704 |
|
|
1705 |
|
|
1706 |
|
/* |
1707 |
|
* mips_cpu_gdb_stub(): |
1708 |
|
* |
1709 |
|
* Execute a "remote GDB" command. Returns 1 on success, 0 on error. |
1710 |
|
*/ |
1711 |
|
char *mips_cpu_gdb_stub(struct cpu *cpu, char *cmd) |
1712 |
|
{ |
1713 |
|
if (strcmp(cmd, "g") == 0) { |
1714 |
|
/* 76 registers: gprs, sr, lo, hi, badvaddr, cause, pc, |
1715 |
|
fprs, fsr, fir, fp. */ |
1716 |
|
int i; |
1717 |
|
char *r; |
1718 |
|
size_t wlen = cpu->is_32bit? |
1719 |
|
sizeof(uint32_t) : sizeof(uint64_t); |
1720 |
|
size_t len = 1 + 76 * wlen; |
1721 |
|
r = malloc(len); |
1722 |
|
if (r == NULL) { |
1723 |
|
fprintf(stderr, "out of memory\n"); |
1724 |
|
exit(1); |
1725 |
|
} |
1726 |
|
r[0] = '\0'; |
1727 |
|
for (i=0; i<32; i++) |
1728 |
|
add_response_word(cpu, r, cpu->cd.mips.gpr[i], |
1729 |
|
len, wlen); |
1730 |
|
add_response_word(cpu, r, |
1731 |
|
cpu->cd.mips.coproc[0]->reg[COP0_STATUS], len, wlen); |
1732 |
|
add_response_word(cpu, r, cpu->cd.mips.lo, len, wlen); |
1733 |
|
add_response_word(cpu, r, cpu->cd.mips.hi, len, wlen); |
1734 |
|
add_response_word(cpu, r, |
1735 |
|
cpu->cd.mips.coproc[0]->reg[COP0_BADVADDR], len, wlen); |
1736 |
|
add_response_word(cpu, r, |
1737 |
|
cpu->cd.mips.coproc[0]->reg[COP0_CAUSE], len, wlen); |
1738 |
|
add_response_word(cpu, r, cpu->pc, len, wlen); |
1739 |
|
for (i=0; i<32; i++) |
1740 |
|
add_response_word(cpu, r, |
1741 |
|
cpu->cd.mips.coproc[1]->reg[i], len, wlen); |
1742 |
|
add_response_word(cpu, r, |
1743 |
|
cpu->cd.mips.coproc[1]->reg[31] /* fcsr */, len, wlen); |
1744 |
|
add_response_word(cpu, r, |
1745 |
|
cpu->cd.mips.coproc[1]->reg[0] /* fcir */, len, wlen); |
1746 |
|
|
1747 |
|
/* TODO: fp = gpr 30? */ |
1748 |
|
add_response_word(cpu, r, cpu->cd.mips.gpr[30], len, wlen); |
1749 |
|
|
1750 |
|
return r; |
1751 |
|
} |
1752 |
|
|
1753 |
|
if (cmd[0] == 'p') { |
1754 |
|
int regnr = strtol(cmd + 1, NULL, 16); |
1755 |
|
size_t wlen = cpu->is_32bit? sizeof(uint32_t):sizeof(uint64_t); |
1756 |
|
size_t len = 2 * wlen + 1; |
1757 |
|
char *r = malloc(len); |
1758 |
|
r[0] = '\0'; |
1759 |
|
if (regnr >= 0 && regnr <= 31) { |
1760 |
|
add_response_word(cpu, r, |
1761 |
|
cpu->cd.mips.gpr[regnr], len, wlen); |
1762 |
|
} else if (regnr == 0x20) { |
1763 |
|
add_response_word(cpu, r, cpu->cd.mips.coproc[0]-> |
1764 |
|
reg[COP0_STATUS], len, wlen); |
1765 |
|
} else if (regnr == 0x21) { |
1766 |
|
add_response_word(cpu, r, cpu->cd.mips.lo, len, wlen); |
1767 |
|
} else if (regnr == 0x22) { |
1768 |
|
add_response_word(cpu, r, cpu->cd.mips.hi, len, wlen); |
1769 |
|
} else if (regnr == 0x23) { |
1770 |
|
add_response_word(cpu, r, cpu->cd.mips.coproc[0]-> |
1771 |
|
reg[COP0_BADVADDR], len, wlen); |
1772 |
|
} else if (regnr == 0x24) { |
1773 |
|
add_response_word(cpu, r, cpu->cd.mips.coproc[0]-> |
1774 |
|
reg[COP0_CAUSE], len, wlen); |
1775 |
|
} else if (regnr == 0x25) { |
1776 |
|
add_response_word(cpu, r, cpu->pc, len, wlen); |
1777 |
|
} else if (regnr >= 0x26 && regnr <= 0x45 && |
1778 |
|
cpu->cd.mips.coproc[1] != NULL) { |
1779 |
|
add_response_word(cpu, r, cpu->cd.mips.coproc[1]-> |
1780 |
|
reg[regnr - 0x26], len, wlen); |
1781 |
|
} else if (regnr == 0x46) { |
1782 |
|
add_response_word(cpu, r, cpu->cd.mips.coproc[1]-> |
1783 |
|
fcr[MIPS_FPU_FCSR], len, wlen); |
1784 |
|
} else if (regnr == 0x47) { |
1785 |
|
add_response_word(cpu, r, cpu->cd.mips.coproc[1]-> |
1786 |
|
fcr[MIPS_FPU_FCIR], len, wlen); |
1787 |
|
} else { |
1788 |
|
/* Unimplemented: */ |
1789 |
|
add_response_word(cpu, r, 0xcc000 + regnr, len, wlen); |
1790 |
|
} |
1791 |
|
return r; |
1792 |
|
} |
1793 |
|
|
1794 |
|
fatal("mips_cpu_gdb_stub(): cmd='%s' TODO\n", cmd); |
1795 |
|
return NULL; |
1796 |
|
} |
1797 |
|
|
1798 |
|
|
1799 |
/* |
/* |
1808 |
{ |
{ |
1809 |
if (irq_nr >= 8) { |
if (irq_nr >= 8) { |
1810 |
if (cpu->machine->md_interrupt != NULL) |
if (cpu->machine->md_interrupt != NULL) |
1811 |
cpu->machine->md_interrupt(cpu->machine, cpu, irq_nr, 1); |
cpu->machine->md_interrupt(cpu->machine, |
1812 |
|
cpu, irq_nr, 1); |
1813 |
else |
else |
1814 |
fatal("mips_cpu_interrupt(): irq_nr = %i, but md_interrupt = NULL ?\n", irq_nr); |
fatal("mips_cpu_interrupt(): irq_nr = %i, " |
1815 |
|
"but md_interrupt = NULL ?\n", irq_nr); |
1816 |
return 1; |
return 1; |
1817 |
} |
} |
1818 |
|
|
1819 |
if (irq_nr < 2) |
if (irq_nr < 2) |
1820 |
return 0; |
return 0; |
1821 |
|
|
1822 |
cpu->cd.mips.coproc[0]->reg[COP0_CAUSE] |= ((1 << irq_nr) << STATUS_IM_SHIFT); |
cpu->cd.mips.coproc[0]->reg[COP0_CAUSE] |= |
1823 |
cpu->cd.mips.cached_interrupt_is_possible = 1; |
((1 << irq_nr) << STATUS_IM_SHIFT); |
1824 |
|
|
1825 |
return 1; |
return 1; |
1826 |
} |
} |
1827 |
|
|
1832 |
* Acknowledge an interrupt. If irq_nr is 2..7, then it is a MIPS hardware |
* Acknowledge an interrupt. If irq_nr is 2..7, then it is a MIPS hardware |
1833 |
* interrupt. Interrupts 0..1 are ignored (software interrupts). |
* interrupt. Interrupts 0..1 are ignored (software interrupts). |
1834 |
* |
* |
1835 |
* If irq_nr is >= 8, then it is machine dependant, and md_interrupt() is |
* If irq_nr is >= 8, then it is machine dependent, and md_interrupt() is |
1836 |
* called. |
* called. |
1837 |
*/ |
*/ |
1838 |
int mips_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr) |
int mips_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr) |
1839 |
{ |
{ |
1840 |
if (irq_nr >= 8) { |
if (irq_nr >= 8) { |
1841 |
if (cpu->machine->md_interrupt != NULL) |
if (cpu->machine->md_interrupt != NULL) |
1842 |
cpu->machine->md_interrupt(cpu->machine, cpu, irq_nr, 0); |
cpu->machine->md_interrupt(cpu->machine, cpu, |
1843 |
|
irq_nr, 0); |
1844 |
else |
else |
1845 |
fatal("mips_cpu_interrupt_ack(): irq_nr = %i, but md_interrupt = NULL ?\n", irq_nr); |
fatal("mips_cpu_interrupt_ack(): irq_nr = %i, " |
1846 |
|
"but md_interrupt = NULL ?\n", irq_nr); |
1847 |
return 1; |
return 1; |
1848 |
} |
} |
1849 |
|
|
1850 |
if (irq_nr < 2) |
if (irq_nr < 2) |
1851 |
return 0; |
return 0; |
1852 |
|
|
1853 |
cpu->cd.mips.coproc[0]->reg[COP0_CAUSE] &= ~((1 << irq_nr) << STATUS_IM_SHIFT); |
cpu->cd.mips.coproc[0]->reg[COP0_CAUSE] &= |
1854 |
if (!(cpu->cd.mips.coproc[0]->reg[COP0_CAUSE] & STATUS_IM_MASK)) |
~((1 << irq_nr) << STATUS_IM_SHIFT); |
|
cpu->cd.mips.cached_interrupt_is_possible = 0; |
|
1855 |
|
|
1856 |
return 1; |
return 1; |
1857 |
} |
} |
1883 |
uint64_t offset; |
uint64_t offset; |
1884 |
int x; |
int x; |
1885 |
char *symbol = get_symbol_name(&cpu->machine->symbol_context, |
char *symbol = get_symbol_name(&cpu->machine->symbol_context, |
1886 |
cpu->cd.mips.pc_last, &offset); |
cpu->pc, &offset); |
1887 |
|
|
1888 |
debug("[ "); |
debug("[ "); |
1889 |
if (cpu->machine->ncpus > 1) |
if (cpu->machine->ncpus > 1) |
1893 |
exception_names[exccode], tlb? " <tlb>" : ""); |
exception_names[exccode], tlb? " <tlb>" : ""); |
1894 |
|
|
1895 |
switch (exccode) { |
switch (exccode) { |
1896 |
|
|
1897 |
case EXCEPTION_INT: |
case EXCEPTION_INT: |
1898 |
debug(" cause_im=0x%02x", (int)((reg[COP0_CAUSE] & CAUSE_IP_MASK) >> CAUSE_IP_SHIFT)); |
debug(" cause_im=0x%02x", (int)((reg[COP0_CAUSE] & CAUSE_IP_MASK) >> CAUSE_IP_SHIFT)); |
1899 |
break; |
break; |
1900 |
|
|
1901 |
case EXCEPTION_SYS: |
case EXCEPTION_SYS: |
1902 |
debug(" v0=%i", (int)cpu->cd.mips.gpr[MIPS_GPR_V0]); |
debug(" v0=%i", (int)cpu->cd.mips.gpr[MIPS_GPR_V0]); |
1903 |
for (x=0; x<4; x++) { |
for (x=0; x<4; x++) { |
1904 |
int64_t d = cpu->cd.mips.gpr[MIPS_GPR_A0 + x]; |
int64_t d = cpu->cd.mips.gpr[MIPS_GPR_A0 + x]; |
1905 |
char strbuf[30]; |
char strbuf[30]; |
1906 |
|
|
1907 |
if (d > -256 && d < 256) |
if (d > -256 && d < 256) { |
1908 |
debug(" a%i=%i", x, (int)d); |
debug(" a%i=%i", x, (int)d); |
1909 |
else if (memory_points_to_string(cpu, cpu->mem, d, 1)) |
} else if (memory_points_to_string(cpu, |
1910 |
debug(" a%i=\"%s\"", x, memory_conv_to_string(cpu, cpu->mem, d, strbuf, sizeof(strbuf))); |
cpu->mem, d, 1)) { |
1911 |
else |
debug(" a%i=\"%s\"", x, |
1912 |
debug(" a%i=0x%llx", x, (long long)d); |
memory_conv_to_string(cpu, cpu->mem, |
1913 |
|
d, strbuf, sizeof(strbuf))); |
1914 |
|
} else { |
1915 |
|
if (cpu->is_32bit) |
1916 |
|
debug(" a%i=0x%"PRIx32, x, |
1917 |
|
(uint32_t)d); |
1918 |
|
else |
1919 |
|
debug(" a%i=0x%"PRIx64, x, |
1920 |
|
(uint64_t)d); |
1921 |
|
} |
1922 |
} |
} |
1923 |
break; |
break; |
1924 |
|
|
1925 |
|
case EXCEPTION_CPU: |
1926 |
|
debug(" coproc_nr=%i", coproc_nr); |
1927 |
|
break; |
1928 |
|
|
1929 |
default: |
default: |
1930 |
if (cpu->is_32bit) |
if (cpu->is_32bit) |
1931 |
debug(" vaddr=0x%08x", (int)vaddr); |
debug(" vaddr=0x%08x", (int)vaddr); |
1932 |
else |
else |
1933 |
debug(" vaddr=0x%016llx", (long long)vaddr); |
debug(" vaddr=0x%016"PRIx64, (uint64_t)vaddr); |
1934 |
} |
} |
1935 |
|
|
1936 |
if (cpu->is_32bit) |
if (cpu->is_32bit) |
1937 |
debug(" pc=0x%08x ", (int)cpu->cd.mips.pc_last); |
debug(" pc=0x%08"PRIx32" ", (uint32_t)cpu->pc); |
1938 |
else |
else |
1939 |
debug(" pc=0x%016llx ", (long long)cpu->cd.mips.pc_last); |
debug(" pc=0x%016"PRIx64" ", (uint64_t)cpu->pc); |
1940 |
|
|
1941 |
if (symbol != NULL) |
if (symbol != NULL) |
1942 |
debug("<%s> ]\n", symbol); |
debug("<%s> ]\n", symbol); |
1947 |
if (tlb && vaddr < 0x1000) { |
if (tlb && vaddr < 0x1000) { |
1948 |
uint64_t offset; |
uint64_t offset; |
1949 |
char *symbol = get_symbol_name(&cpu->machine->symbol_context, |
char *symbol = get_symbol_name(&cpu->machine->symbol_context, |
1950 |
cpu->cd.mips.pc_last, &offset); |
cpu->pc, &offset); |
1951 |
fatal("[ "); |
fatal("[ "); |
1952 |
if (cpu->machine->ncpus > 1) |
if (cpu->machine->ncpus > 1) |
1953 |
fatal("cpu%i: ", cpu->cpu_id); |
fatal("cpu%i: ", cpu->cpu_id); |
1954 |
fatal("warning: LOW reference: vaddr="); |
fatal("warning: LOW reference: vaddr="); |
1955 |
if (cpu->is_32bit) |
if (cpu->is_32bit) |
1956 |
fatal("0x%08x", (int)vaddr); |
fatal("0x%08"PRIx32, (uint32_t) vaddr); |
1957 |
else |
else |
1958 |
fatal("0x%016llx", (long long)vaddr); |
fatal("0x%016"PRIx64, (uint64_t) vaddr); |
1959 |
fatal(", exception %s, pc=", exception_names[exccode]); |
fatal(", exception %s, pc=", exception_names[exccode]); |
1960 |
if (cpu->is_32bit) |
if (cpu->is_32bit) |
1961 |
fatal("0x%08x", (int)cpu->cd.mips.pc_last); |
fatal("0x%08"PRIx32, (uint32_t) cpu->pc); |
1962 |
else |
else |
1963 |
fatal("0x%016llx", (long long)cpu->cd.mips.pc_last); |
fatal("0x%016"PRIx64, (uint64_t)cpu->pc); |
1964 |
fatal(" <%s> ]\n", symbol? symbol : "(no symbol)"); |
fatal(" <%s> ]\n", symbol? symbol : "(no symbol)"); |
|
|
|
|
#ifdef TRACE_NULL_CRASHES |
|
|
/* This can be useful for debugging kernel bugs: */ |
|
|
{ |
|
|
int i = cpu->trace_null_index; |
|
|
do { |
|
|
fatal("TRACE: 0x%016llx\n", |
|
|
cpu->trace_null_addr[i]); |
|
|
i ++; |
|
|
i %= TRACE_NULL_N_ENTRIES; |
|
|
} while (i != cpu->trace_null_index); |
|
|
} |
|
|
cpu->running = 0; |
|
|
cpu->dead = 1; |
|
|
#endif |
|
1965 |
} |
} |
1966 |
|
|
1967 |
/* Clear the exception code bits of the cause register... */ |
/* Clear the exception code bits of the cause register... */ |
1980 |
if (tlb || (exccode >= EXCEPTION_MOD && exccode <= EXCEPTION_ADES) || |
if (tlb || (exccode >= EXCEPTION_MOD && exccode <= EXCEPTION_ADES) || |
1981 |
exccode == EXCEPTION_VCEI || exccode == EXCEPTION_VCED) { |
exccode == EXCEPTION_VCEI || exccode == EXCEPTION_VCED) { |
1982 |
reg[COP0_BADVADDR] = vaddr; |
reg[COP0_BADVADDR] = vaddr; |
1983 |
#if 1 |
if (cpu->is_32bit) |
1984 |
/* TODO: This should be removed. */ |
reg[COP0_BADVADDR] = (int32_t)reg[COP0_BADVADDR]; |
1985 |
/* sign-extend vaddr, if it is 32-bit */ |
|
|
if ((vaddr >> 32) == 0 && (vaddr & 0x80000000ULL)) |
|
|
reg[COP0_BADVADDR] |= |
|
|
0xffffffff00000000ULL; |
|
|
#endif |
|
1986 |
if (exc_model == EXC3K) { |
if (exc_model == EXC3K) { |
1987 |
reg[COP0_CONTEXT] &= ~R2K3K_CONTEXT_BADVPN_MASK; |
reg[COP0_CONTEXT] &= ~R2K3K_CONTEXT_BADVPN_MASK; |
1988 |
reg[COP0_CONTEXT] |= ((vaddr_vpn2 << R2K3K_CONTEXT_BADVPN_SHIFT) & R2K3K_CONTEXT_BADVPN_MASK); |
reg[COP0_CONTEXT] |= ((vaddr_vpn2 << R2K3K_CONTEXT_BADVPN_SHIFT) & R2K3K_CONTEXT_BADVPN_MASK); |
2026 |
} |
} |
2027 |
} |
} |
2028 |
|
|
2029 |
if (exc_model == EXC4K && reg[COP0_STATUS] & STATUS_EXL) { |
if (exc_model != EXC3K && reg[COP0_STATUS] & STATUS_EXL) { |
2030 |
/* |
/* |
2031 |
* Don't set EPC if STATUS_EXL is set, for R4000 and up. |
* Don't set EPC if STATUS_EXL is set, for R4000 and up. |
2032 |
* This actually happens when running IRIX and Ultrix, when |
* This actually happens when running IRIX and Ultrix, when |
2033 |
* they handle interrupts and/or tlb updates, I think, so |
* they handle interrupts and/or tlb updates, I think, so |
2034 |
* printing this with debug() looks better than with fatal(). |
* printing this with debug() looks better than with fatal(). |
2035 |
*/ |
*/ |
2036 |
/* debug("[ warning: cpu%i exception while EXL is set, not setting EPC ]\n", cpu->cpu_id); */ |
/* debug("[ warning: cpu%i exception while EXL is set," |
2037 |
|
" not setting EPC ]\n", cpu->cpu_id); */ |
2038 |
} else { |
} else { |
2039 |
if (cpu->cd.mips.delay_slot || cpu->cd.mips.nullify_next) { |
if (cpu->delay_slot || cpu->cd.mips.nullify_next) { |
2040 |
reg[COP0_EPC] = cpu->cd.mips.pc_last - 4; |
reg[COP0_EPC] = cpu->pc - 4; |
2041 |
reg[COP0_CAUSE] |= CAUSE_BD; |
reg[COP0_CAUSE] |= CAUSE_BD; |
2042 |
|
|
2043 |
/* TODO: Should the BD flag actually be set |
/* TODO: Should the BD flag actually be set |
2044 |
on nullified slots? */ |
on nullified slots? */ |
2045 |
} else { |
} else { |
2046 |
reg[COP0_EPC] = cpu->cd.mips.pc_last; |
reg[COP0_EPC] = cpu->pc; |
2047 |
reg[COP0_CAUSE] &= ~CAUSE_BD; |
reg[COP0_CAUSE] &= ~CAUSE_BD; |
2048 |
} |
} |
2049 |
} |
} |
2050 |
|
|
2051 |
cpu->cd.mips.delay_slot = NOT_DELAYED; |
if (cpu->delay_slot) |
2052 |
|
cpu->delay_slot = EXCEPTION_IN_DELAY_SLOT; |
2053 |
|
else |
2054 |
|
cpu->delay_slot = NOT_DELAYED; |
2055 |
|
|
2056 |
cpu->cd.mips.nullify_next = 0; |
cpu->cd.mips.nullify_next = 0; |
2057 |
|
|
2058 |
/* TODO: This is true for MIPS64, but how about others? */ |
/* TODO: This is true for MIPS64, but how about others? */ |
2098 |
} |
} |
2099 |
|
|
2100 |
if (exc_model == EXC3K) { |
if (exc_model == EXC3K) { |
2101 |
/* R2000/R3000: Shift the lowest 6 bits to the left two steps: */ |
/* R{2,3}000: Shift the lowest 6 bits to the left two steps:*/ |
2102 |
reg[COP0_STATUS] = |
reg[COP0_STATUS] = (reg[COP0_STATUS] & ~0x3f) + |
|
(reg[COP0_STATUS] & ~0x3f) + |
|
2103 |
((reg[COP0_STATUS] & 0xf) << 2); |
((reg[COP0_STATUS] & 0xf) << 2); |
2104 |
} else { |
} else { |
2105 |
/* R4000: */ |
/* R4000: */ |
2109 |
/* Sign-extend: */ |
/* Sign-extend: */ |
2110 |
reg[COP0_CAUSE] = (int64_t)(int32_t)reg[COP0_CAUSE]; |
reg[COP0_CAUSE] = (int64_t)(int32_t)reg[COP0_CAUSE]; |
2111 |
reg[COP0_STATUS] = (int64_t)(int32_t)reg[COP0_STATUS]; |
reg[COP0_STATUS] = (int64_t)(int32_t)reg[COP0_STATUS]; |
|
} |
|
|
|
|
|
|
|
|
#ifdef BINTRANS |
|
|
/* |
|
|
* mips_cpu_cause_simple_exception(): |
|
|
* |
|
|
* Useful for causing raw exceptions from bintrans, for example |
|
|
* SYSCALL or BREAK. |
|
|
*/ |
|
|
void mips_cpu_cause_simple_exception(struct cpu *cpu, int exc_code) |
|
|
{ |
|
|
mips_cpu_exception(cpu, exc_code, 0, 0, 0, 0, 0, 0); |
|
|
} |
|
|
#endif |
|
|
|
|
|
|
|
|
/* Included here for better cache characteristics: */ |
|
|
#include "memory_mips.c" |
|
|
|
|
|
|
|
|
/* |
|
|
* mips_cpu_run_instr(): |
|
|
* |
|
|
* Execute one instruction on a cpu. |
|
|
* |
|
|
* If we are in a delay slot, set cpu->pc to cpu->cd.mips.delay_jmpaddr |
|
|
* after the instruction is executed. |
|
|
* |
|
|
* Return value is the number of instructions executed during this call, |
|
|
* 0 if no instruction was executed. |
|
|
*/ |
|
|
int mips_cpu_run_instr(struct emul *emul, struct cpu *cpu) |
|
|
{ |
|
|
int quiet_mode_cached = quiet_mode; |
|
|
int instruction_trace_cached = cpu->machine->instruction_trace; |
|
|
struct mips_coproc *cp0 = cpu->cd.mips.coproc[0]; |
|
|
int i, tmp, ninstrs_executed; |
|
|
unsigned char instr[4]; |
|
|
uint32_t instrword; |
|
|
uint64_t cached_pc; |
|
|
int hi6, special6, regimm5, rd, rs, rt, sa, imm; |
|
|
int copz, which_cache, cache_op; |
|
|
|
|
|
int cond, likely, and_link; |
|
|
|
|
|
/* for unaligned load/store */ |
|
|
uint64_t dir, is_left, reg_ofs, reg_dir; |
|
|
|
|
|
uint64_t tmpvalue, tmpaddr; |
|
|
|
|
|
int cpnr; /* coprocessor nr */ |
|
|
|
|
|
/* for load/store */ |
|
|
uint64_t addr, value, value_hi, result_value; |
|
|
int wlen, st, signd, linked; |
|
|
unsigned char d[16]; /* room for at most 128 bits */ |
|
|
|
|
|
|
|
|
/* |
|
|
* Update Coprocessor 0 registers: |
|
|
* |
|
|
* The COUNT register needs to be updated on every [other] instruction. |
|
|
* The RANDOM register should decrease for every instruction. |
|
|
*/ |
|
|
|
|
|
if (cpu->cd.mips.cpu_type.exc_model == EXC3K) { |
|
|
int r = (cp0->reg[COP0_RANDOM] & R2K3K_RANDOM_MASK) >> R2K3K_RANDOM_SHIFT; |
|
|
r --; |
|
|
if (r >= cp0->nr_of_tlbs || r < 8) |
|
|
r = cp0->nr_of_tlbs-1; |
|
|
cp0->reg[COP0_RANDOM] = r << R2K3K_RANDOM_SHIFT; |
|
|
} else { |
|
|
cp0->reg[COP0_RANDOM] --; |
|
|
if ((int64_t)cp0->reg[COP0_RANDOM] >= cp0->nr_of_tlbs || |
|
|
(int64_t)cp0->reg[COP0_RANDOM] < (int64_t) cp0->reg[COP0_WIRED]) |
|
|
cp0->reg[COP0_RANDOM] = cp0->nr_of_tlbs-1; |
|
|
|
|
|
/* |
|
|
* TODO: only increase count every other instruction, |
|
|
* according to the R4000 manual. But according to the |
|
|
* R5000 manual: increment every other clock cycle. |
|
|
* Which one is it? :-) |
|
|
*/ |
|
|
cp0->reg[COP0_COUNT] = (int64_t)(int32_t)(cp0->reg[COP0_COUNT] + 1); |
|
|
|
|
|
if (cpu->cd.mips.compare_register_set && |
|
|
cp0->reg[COP0_COUNT] == cp0->reg[COP0_COMPARE]) { |
|
|
mips_cpu_interrupt(cpu, 7); |
|
|
cpu->cd.mips.compare_register_set = 0; |
|
|
} |
|
|
} |
|
|
|
|
|
|
|
|
#ifdef ENABLE_INSTRUCTION_DELAYS |
|
|
if (cpu->cd.mips.instruction_delay > 0) { |
|
|
cpu->cd.mips.instruction_delay --; |
|
|
return 1; |
|
|
} |
|
|
#endif |
|
|
|
|
|
/* Cache the program counter in a local variable: */ |
|
|
cached_pc = cpu->pc; |
|
|
|
|
|
#ifdef TRACE_NULL_CRASHES |
|
|
cpu->trace_null_addr[cpu->trace_null_index] = cached_pc; |
|
|
cpu->trace_null_index ++; |
|
|
cpu->trace_null_index %= TRACE_NULL_N_ENTRIES; |
|
|
#endif |
|
|
|
|
|
/* Hardwire the zero register to 0: */ |
|
|
cpu->cd.mips.gpr[MIPS_GPR_ZERO] = 0; |
|
|
|
|
|
if (cpu->cd.mips.delay_slot) { |
|
|
if (cpu->cd.mips.delay_slot == DELAYED) { |
|
|
cached_pc = cpu->pc = cpu->cd.mips.delay_jmpaddr; |
|
|
cpu->cd.mips.delay_slot = NOT_DELAYED; |
|
|
} else /* if (cpu->cd.mips.delay_slot == TO_BE_DELAYED) */ { |
|
|
/* next instruction will be delayed */ |
|
|
cpu->cd.mips.delay_slot = DELAYED; |
|
|
} |
|
|
} |
|
|
|
|
|
if (cpu->cd.mips.last_was_jumptoself > 0) |
|
|
cpu->cd.mips.last_was_jumptoself --; |
|
|
|
|
|
/* Check PC against breakpoints: */ |
|
|
if (!single_step) |
|
|
for (i=0; i<cpu->machine->n_breakpoints; i++) |
|
|
if (cached_pc == cpu->machine->breakpoint_addr[i]) { |
|
|
fatal("Breakpoint reached, pc=0x"); |
|
|
if (cpu->is_32bit) |
|
|
fatal("%08x", (int)cached_pc); |
|
|
else |
|
|
fatal("%016llx", (long long)cached_pc); |
|
|
fatal("\n"); |
|
|
single_step = 1; |
|
|
return 0; |
|
|
} |
|
|
|
|
|
|
|
|
/* Remember where we are, in case of interrupt or exception: */ |
|
|
cpu->cd.mips.pc_last = cached_pc; |
|
|
|
|
|
/* |
|
|
* Any pending interrupts? |
|
|
* |
|
|
* If interrupts are enabled, and any interrupt has arrived (ie its |
|
|
* bit in the cause register is set) and corresponding enable bits |
|
|
* in the status register are set, then cause an interrupt exception |
|
|
* instead of executing the current instruction. |
|
|
* |
|
|
* NOTE: cached_interrupt_is_possible is set to 1 whenever an |
|
|
* interrupt bit in the cause register is set to one (in |
|
|
* mips_cpu_interrupt()) and set to 0 whenever all interrupt bits are |
|
|
* cleared (in mips_cpu_interrupt_ack()), so we don't need to do a |
|
|
* full check each time. |
|
|
*/ |
|
|
if (cpu->cd.mips.cached_interrupt_is_possible && !cpu->cd.mips.nullify_next) { |
|
|
if (cpu->cd.mips.cpu_type.exc_model == EXC3K) { |
|
|
/* R3000: */ |
|
|
int enabled, mask; |
|
|
int status = cp0->reg[COP0_STATUS]; |
|
|
|
|
|
enabled = status & MIPS_SR_INT_IE; |
|
|
mask = status & cp0->reg[COP0_CAUSE] & STATUS_IM_MASK; |
|
|
if (enabled && mask) { |
|
|
mips_cpu_exception(cpu, EXCEPTION_INT, 0, 0, 0, 0, 0, 0); |
|
|
return 0; |
|
|
} |
|
|
} else { |
|
|
/* R4000 and others: */ |
|
|
int enabled, mask; |
|
|
int status = cp0->reg[COP0_STATUS]; |
|
|
|
|
|
enabled = (status & STATUS_IE) |
|
|
&& !(status & STATUS_EXL) |
|
|
&& !(status & STATUS_ERL); |
|
|
|
|
|
mask = status & cp0->reg[COP0_CAUSE] & STATUS_IM_MASK; |
|
|
if (enabled && mask) { |
|
|
mips_cpu_exception(cpu, EXCEPTION_INT, 0, 0, 0, 0, 0, 0); |
|
|
return 0; |
|
|
} |
|
|
} |
|
|
} |
|
|
|
|
|
|
|
|
/* |
|
|
* ROM emulation: (0xbfcXXXXX or 0x9fcXXXXX) |
|
|
* |
|
|
* This assumes that a jal was made to a ROM address, |
|
|
* and we should return via gpr ra. |
|
|
*/ |
|
|
if ((cached_pc & 0xdff00000) == 0x9fc00000 && |
|
|
cpu->machine->prom_emulation) { |
|
|
int rom_jal = 1, res = 1; |
|
|
switch (cpu->machine->machine_type) { |
|
|
case MACHINE_DEC: |
|
|
res = decstation_prom_emul(cpu); |
|
|
break; |
|
|
case MACHINE_PS2: |
|
|
res = playstation2_sifbios_emul(cpu); |
|
|
break; |
|
|
case MACHINE_ARC: |
|
|
case MACHINE_SGI: |
|
|
res = arcbios_emul(cpu); |
|
|
break; |
|
|
case MACHINE_EVBMIPS: |
|
|
res = yamon_emul(cpu); |
|
|
break; |
|
|
default: |
|
|
rom_jal = 0; |
|
|
} |
|
|
|
|
|
if (rom_jal) { |
|
|
/* |
|
|
* Special hack: If the PROM emulation layer needs |
|
|
* to loop (for example when emulating blocking |
|
|
* console input) then we should simply return, so |
|
|
* that the same PROM routine is called on the next |
|
|
* round as well. |
|
|
* |
|
|
* This still has to count as one or more |
|
|
* instructions, so 1000 is returned. (Ugly.) |
|
|
*/ |
|
|
if (!res) |
|
|
return 1000; |
|
|
|
|
|
cpu->pc = cpu->cd.mips.gpr[MIPS_GPR_RA]; |
|
|
/* no need to update cached_pc, as we're returning */ |
|
|
cpu->cd.mips.delay_slot = NOT_DELAYED; |
|
2112 |
|
|
|
if (cpu->machine->show_trace_tree) |
|
|
cpu_functioncall_trace_return(cpu); |
|
|
|
|
|
/* TODO: how many instrs should this count as? */ |
|
|
return 10; |
|
|
} |
|
|
} |
|
|
|
|
|
#ifdef ALWAYS_SIGNEXTEND_32 |
|
|
/* |
|
|
* An extra check for 32-bit mode to make sure that all |
|
|
* registers are sign-extended: (Slow, but might be useful |
|
|
* to detect bugs that have to do with sign-extension.) |
|
|
*/ |
|
2113 |
if (cpu->is_32bit) { |
if (cpu->is_32bit) { |
2114 |
int warning = 0; |
reg[COP0_EPC] = (int64_t)(int32_t)reg[COP0_EPC]; |
2115 |
uint64_t x; |
mips32_pc_to_pointers(cpu); |
2116 |
|
} else { |
2117 |
if (cpu->cd.mips.gpr[0] != 0) { |
mips_pc_to_pointers(cpu); |
|
fatal("\nWARNING: r0 was not zero! (%016llx)\n\n", |
|
|
(long long)cpu->cd.mips.gpr[0]); |
|
|
cpu->cd.mips.gpr[0] = 0; |
|
|
warning = 1; |
|
|
} |
|
|
|
|
|
if (cpu->pc != (int64_t)(int32_t)cpu->pc) { |
|
|
fatal("\nWARNING: pc was not sign-extended correctly" |
|
|
" (%016llx)\n\n", (long long)cpu->pc); |
|
|
cpu->pc = (int64_t)(int32_t)cpu->pc; |
|
|
warning = 1; |
|
|
} |
|
|
|
|
|
if (cpu->cd.mips.pc_last != (int64_t)(int32_t)cpu->cd.mips.pc_last) { |
|
|
fatal("\nWARNING: pc_last was not sign-extended correc" |
|
|
"tly (%016llx)\n\n", (long long)cpu->cd.mips.pc_last); |
|
|
cpu->cd.mips.pc_last = (int64_t)(int32_t)cpu->cd.mips.pc_last; |
|
|
warning = 1; |
|
|
} |
|
|
|
|
|
/* Sign-extend ALL registers, including coprocessor registers and tlbs: */ |
|
|
for (i=1; i<32; i++) { |
|
|
x = cpu->cd.mips.gpr[i]; |
|
|
cpu->cd.mips.gpr[i] &= 0xffffffff; |
|
|
if (cpu->cd.mips.gpr[i] & 0x80000000ULL) |
|
|
cpu->cd.mips.gpr[i] |= 0xffffffff00000000ULL; |
|
|
if (x != cpu->cd.mips.gpr[i]) { |
|
|
fatal("\nWARNING: r%i (%s) was not sign-" |
|
|
"extended correctly (%016llx != " |
|
|
"%016llx)\n\n", i, regname(cpu->machine, i), |
|
|
(long long)x, (long long)cpu->cd.mips.gpr[i]); |
|
|
warning = 1; |
|
|
} |
|
|
} |
|
|
for (i=0; i<32; i++) { |
|
|
x = cpu->cd.mips.coproc[0]->reg[i]; |
|
|
cpu->cd.mips.coproc[0]->reg[i] &= 0xffffffffULL; |
|
|
if (cpu->cd.mips.coproc[0]->reg[i] & 0x80000000ULL) |
|
|
cpu->cd.mips.coproc[0]->reg[i] |= |
|
|
0xffffffff00000000ULL; |
|
|
if (x != cpu->cd.mips.coproc[0]->reg[i]) { |
|
|
fatal("\nWARNING: cop0,r%i was not sign-extended correctly (%016llx != %016llx)\n\n", |
|
|
i, (long long)x, (long long)cpu->cd.mips.coproc[0]->reg[i]); |
|
|
warning = 1; |
|
|
} |
|
|
} |
|
|
for (i=0; i<cpu->cd.mips.coproc[0]->nr_of_tlbs; i++) { |
|
|
x = cpu->cd.mips.coproc[0]->tlbs[i].hi; |
|
|
cpu->cd.mips.coproc[0]->tlbs[i].hi &= 0xffffffffULL; |
|
|
if (cpu->cd.mips.coproc[0]->tlbs[i].hi & 0x80000000ULL) |
|
|
cpu->cd.mips.coproc[0]->tlbs[i].hi |= |
|
|
0xffffffff00000000ULL; |
|
|
if (x != cpu->cd.mips.coproc[0]->tlbs[i].hi) { |
|
|
fatal("\nWARNING: tlb[%i].hi was not sign-extended correctly (%016llx != %016llx)\n\n", |
|
|
i, (long long)x, (long long)cpu->cd.mips.coproc[0]->tlbs[i].hi); |
|
|
warning = 1; |
|
|
} |
|
|
|
|
|
x = cpu->cd.mips.coproc[0]->tlbs[i].lo0; |
|
|
cpu->cd.mips.coproc[0]->tlbs[i].lo0 &= 0xffffffffULL; |
|
|
if (cpu->cd.mips.coproc[0]->tlbs[i].lo0 & 0x80000000ULL) |
|
|
cpu->cd.mips.coproc[0]->tlbs[i].lo0 |= |
|
|
0xffffffff00000000ULL; |
|
|
if (x != cpu->cd.mips.coproc[0]->tlbs[i].lo0) { |
|
|
fatal("\nWARNING: tlb[%i].lo0 was not sign-extended correctly (%016llx != %016llx)\n\n", |
|
|
i, (long long)x, (long long)cpu->cd.mips.coproc[0]->tlbs[i].lo0); |
|
|
warning = 1; |
|
|
} |
|
|
} |
|
|
|
|
|
if (warning) { |
|
|
fatal("Halting. pc = %016llx\n", (long long)cpu->pc); |
|
|
cpu->running = 0; |
|
|
} |
|
|
} |
|
|
#endif |
|
|
|
|
|
PREFETCH(cpu->cd.mips.pc_last_host_4k_page + (cached_pc & 0xfff)); |
|
|
|
|
|
#ifdef HALT_IF_PC_ZERO |
|
|
/* Halt if PC = 0: */ |
|
|
if (cached_pc == 0) { |
|
|
debug("cpu%i: pc=0, halting\n", cpu->cpu_id); |
|
|
cpu->running = 0; |
|
|
return 0; |
|
|
} |
|
|
#endif |
|
|
|
|
|
#ifdef BINTRANS |
|
|
if ((single_step || instruction_trace_cached) |
|
|
&& cpu->machine->bintrans_enable) |
|
|
cpu->cd.mips.dont_run_next_bintrans = 1; |
|
|
#endif |
|
|
|
|
|
if (!quiet_mode_cached) { |
|
|
/* Dump CPU registers for debugging: */ |
|
|
if (cpu->machine->register_dump) { |
|
|
debug("\n"); |
|
|
mips_cpu_register_dump(cpu, 1, 0x1); |
|
|
} |
|
|
} |
|
|
|
|
|
/* Trace tree: */ |
|
|
if (cpu->machine->show_trace_tree && cpu->cd.mips.show_trace_delay > 0) { |
|
|
cpu->cd.mips.show_trace_delay --; |
|
|
if (cpu->cd.mips.show_trace_delay == 0) |
|
|
cpu_functioncall_trace(cpu, cpu->cd.mips.show_trace_addr); |
|
|
} |
|
|
|
|
|
#ifdef MFHILO_DELAY |
|
|
/* Decrease the MFHI/MFLO delays: */ |
|
|
if (cpu->mfhi_delay > 0) |
|
|
cpu->mfhi_delay--; |
|
|
if (cpu->mflo_delay > 0) |
|
|
cpu->mflo_delay--; |
|
|
#endif |
|
|
|
|
|
/* Read an instruction from memory: */ |
|
|
#ifdef ENABLE_MIPS16 |
|
|
if (cpu->cd.mips.mips16 && (cached_pc & 1)) { |
|
|
/* 16-bit instruction word: */ |
|
|
unsigned char instr16[2]; |
|
|
int mips16_offset = 0; |
|
|
|
|
|
if (!cpu->memory_rw(cpu, cpu->mem, cached_pc ^ 1, &instr16[0], |
|
|
sizeof(instr16), MEM_READ, CACHE_INSTRUCTION)) |
|
|
return 0; |
|
|
|
|
|
/* TODO: If Reverse-endian is set in the status cop0 register, and |
|
|
we are in usermode, then reverse endianness! */ |
|
|
|
|
|
/* The rest of the code is written for little endian, so swap if necessary: */ |
|
|
if (cpu->byte_order == EMUL_BIG_ENDIAN) { |
|
|
int tmp; |
|
|
tmp = instr16[0]; instr16[0] = instr16[1]; instr16[1] = tmp; |
|
|
} |
|
|
|
|
|
cpu->cd.mips.mips16_extend = 0; |
|
|
|
|
|
/* |
|
|
* Translate into 32-bit instruction, little endian (instr[3..0]): |
|
|
* |
|
|
* This ugly loop is necessary because if we would get an exception between |
|
|
* reading an extend instruction and the next instruction, and execution |
|
|
* continues on the second instruction, the extend data would be lost. So the |
|
|
* entire instruction (the two parts) need to be read in. If an exception is |
|
|
* caused, it will appear as if it was caused when reading the extend instruction. |
|
|
*/ |
|
|
while (mips16_to_32(cpu, instr16, instr) == 0) { |
|
|
if (instruction_trace_cached) |
|
|
debug("cpu%i @ %016llx: %02x%02x\t\t\textend\n", |
|
|
cpu->cpu_id, (cpu->cd.mips.pc_last ^ 1) + mips16_offset, |
|
|
instr16[1], instr16[0]); |
|
|
|
|
|
/* instruction with extend: */ |
|
|
mips16_offset += 2; |
|
|
if (!cpu->memory_rw(cpu, cpu->mem, (cached_pc ^ 1) + |
|
|
mips16_offset, &instr16[0], sizeof(instr16), |
|
|
MEM_READ, CACHE_INSTRUCTION)) |
|
|
return 0; |
|
|
|
|
|
if (cpu->byte_order == EMUL_BIG_ENDIAN) { |
|
|
int tmp; |
|
|
tmp = instr16[0]; instr16[0] = instr16[1]; instr16[1] = tmp; |
|
|
} |
|
|
} |
|
|
|
|
|
/* TODO: bintrans like in 32-bit mode? */ |
|
|
|
|
|
/* Advance the program counter: */ |
|
|
cpu->pc += sizeof(instr16) + mips16_offset; |
|
|
cached_pc = cpu->pc; |
|
|
|
|
|
if (instruction_trace_cached) { |
|
|
uint64_t offset; |
|
|
char *symbol = get_symbol_name(&cpu->machine-> |
|
|
symbol_context, cpu->cd.mips.pc_last ^ 1, &offset); |
|
|
if (symbol != NULL && offset==0) |
|
|
debug("<%s>\n", symbol); |
|
|
|
|
|
debug("cpu%i @ %016llx: %02x%02x => %02x%02x%02x%02x%s\t", |
|
|
cpu->cpu_id, (cpu->cd.mips.pc_last ^ 1) + mips16_offset, |
|
|
instr16[1], instr16[0], |
|
|
instr[3], instr[2], instr[1], instr[0], |
|
|
cpu_flags(cpu)); |
|
|
} |
|
|
} else |
|
|
#endif |
|
|
{ |
|
|
/* |
|
|
* Fetch a 32-bit instruction word from memory: |
|
|
* |
|
|
* 1) The special case of reading an instruction from the |
|
|
* same host RAM page as the last one is handled here, |
|
|
* to gain a little bit performance. |
|
|
* |
|
|
* 2) Fallback to reading from memory the usual way. |
|
|
*/ |
|
|
if (cached_pc & 3) { |
|
|
mips_cpu_exception(cpu, EXCEPTION_ADEL, |
|
|
0, cached_pc, 0, 0, 0, 0); |
|
|
return 0; |
|
|
} |
|
|
if (cpu->cd.mips.pc_last_host_4k_page != NULL && |
|
|
(cached_pc & ~0xfff) == cpu->cd.mips.pc_last_virtual_page) { |
|
|
/* NOTE: This only works on the host if offset is |
|
|
aligned correctly! (TODO) */ |
|
|
*(uint32_t *)instr = *(uint32_t *) |
|
|
(cpu->cd.mips.pc_last_host_4k_page + (cached_pc & 0xffc)); |
|
|
#ifdef BINTRANS |
|
|
cpu->cd.mips.pc_bintrans_paddr_valid = 1; |
|
|
cpu->cd.mips.pc_bintrans_paddr = |
|
|
cpu->cd.mips.pc_last_physical_page | (cached_pc & 0xfff); |
|
|
cpu->cd.mips.pc_bintrans_host_4kpage = cpu->cd.mips.pc_last_host_4k_page; |
|
|
#endif |
|
|
} else { |
|
|
if (!cpu->memory_rw(cpu, cpu->mem, cached_pc, &instr[0], |
|
|
sizeof(instr), MEM_READ, CACHE_INSTRUCTION)) |
|
|
return 0; |
|
|
} |
|
|
|
|
|
#ifdef BINTRANS |
|
|
if (cpu->cd.mips.dont_run_next_bintrans) { |
|
|
cpu->cd.mips.dont_run_next_bintrans = 0; |
|
|
} else if (cpu->machine->bintrans_enable && |
|
|
cpu->cd.mips.pc_bintrans_paddr_valid) { |
|
|
int res; |
|
|
cpu->cd.mips.bintrans_instructions_executed = 0; |
|
|
|
|
|
res = bintrans_attempt_translate(cpu, |
|
|
cpu->cd.mips.pc_bintrans_paddr); |
|
|
|
|
|
if (res >= 0) { |
|
|
/* debug("BINTRANS translation + hit," |
|
|
" pc = %016llx\n", (long long)cached_pc); */ |
|
|
if (res > 0 || cpu->pc != cached_pc) { |
|
|
if (instruction_trace_cached) |
|
|
mips_cpu_disassemble_instr(cpu, instr, 1, 0, 1); |
|
|
if (res & BINTRANS_DONT_RUN_NEXT) |
|
|
cpu->cd.mips.dont_run_next_bintrans = 1; |
|
|
res &= BINTRANS_N_MASK; |
|
|
|
|
|
if (cpu->cd.mips.cpu_type.exc_model != EXC3K) { |
|
|
int x = cp0->reg[COP0_COUNT], y = cp0->reg[COP0_COMPARE]; |
|
|
int diff = x - y; |
|
|
if (diff < 0 && diff + (res-1) >= 0 |
|
|
&& cpu->cd.mips.compare_register_set) { |
|
|
mips_cpu_interrupt(cpu, 7); |
|
|
cpu->cd.mips.compare_register_set = 0; |
|
|
} |
|
|
|
|
|
cp0->reg[COP0_COUNT] = (int64_t) |
|
|
(int32_t)(cp0->reg[COP0_COUNT] + res-1); |
|
|
} |
|
|
|
|
|
return res; |
|
|
} |
|
|
} |
|
|
} |
|
|
#endif |
|
|
|
|
|
if (instruction_trace_cached) |
|
|
mips_cpu_disassemble_instr(cpu, instr, 1, 0, 0); |
|
|
|
|
|
/* Advance the program counter: */ |
|
|
cpu->pc += sizeof(instr); |
|
|
cached_pc = cpu->pc; |
|
|
|
|
|
/* |
|
|
* TODO: If Reverse-endian is set in the status cop0 register |
|
|
* and we are in usermode, then reverse endianness! |
|
|
*/ |
|
|
|
|
|
/* |
|
|
* The rest of the code is written for little endian, so |
|
|
* swap if necessary: |
|
|
*/ |
|
|
if (cpu->byte_order == EMUL_BIG_ENDIAN) { |
|
|
int tmp = instr[0]; instr[0] = instr[3]; instr[3] = tmp; |
|
|
tmp = instr[1]; instr[1] = instr[2]; instr[2] = tmp; |
|
|
} |
|
|
} |
|
|
|
|
|
|
|
|
/* |
|
|
* Nullify this instruction? (Set by a previous branch-likely |
|
|
* instruction.) |
|
|
* |
|
|
* Note: The return value is 1, even if no instruction was actually |
|
|
* executed. |
|
|
*/ |
|
|
if (cpu->cd.mips.nullify_next) { |
|
|
cpu->cd.mips.nullify_next = 0; |
|
|
return 1; |
|
|
} |
|
|
|
|
|
|
|
|
/* |
|
|
* Execute the instruction: |
|
|
*/ |
|
|
|
|
|
/* Get the top 6 bits of the instruction: */ |
|
|
hi6 = instr[3] >> 2; /* & 0x3f */ |
|
|
|
|
|
if (show_opcode_statistics) |
|
|
cpu->cd.mips.stats_opcode[hi6] ++; |
|
|
|
|
|
switch (hi6) { |
|
|
case HI6_SPECIAL: |
|
|
special6 = instr[0] & 0x3f; |
|
|
|
|
|
if (show_opcode_statistics) |
|
|
cpu->cd.mips.stats__special[special6] ++; |
|
|
|
|
|
switch (special6) { |
|
|
case SPECIAL_SLL: |
|
|
case SPECIAL_SRL: |
|
|
case SPECIAL_SRA: |
|
|
case SPECIAL_DSLL: |
|
|
case SPECIAL_DSRL: |
|
|
case SPECIAL_DSRA: |
|
|
case SPECIAL_DSLL32: |
|
|
case SPECIAL_DSRL32: |
|
|
case SPECIAL_DSRA32: |
|
|
rt = instr[2] & 31; |
|
|
rd = (instr[1] >> 3) & 31; |
|
|
sa = ((instr[1] & 7) << 2) + ((instr[0] >> 6) & 3); |
|
|
|
|
|
/* |
|
|
* Check for NOP: |
|
|
* |
|
|
* The R4000 manual says that a shift amount of zero |
|
|
* is treated as a nop by some assemblers. Checking |
|
|
* for sa == 0 here would not be correct, though, |
|
|
* because instructions such as sll r3,r4,0 are |
|
|
* possible, and are definitely not a nop. |
|
|
* Instead, check if the destination register is r0. |
|
|
* |
|
|
* TODO: ssnop should wait until the _next_ |
|
|
* cycle boundary, or something like that. The |
|
|
* code here is incorrect. |
|
|
*/ |
|
|
if (rd == 0 && special6 == SPECIAL_SLL) { |
|
|
if (sa == 1) { |
|
|
/* ssnop */ |
|
|
#ifdef ENABLE_INSTRUCTION_DELAYS |
|
|
cpu->cd.mips.instruction_delay += |
|
|
cpu->cd.mips.cpu_type. |
|
|
instrs_per_cycle - 1; |
|
|
#endif |
|
|
} |
|
|
return 1; |
|
|
} |
|
|
|
|
|
if (special6 == SPECIAL_SLL) { |
|
|
switch (sa) { |
|
|
case 8: cpu->cd.mips.gpr[rd] = cpu->cd.mips.gpr[rt] << 8; break; |
|
|
case 16:cpu->cd.mips.gpr[rd] = cpu->cd.mips.gpr[rt] << 16; break; |
|
|
default:cpu->cd.mips.gpr[rd] = cpu->cd.mips.gpr[rt] << sa; |
|
|
} |
|
|
/* Sign-extend rd: */ |
|
|
cpu->cd.mips.gpr[rd] = (int64_t) (int32_t) cpu->cd.mips.gpr[rd]; |
|
|
} |
|
|
if (special6 == SPECIAL_DSLL) { |
|
|
cpu->cd.mips.gpr[rd] = cpu->cd.mips.gpr[rt] << sa; |
|
|
} |
|
|
if (special6 == SPECIAL_DSRL) { |
|
|
cpu->cd.mips.gpr[rd] = cpu->cd.mips.gpr[rt] >> sa; |
|
|
} |
|
|
if (special6 == SPECIAL_DSLL32) { |
|
|
cpu->cd.mips.gpr[rd] = cpu->cd.mips.gpr[rt] << (sa + 32); |
|
|
} |
|
|
if (special6 == SPECIAL_SRL) { |
|
|
/* |
|
|
* Three cases: |
|
|
* shift amount = zero: just copy |
|
|
* high bit of rt zero: plain shift right (of all bits) |
|
|
* high bit of rt one: plain shift right (of lowest 32 bits) |
|
|
*/ |
|
|
if (sa == 0) |
|
|
cpu->cd.mips.gpr[rd] = cpu->cd.mips.gpr[rt]; |
|
|
else if (!(cpu->cd.mips.gpr[rt] & 0x80000000ULL)) { |
|
|
cpu->cd.mips.gpr[rd] = cpu->cd.mips.gpr[rt] >> sa; |
|
|
} else |
|
|
cpu->cd.mips.gpr[rd] = (cpu->cd.mips.gpr[rt] & 0xffffffffULL) >> sa; |
|
|
} |
|
|
if (special6 == SPECIAL_SRA) { |
|
|
int topbit = cpu->cd.mips.gpr[rt] & 0x80000000ULL; |
|
|
switch (sa) { |
|
|
case 8: cpu->cd.mips.gpr[rd] = cpu->cd.mips.gpr[rt] >> 8; break; |
|
|
case 16:cpu->cd.mips.gpr[rd] = cpu->cd.mips.gpr[rt] >> 16; break; |
|
|
default:cpu->cd.mips.gpr[rd] = cpu->cd.mips.gpr[rt] >> sa; |
|
|
} |
|
|
if (topbit) |
|
|
cpu->cd.mips.gpr[rd] |= 0xffffffff00000000ULL; |
|
|
} |
|
|
if (special6 == SPECIAL_DSRL32) { |
|
|
cpu->cd.mips.gpr[rd] = cpu->cd.mips.gpr[rt] >> (sa + 32); |
|
|
} |
|
|
if (special6 == SPECIAL_DSRA32 || special6 == SPECIAL_DSRA) { |
|
|
if (special6 == SPECIAL_DSRA32) |
|
|
sa += 32; |
|
|
cpu->cd.mips.gpr[rd] = cpu->cd.mips.gpr[rt]; |
|
|
while (sa > 0) { |
|
|
cpu->cd.mips.gpr[rd] = cpu->cd.mips.gpr[rd] >> 1; |
|
|
sa--; |
|
|
if (cpu->cd.mips.gpr[rd] & ((uint64_t)1 << 62)) /* old signbit */ |
|
|
cpu->cd.mips.gpr[rd] |= ((uint64_t)1 << 63); |
|
|
} |
|
|
} |
|
|
return 1; |
|
|
case SPECIAL_DSRLV: |
|
|
case SPECIAL_DSRAV: |
|
|
case SPECIAL_DSLLV: |
|
|
case SPECIAL_SLLV: |
|
|
case SPECIAL_SRAV: |
|
|
case SPECIAL_SRLV: |
|
|
rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7); |
|
|
rt = instr[2] & 31; |
|
|
rd = (instr[1] >> 3) & 31; |
|
|
|
|
|
if (special6 == SPECIAL_DSRLV) { |
|
|
sa = cpu->cd.mips.gpr[rs] & 63; |
|
|
cpu->cd.mips.gpr[rd] = cpu->cd.mips.gpr[rt] >> sa; |
|
|
} |
|
|
if (special6 == SPECIAL_DSRAV) { |
|
|
sa = cpu->cd.mips.gpr[rs] & 63; |
|
|
cpu->cd.mips.gpr[rd] = cpu->cd.mips.gpr[rt]; |
|
|
while (sa > 0) { |
|
|
cpu->cd.mips.gpr[rd] = cpu->cd.mips.gpr[rd] >> 1; |
|
|
sa--; |
|
|
if (cpu->cd.mips.gpr[rd] & ((uint64_t)1 << 62)) /* old sign-bit */ |
|
|
cpu->cd.mips.gpr[rd] |= ((uint64_t)1 << 63); |
|
|
} |
|
|
} |
|
|
if (special6 == SPECIAL_DSLLV) { |
|
|
sa = cpu->cd.mips.gpr[rs] & 63; |
|
|
cpu->cd.mips.gpr[rd] = cpu->cd.mips.gpr[rt]; |
|
|
cpu->cd.mips.gpr[rd] = cpu->cd.mips.gpr[rd] << sa; |
|
|
} |
|
|
if (special6 == SPECIAL_SLLV) { |
|
|
sa = cpu->cd.mips.gpr[rs] & 31; |
|
|
cpu->cd.mips.gpr[rd] = cpu->cd.mips.gpr[rt]; |
|
|
cpu->cd.mips.gpr[rd] = cpu->cd.mips.gpr[rd] << sa; |
|
|
/* Sign-extend rd: */ |
|
|
cpu->cd.mips.gpr[rd] &= 0xffffffffULL; |
|
|
if (cpu->cd.mips.gpr[rd] & 0x80000000ULL) |
|
|
cpu->cd.mips.gpr[rd] |= 0xffffffff00000000ULL; |
|
|
} |
|
|
if (special6 == SPECIAL_SRAV) { |
|
|
sa = cpu->cd.mips.gpr[rs] & 31; |
|
|
cpu->cd.mips.gpr[rd] = cpu->cd.mips.gpr[rt]; |
|
|
/* Sign-extend rd: */ |
|
|
cpu->cd.mips.gpr[rd] &= 0xffffffffULL; |
|
|
if (cpu->cd.mips.gpr[rd] & 0x80000000ULL) |
|
|
cpu->cd.mips.gpr[rd] |= 0xffffffff00000000ULL; |
|
|
while (sa > 0) { |
|
|
cpu->cd.mips.gpr[rd] = cpu->cd.mips.gpr[rd] >> 1; |
|
|
sa--; |
|
|
} |
|
|
if (cpu->cd.mips.gpr[rd] & 0x80000000ULL) |
|
|
cpu->cd.mips.gpr[rd] |= 0xffffffff00000000ULL; |
|
|
} |
|
|
if (special6 == SPECIAL_SRLV) { |
|
|
sa = cpu->cd.mips.gpr[rs] & 31; |
|
|
cpu->cd.mips.gpr[rd] = cpu->cd.mips.gpr[rt]; |
|
|
cpu->cd.mips.gpr[rd] &= 0xffffffffULL; |
|
|
cpu->cd.mips.gpr[rd] = cpu->cd.mips.gpr[rd] >> sa; |
|
|
/* And finally sign-extend rd: */ |
|
|
if (cpu->cd.mips.gpr[rd] & 0x80000000ULL) |
|
|
cpu->cd.mips.gpr[rd] |= 0xffffffff00000000ULL; |
|
|
} |
|
|
return 1; |
|
|
case SPECIAL_JR: |
|
|
if (cpu->cd.mips.delay_slot) { |
|
|
fatal("jr: jump inside a jump's delay slot, or similar. TODO\n"); |
|
|
cpu->running = 0; |
|
|
return 1; |
|
|
} |
|
|
|
|
|
rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7); |
|
|
|
|
|
cpu->cd.mips.delay_slot = TO_BE_DELAYED; |
|
|
cpu->cd.mips.delay_jmpaddr = cpu->cd.mips.gpr[rs]; |
|
|
|
|
|
if (cpu->machine->show_trace_tree && rs == 31) |
|
|
cpu_functioncall_trace_return(cpu); |
|
|
|
|
|
return 1; |
|
|
case SPECIAL_JALR: |
|
|
if (cpu->cd.mips.delay_slot) { |
|
|
fatal("jalr: jump inside a jump's delay slot, or similar. TODO\n"); |
|
|
cpu->running = 0; |
|
|
return 1; |
|
|
} |
|
|
|
|
|
rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7); |
|
|
rd = (instr[1] >> 3) & 31; |
|
|
|
|
|
tmpvalue = cpu->cd.mips.gpr[rs]; |
|
|
cpu->cd.mips.gpr[rd] = cached_pc + 4; |
|
|
/* already increased by 4 earlier */ |
|
|
|
|
|
if (cpu->machine->show_trace_tree && rd == 31) { |
|
|
cpu->cd.mips.show_trace_delay = 2; |
|
|
cpu->cd.mips.show_trace_addr = tmpvalue; |
|
|
} |
|
|
|
|
|
cpu->cd.mips.delay_slot = TO_BE_DELAYED; |
|
|
cpu->cd.mips.delay_jmpaddr = tmpvalue; |
|
|
return 1; |
|
|
case SPECIAL_MFHI: |
|
|
case SPECIAL_MFLO: |
|
|
rd = (instr[1] >> 3) & 31; |
|
|
|
|
|
if (special6 == SPECIAL_MFHI) { |
|
|
cpu->cd.mips.gpr[rd] = cpu->cd.mips.hi; |
|
|
#ifdef MFHILO_DELAY |
|
|
cpu->mfhi_delay = 3; |
|
|
#endif |
|
|
} |
|
|
if (special6 == SPECIAL_MFLO) { |
|
|
cpu->cd.mips.gpr[rd] = cpu->cd.mips.lo; |
|
|
#ifdef MFHILO_DELAY |
|
|
cpu->mflo_delay = 3; |
|
|
#endif |
|
|
} |
|
|
return 1; |
|
|
case SPECIAL_ADD: |
|
|
case SPECIAL_ADDU: |
|
|
case SPECIAL_SUB: |
|
|
case SPECIAL_SUBU: |
|
|
case SPECIAL_AND: |
|
|
case SPECIAL_OR: |
|
|
case SPECIAL_XOR: |
|
|
case SPECIAL_NOR: |
|
|
case SPECIAL_SLT: |
|
|
case SPECIAL_SLTU: |
|
|
case SPECIAL_MTLO: |
|
|
case SPECIAL_MTHI: |
|
|
case SPECIAL_MULT: |
|
|
case SPECIAL_MULTU: |
|
|
case SPECIAL_DMULT: |
|
|
case SPECIAL_DMULTU: |
|
|
case SPECIAL_DIV: |
|
|
case SPECIAL_DIVU: |
|
|
case SPECIAL_DDIV: |
|
|
case SPECIAL_DDIVU: |
|
|
case SPECIAL_TGE: |
|
|
case SPECIAL_TGEU: |
|
|
case SPECIAL_TLT: |
|
|
case SPECIAL_TLTU: |
|
|
case SPECIAL_TEQ: |
|
|
case SPECIAL_TNE: |
|
|
case SPECIAL_DADD: |
|
|
case SPECIAL_DADDU: |
|
|
case SPECIAL_DSUB: |
|
|
case SPECIAL_DSUBU: |
|
|
case SPECIAL_MOVZ: |
|
|
case SPECIAL_MOVN: |
|
|
rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7); |
|
|
rt = instr[2] & 31; |
|
|
rd = (instr[1] >> 3) & 31; |
|
|
|
|
|
#ifdef MFHILO_DELAY |
|
|
if (cpu->mflo_delay > 0 && ( |
|
|
special6 == SPECIAL_DDIV || special6 == SPECIAL_DDIVU || |
|
|
special6 == SPECIAL_DIV || special6 == SPECIAL_DIVU || |
|
|
special6 == SPECIAL_DMULT || special6 == SPECIAL_DMULTU || |
|
|
special6 == SPECIAL_MTLO || special6 == SPECIAL_MULT |
|
|
|| special6 == SPECIAL_MULTU |
|
|
) ) |
|
|
debug("warning: instruction modifying LO too early after mflo!\n"); |
|
|
|
|
|
if (cpu->mfhi_delay > 0 && ( |
|
|
special6 == SPECIAL_DDIV || special6 == SPECIAL_DDIVU || |
|
|
special6 == SPECIAL_DIV || special6 == SPECIAL_DIVU || |
|
|
special6 == SPECIAL_DMULT || special6 == SPECIAL_DMULTU || |
|
|
special6 == SPECIAL_MTHI || special6 == SPECIAL_MULT |
|
|
|| special6 == SPECIAL_MULTU |
|
|
) ) |
|
|
debug("warning: instruction modifying HI too early after mfhi!\n"); |
|
|
#endif |
|
|
|
|
|
if (special6 == SPECIAL_ADDU) { |
|
|
cpu->cd.mips.gpr[rd] = cpu->cd.mips.gpr[rs] + cpu->cd.mips.gpr[rt]; |
|
|
cpu->cd.mips.gpr[rd] &= 0xffffffffULL; |
|
|
if (cpu->cd.mips.gpr[rd] & 0x80000000ULL) |
|
|
cpu->cd.mips.gpr[rd] |= 0xffffffff00000000ULL; |
|
|
break; |
|
|
} |
|
|
if (special6 == SPECIAL_ADD) { |
|
|
/* According to the MIPS64 manual: */ |
|
|
uint64_t temp, temp1, temp2; |
|
|
temp1 = cpu->cd.mips.gpr[rs] + ((cpu->cd.mips.gpr[rs] & 0x80000000ULL) << 1); |
|
|
temp2 = cpu->cd.mips.gpr[rt] + ((cpu->cd.mips.gpr[rt] & 0x80000000ULL) << 1); |
|
|
temp = temp1 + temp2; |
|
|
#if 0 |
|
|
/* TODO: apparently this doesn't work (an example of |
|
|
something that breaks is NetBSD/sgimips' mips3_TBIA() */ |
|
|
/* If bits 32 and 31 of temp differ, then it's an overflow */ |
|
|
temp1 = temp & 0x100000000ULL; |
|
|
temp2 = temp & 0x80000000ULL; |
|
|
if ((temp1 && !temp2) || (!temp1 && temp2)) { |
|
|
mips_cpu_exception(cpu, EXCEPTION_OV, 0, 0, 0, 0, 0, 0); |
|
|
break; |
|
|
} |
|
|
#endif |
|
|
cpu->cd.mips.gpr[rd] = temp & 0xffffffffULL; |
|
|
if (cpu->cd.mips.gpr[rd] & 0x80000000ULL) |
|
|
cpu->cd.mips.gpr[rd] |= 0xffffffff00000000ULL; |
|
|
break; |
|
|
} |
|
|
if (special6 == SPECIAL_SUBU) { |
|
|
cpu->cd.mips.gpr[rd] = cpu->cd.mips.gpr[rs] - cpu->cd.mips.gpr[rt]; |
|
|
cpu->cd.mips.gpr[rd] &= 0xffffffffULL; |
|
|
if (cpu->cd.mips.gpr[rd] & 0x80000000ULL) |
|
|
cpu->cd.mips.gpr[rd] |= 0xffffffff00000000ULL; |
|
|
break; |
|
|
} |
|
|
if (special6 == SPECIAL_SUB) { |
|
|
/* According to the MIPS64 manual: */ |
|
|
uint64_t temp, temp1, temp2; |
|
|
temp1 = cpu->cd.mips.gpr[rs] + ((cpu->cd.mips.gpr[rs] & 0x80000000ULL) << 1); |
|
|
temp2 = cpu->cd.mips.gpr[rt] + ((cpu->cd.mips.gpr[rt] & 0x80000000ULL) << 1); |
|
|
temp = temp1 - temp2; |
|
|
#if 0 |
|
|
/* If bits 32 and 31 of temp differ, then it's an overflow */ |
|
|
temp1 = temp & 0x100000000ULL; |
|
|
temp2 = temp & 0x80000000ULL; |
|
|
if ((temp1 && !temp2) || (!temp1 && temp2)) { |
|
|
mips_cpu_exception(cpu, EXCEPTION_OV, 0, 0, 0, 0, 0, 0); |
|
|
break; |
|
|
} |
|
|
#endif |
|
|
cpu->cd.mips.gpr[rd] = temp & 0xffffffffULL; |
|
|
if (cpu->cd.mips.gpr[rd] & 0x80000000ULL) |
|
|
cpu->cd.mips.gpr[rd] |= 0xffffffff00000000ULL; |
|
|
break; |
|
|
} |
|
|
|
|
|
if (special6 == SPECIAL_AND) { |
|
|
cpu->cd.mips.gpr[rd] = cpu->cd.mips.gpr[rs] & cpu->cd.mips.gpr[rt]; |
|
|
break; |
|
|
} |
|
|
if (special6 == SPECIAL_OR) { |
|
|
cpu->cd.mips.gpr[rd] = cpu->cd.mips.gpr[rs] | cpu->cd.mips.gpr[rt]; |
|
|
break; |
|
|
} |
|
|
if (special6 == SPECIAL_XOR) { |
|
|
cpu->cd.mips.gpr[rd] = cpu->cd.mips.gpr[rs] ^ cpu->cd.mips.gpr[rt]; |
|
|
break; |
|
|
} |
|
|
if (special6 == SPECIAL_NOR) { |
|
|
cpu->cd.mips.gpr[rd] = ~(cpu->cd.mips.gpr[rs] | cpu->cd.mips.gpr[rt]); |
|
|
break; |
|
|
} |
|
|
if (special6 == SPECIAL_SLT) { |
|
|
cpu->cd.mips.gpr[rd] = (int64_t)cpu->cd.mips.gpr[rs] < (int64_t)cpu->cd.mips.gpr[rt]; |
|
|
break; |
|
|
} |
|
|
if (special6 == SPECIAL_SLTU) { |
|
|
cpu->cd.mips.gpr[rd] = cpu->cd.mips.gpr[rs] < cpu->cd.mips.gpr[rt]; |
|
|
break; |
|
|
} |
|
|
if (special6 == SPECIAL_MTLO) { |
|
|
cpu->cd.mips.lo = cpu->cd.mips.gpr[rs]; |
|
|
break; |
|
|
} |
|
|
if (special6 == SPECIAL_MTHI) { |
|
|
cpu->cd.mips.hi = cpu->cd.mips.gpr[rs]; |
|
|
break; |
|
|
} |
|
|
if (special6 == SPECIAL_MULT) { |
|
|
int64_t f1, f2, sum; |
|
|
f1 = cpu->cd.mips.gpr[rs] & 0xffffffffULL; |
|
|
/* sign extend f1 */ |
|
|
if (f1 & 0x80000000ULL) |
|
|
f1 |= 0xffffffff00000000ULL; |
|
|
f2 = cpu->cd.mips.gpr[rt] & 0xffffffffULL; |
|
|
/* sign extend f2 */ |
|
|
if (f2 & 0x80000000ULL) |
|
|
f2 |= 0xffffffff00000000ULL; |
|
|
sum = f1 * f2; |
|
|
|
|
|
cpu->cd.mips.lo = sum & 0xffffffffULL; |
|
|
cpu->cd.mips.hi = ((uint64_t)sum >> 32) & 0xffffffffULL; |
|
|
|
|
|
/* sign-extend: */ |
|
|
if (cpu->cd.mips.lo & 0x80000000ULL) |
|
|
cpu->cd.mips.lo |= 0xffffffff00000000ULL; |
|
|
if (cpu->cd.mips.hi & 0x80000000ULL) |
|
|
cpu->cd.mips.hi |= 0xffffffff00000000ULL; |
|
|
|
|
|
/* |
|
|
* NOTE: The stuff about rd!=0 is just a |
|
|
* guess, judging from how some NetBSD code |
|
|
* seems to execute. It is not documented in |
|
|
* the MIPS64 ISA docs :-/ |
|
|
*/ |
|
|
|
|
|
if (rd != 0) { |
|
|
if (cpu->cd.mips.cpu_type.rev != MIPS_R5900) |
|
|
debug("WARNING! mult_xx is an undocumented instruction!"); |
|
|
cpu->cd.mips.gpr[rd] = cpu->cd.mips.lo; |
|
|
} |
|
|
break; |
|
|
} |
|
|
if (special6 == SPECIAL_MULTU) { |
|
|
uint64_t f1, f2, sum; |
|
|
/* zero extend f1 and f2 */ |
|
|
f1 = cpu->cd.mips.gpr[rs] & 0xffffffffULL; |
|
|
f2 = cpu->cd.mips.gpr[rt] & 0xffffffffULL; |
|
|
sum = f1 * f2; |
|
|
cpu->cd.mips.lo = sum & 0xffffffffULL; |
|
|
cpu->cd.mips.hi = (sum >> 32) & 0xffffffffULL; |
|
|
|
|
|
/* sign-extend: */ |
|
|
if (cpu->cd.mips.lo & 0x80000000ULL) |
|
|
cpu->cd.mips.lo |= 0xffffffff00000000ULL; |
|
|
if (cpu->cd.mips.hi & 0x80000000ULL) |
|
|
cpu->cd.mips.hi |= 0xffffffff00000000ULL; |
|
|
break; |
|
|
} |
|
|
if (special6 == SPECIAL_DMULT) { |
|
|
/* 64x64 = 128 bit multiplication, signed. */ |
|
|
uint64_t s1 = cpu->cd.mips.gpr[rt]; |
|
|
uint64_t s2 = cpu->cd.mips.gpr[rs]; |
|
|
int n_negative = 0; |
|
|
int i; |
|
|
|
|
|
if ((int64_t)s1 < 0) { |
|
|
s1 = -(int64_t)s1; |
|
|
n_negative ++; |
|
|
} |
|
|
if ((int64_t)s2 < 0) { |
|
|
s2 = -(int64_t)s2; |
|
|
n_negative ++; |
|
|
} |
|
|
|
|
|
cpu->cd.mips.lo = cpu->cd.mips.hi = 0; |
|
|
|
|
|
for (i=0; i<64; i++) { |
|
|
int bit = (s1 & 0x8000000000000000ULL)? 1 : 0; |
|
|
s1 <<= 1; |
|
|
/* If bit in s1 set, then add s2 to hi/lo: */ |
|
|
if (bit) { |
|
|
uint64_t old_lo = cpu->cd.mips.lo; |
|
|
cpu->cd.mips.lo += s2; |
|
|
if (cpu->cd.mips.lo < old_lo) |
|
|
cpu->cd.mips.hi ++; |
|
|
} |
|
|
if (i != 63) { |
|
|
cpu->cd.mips.hi <<= 1; |
|
|
cpu->cd.mips.hi += |
|
|
(cpu->cd.mips.lo & 0x8000000000000000ULL) ? 1 : 0; |
|
|
cpu->cd.mips.lo <<= 1; |
|
|
} |
|
|
} |
|
|
|
|
|
if (n_negative == 1) { |
|
|
cpu->cd.mips.hi = -(int64_t)cpu->cd.mips.hi; |
|
|
cpu->cd.mips.lo = -(int64_t)cpu->cd.mips.lo; |
|
|
if ((int64_t)cpu->cd.mips.lo < 0) |
|
|
cpu->cd.mips.hi --; |
|
|
} |
|
|
break; |
|
|
} |
|
|
if (special6 == SPECIAL_DMULTU) { |
|
|
/* 64x64 = 128 bit multiplication, unsigned. */ |
|
|
uint64_t s1 = cpu->cd.mips.gpr[rt]; |
|
|
uint64_t s2 = cpu->cd.mips.gpr[rs]; |
|
|
int i; |
|
|
|
|
|
cpu->cd.mips.lo = cpu->cd.mips.hi = 0; |
|
|
|
|
|
for (i=0; i<64; i++) { |
|
|
int bit = (s1 & 0x8000000000000000ULL)? 1 : 0; |
|
|
s1 <<= 1; |
|
|
/* If bit in s1 set, then add s2 to hi/lo: */ |
|
|
if (bit) { |
|
|
uint64_t old_lo = cpu->cd.mips.lo; |
|
|
cpu->cd.mips.lo += s2; |
|
|
if (cpu->cd.mips.lo < old_lo) |
|
|
cpu->cd.mips.hi ++; |
|
|
} |
|
|
if (i != 63) { |
|
|
cpu->cd.mips.hi <<= 1; |
|
|
cpu->cd.mips.hi += |
|
|
(cpu->cd.mips.lo & 0x8000000000000000ULL) ? 1 : 0; |
|
|
cpu->cd.mips.lo <<= 1; |
|
|
} |
|
|
} |
|
|
break; |
|
|
} |
|
|
if (special6 == SPECIAL_DIV) { |
|
|
int64_t a, b; |
|
|
/* Signextend rs and rt: */ |
|
|
a = cpu->cd.mips.gpr[rs] & 0xffffffffULL; |
|
|
if (a & 0x80000000ULL) |
|
|
a |= 0xffffffff00000000ULL; |
|
|
b = cpu->cd.mips.gpr[rt] & 0xffffffffULL; |
|
|
if (b & 0x80000000ULL) |
|
|
b |= 0xffffffff00000000ULL; |
|
|
|
|
|
if (b == 0) { |
|
|
/* undefined */ |
|
|
cpu->cd.mips.lo = cpu->cd.mips.hi = 0; |
|
|
} else { |
|
|
cpu->cd.mips.lo = a / b; |
|
|
cpu->cd.mips.hi = a % b; |
|
|
} |
|
|
/* Sign-extend lo and hi: */ |
|
|
cpu->cd.mips.lo &= 0xffffffffULL; |
|
|
if (cpu->cd.mips.lo & 0x80000000ULL) |
|
|
cpu->cd.mips.lo |= 0xffffffff00000000ULL; |
|
|
cpu->cd.mips.hi &= 0xffffffffULL; |
|
|
if (cpu->cd.mips.hi & 0x80000000ULL) |
|
|
cpu->cd.mips.hi |= 0xffffffff00000000ULL; |
|
|
break; |
|
|
} |
|
|
if (special6 == SPECIAL_DIVU) { |
|
|
int64_t a, b; |
|
|
/* Zero-extend rs and rt: */ |
|
|
a = cpu->cd.mips.gpr[rs] & 0xffffffffULL; |
|
|
b = cpu->cd.mips.gpr[rt] & 0xffffffffULL; |
|
|
if (b == 0) { |
|
|
/* undefined */ |
|
|
cpu->cd.mips.lo = cpu->cd.mips.hi = 0; |
|
|
} else { |
|
|
cpu->cd.mips.lo = a / b; |
|
|
cpu->cd.mips.hi = a % b; |
|
|
} |
|
|
/* Sign-extend lo and hi: */ |
|
|
cpu->cd.mips.lo &= 0xffffffffULL; |
|
|
if (cpu->cd.mips.lo & 0x80000000ULL) |
|
|
cpu->cd.mips.lo |= 0xffffffff00000000ULL; |
|
|
cpu->cd.mips.hi &= 0xffffffffULL; |
|
|
if (cpu->cd.mips.hi & 0x80000000ULL) |
|
|
cpu->cd.mips.hi |= 0xffffffff00000000ULL; |
|
|
break; |
|
|
} |
|
|
if (special6 == SPECIAL_DDIV) { |
|
|
if (cpu->cd.mips.gpr[rt] == 0) { |
|
|
cpu->cd.mips.lo = cpu->cd.mips.hi = 0; /* undefined */ |
|
|
} else { |
|
|
cpu->cd.mips.lo = (int64_t)cpu->cd.mips.gpr[rs] / (int64_t)cpu->cd.mips.gpr[rt]; |
|
|
cpu->cd.mips.hi = (int64_t)cpu->cd.mips.gpr[rs] % (int64_t)cpu->cd.mips.gpr[rt]; |
|
|
} |
|
|
break; |
|
|
} |
|
|
if (special6 == SPECIAL_DDIVU) { |
|
|
if (cpu->cd.mips.gpr[rt] == 0) { |
|
|
cpu->cd.mips.lo = cpu->cd.mips.hi = 0; /* undefined */ |
|
|
} else { |
|
|
cpu->cd.mips.lo = cpu->cd.mips.gpr[rs] / cpu->cd.mips.gpr[rt]; |
|
|
cpu->cd.mips.hi = cpu->cd.mips.gpr[rs] % cpu->cd.mips.gpr[rt]; |
|
|
} |
|
|
break; |
|
|
} |
|
|
if (special6 == SPECIAL_TGE) { |
|
|
if ((int64_t)cpu->cd.mips.gpr[rs] >= (int64_t)cpu->cd.mips.gpr[rt]) |
|
|
mips_cpu_exception(cpu, EXCEPTION_TR, 0, 0, 0, 0, 0, 0); |
|
|
break; |
|
|
} |
|
|
if (special6 == SPECIAL_TGEU) { |
|
|
if (cpu->cd.mips.gpr[rs] >= cpu->cd.mips.gpr[rt]) |
|
|
mips_cpu_exception(cpu, EXCEPTION_TR, 0, 0, 0, 0, 0, 0); |
|
|
break; |
|
|
} |
|
|
if (special6 == SPECIAL_TLT) { |
|
|
if ((int64_t)cpu->cd.mips.gpr[rs] < (int64_t)cpu->cd.mips.gpr[rt]) |
|
|
mips_cpu_exception(cpu, EXCEPTION_TR, 0, 0, 0, 0, 0, 0); |
|
|
break; |
|
|
} |
|
|
if (special6 == SPECIAL_TLTU) { |
|
|
if (cpu->cd.mips.gpr[rs] < cpu->cd.mips.gpr[rt]) |
|
|
mips_cpu_exception(cpu, EXCEPTION_TR, 0, 0, 0, 0, 0, 0); |
|
|
break; |
|
|
} |
|
|
if (special6 == SPECIAL_TEQ) { |
|
|
if (cpu->cd.mips.gpr[rs] == cpu->cd.mips.gpr[rt]) |
|
|
mips_cpu_exception(cpu, EXCEPTION_TR, 0, 0, 0, 0, 0, 0); |
|
|
break; |
|
|
} |
|
|
if (special6 == SPECIAL_TNE) { |
|
|
if (cpu->cd.mips.gpr[rs] != cpu->cd.mips.gpr[rt]) |
|
|
mips_cpu_exception(cpu, EXCEPTION_TR, 0, 0, 0, 0, 0, 0); |
|
|
break; |
|
|
} |
|
|
if (special6 == SPECIAL_DADD) { |
|
|
cpu->cd.mips.gpr[rd] = cpu->cd.mips.gpr[rs] + cpu->cd.mips.gpr[rt]; |
|
|
/* TODO: exception on overflow */ |
|
|
break; |
|
|
} |
|
|
if (special6 == SPECIAL_DADDU) { |
|
|
cpu->cd.mips.gpr[rd] = cpu->cd.mips.gpr[rs] + cpu->cd.mips.gpr[rt]; |
|
|
break; |
|
|
} |
|
|
if (special6 == SPECIAL_DSUB) { |
|
|
cpu->cd.mips.gpr[rd] = cpu->cd.mips.gpr[rs] - cpu->cd.mips.gpr[rt]; |
|
|
/* TODO: exception on overflow */ |
|
|
break; |
|
|
} |
|
|
if (special6 == SPECIAL_DSUBU) { |
|
|
cpu->cd.mips.gpr[rd] = cpu->cd.mips.gpr[rs] - cpu->cd.mips.gpr[rt]; |
|
|
break; |
|
|
} |
|
|
if (special6 == SPECIAL_MOVZ) { |
|
|
if (cpu->cd.mips.gpr[rt] == 0) |
|
|
cpu->cd.mips.gpr[rd] = cpu->cd.mips.gpr[rs]; |
|
|
break; |
|
|
} |
|
|
if (special6 == SPECIAL_MOVN) { |
|
|
if (cpu->cd.mips.gpr[rt] != 0) |
|
|
cpu->cd.mips.gpr[rd] = cpu->cd.mips.gpr[rs]; |
|
|
return 1; |
|
|
} |
|
|
return 1; |
|
|
case SPECIAL_SYNC: |
|
|
/* imm = ((instr[1] & 7) << 2) + (instr[0] >> 6); */ |
|
|
/* TODO: actually sync */ |
|
|
|
|
|
/* Clear the LLbit (at least on R10000): */ |
|
|
cpu->cd.mips.rmw = 0; |
|
|
return 1; |
|
|
case SPECIAL_SYSCALL: |
|
|
imm = ((instr[3] << 24) + (instr[2] << 16) + |
|
|
(instr[1] << 8) + instr[0]) >> 6; |
|
|
imm &= 0xfffff; |
|
|
|
|
|
if (cpu->machine->userland_emul != NULL) |
|
|
useremul_syscall(cpu, imm); |
|
|
else |
|
|
mips_cpu_exception(cpu, EXCEPTION_SYS, |
|
|
0, 0, 0, 0, 0, 0); |
|
|
return 1; |
|
|
case SPECIAL_BREAK: |
|
|
mips_cpu_exception(cpu, EXCEPTION_BP, 0, 0, 0, 0, 0, 0); |
|
|
return 1; |
|
|
case SPECIAL_MFSA: |
|
|
/* R5900? Move from shift amount register? */ |
|
|
/* rd = (instr[1] >> 3) & 31; */ |
|
|
/* TODO */ |
|
|
return 1; |
|
|
case SPECIAL_MTSA: |
|
|
/* R5900? Move to shift amount register? */ |
|
|
/* rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7); */ |
|
|
/* TODO */ |
|
|
return 1; |
|
|
default: |
|
|
if (!instruction_trace_cached) { |
|
|
fatal("cpu%i @ %016llx: %02x%02x%02x%02x%s\t", |
|
|
cpu->cpu_id, (long long)cpu->cd.mips.pc_last, |
|
|
instr[3], instr[2], instr[1], instr[0], cpu_flags(cpu)); |
|
|
} |
|
|
fatal("unimplemented special6 = 0x%02x\n", special6); |
|
|
cpu->running = 0; |
|
|
return 1; |
|
|
} |
|
|
return 1; |
|
|
case HI6_BEQ: |
|
|
case HI6_BEQL: |
|
|
case HI6_BNE: |
|
|
case HI6_BGTZ: |
|
|
case HI6_BGTZL: |
|
|
case HI6_BLEZ: |
|
|
case HI6_BLEZL: |
|
|
case HI6_BNEL: |
|
|
case HI6_ADDI: |
|
|
case HI6_ADDIU: |
|
|
case HI6_DADDI: |
|
|
case HI6_DADDIU: |
|
|
case HI6_SLTI: |
|
|
case HI6_SLTIU: |
|
|
case HI6_ANDI: |
|
|
case HI6_ORI: |
|
|
case HI6_XORI: |
|
|
case HI6_LUI: |
|
|
case HI6_LB: |
|
|
case HI6_LBU: |
|
|
case HI6_LH: |
|
|
case HI6_LHU: |
|
|
case HI6_LW: |
|
|
case HI6_LWU: |
|
|
case HI6_LD: |
|
|
case HI6_LQ_MDMX: |
|
|
case HI6_LWC1: |
|
|
case HI6_LWC2: |
|
|
case HI6_LWC3: |
|
|
case HI6_LDC1: |
|
|
case HI6_LDC2: |
|
|
case HI6_LL: |
|
|
case HI6_LLD: |
|
|
case HI6_SB: |
|
|
case HI6_SH: |
|
|
case HI6_SW: |
|
|
case HI6_SD: |
|
|
case HI6_SQ: |
|
|
case HI6_SC: |
|
|
case HI6_SCD: |
|
|
case HI6_SWC1: |
|
|
case HI6_SWC2: |
|
|
case HI6_SWC3: |
|
|
case HI6_SDC1: |
|
|
case HI6_SDC2: |
|
|
case HI6_LWL: /* Unaligned load/store */ |
|
|
case HI6_LWR: |
|
|
case HI6_LDL: |
|
|
case HI6_LDR: |
|
|
case HI6_SWL: |
|
|
case HI6_SWR: |
|
|
case HI6_SDL: |
|
|
case HI6_SDR: |
|
|
rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7); |
|
|
rt = instr[2] & 31; |
|
|
imm = (instr[1] << 8) + instr[0]; |
|
|
if (imm >= 32768) /* signed 16-bit */ |
|
|
imm -= 65536; |
|
|
|
|
|
tmpvalue = imm; /* used later in several cases */ |
|
|
|
|
|
switch (hi6) { |
|
|
case HI6_ADDI: |
|
|
case HI6_ADDIU: |
|
|
case HI6_DADDI: |
|
|
case HI6_DADDIU: |
|
|
tmpvalue = cpu->cd.mips.gpr[rs]; |
|
|
result_value = cpu->cd.mips.gpr[rs] + imm; |
|
|
|
|
|
if (hi6 == HI6_ADDI || hi6 == HI6_DADDI) { |
|
|
/* |
|
|
* addi and daddi should trap on overflow: |
|
|
* |
|
|
* TODO: This is incorrect? The R4000 manual |
|
|
* says that overflow occurs if the carry bits |
|
|
* out of bit 62 and 63 differ. The |
|
|
* destination register should not be modified |
|
|
* on overflow. |
|
|
*/ |
|
|
if (imm >= 0) { |
|
|
/* Turn around from 0x7fff.. to 0x800 ? Then overflow. */ |
|
|
if ( ((hi6 == HI6_ADDI && (result_value & |
|
|
0x80000000ULL) && (tmpvalue & |
|
|
0x80000000ULL)==0)) |
|
|
|| ((hi6 == HI6_DADDI && (result_value & |
|
|
0x8000000000000000ULL) && (tmpvalue & |
|
|
0x8000000000000000ULL)==0)) ) { |
|
|
mips_cpu_exception(cpu, EXCEPTION_OV, 0, 0, 0, 0, 0, 0); |
|
|
break; |
|
|
} |
|
|
} else { |
|
|
/* Turn around from 0x8000.. to 0x7fff.. ? Then overflow. */ |
|
|
if ( ((hi6 == HI6_ADDI && (result_value & |
|
|
0x80000000ULL)==0 && (tmpvalue & |
|
|
0x80000000ULL))) |
|
|
|| ((hi6 == HI6_DADDI && (result_value & |
|
|
0x8000000000000000ULL)==0 && (tmpvalue & |
|
|
0x8000000000000000ULL))) ) { |
|
|
mips_cpu_exception(cpu, EXCEPTION_OV, 0, 0, 0, 0, 0, 0); |
|
|
break; |
|
|
} |
|
|
} |
|
|
} |
|
|
|
|
|
cpu->cd.mips.gpr[rt] = result_value; |
|
|
|
|
|
/* |
|
|
* Super-ugly speed-hack: (only if speed_tricks != 0) |
|
|
* NOTE: This makes the emulation less correct. |
|
|
* |
|
|
* If we encounter a loop such as: |
|
|
* |
|
|
* 8012f5f4: 1c40ffff bgtz r0,r2,ffffffff8012f5f4 |
|
|
* 8012f5f8: 2442ffff (d) addiu r2,r2,-1 |
|
|
* |
|
|
* then it is a small loop which simply waits for r2 |
|
|
* to become zero. |
|
|
* |
|
|
* TODO: increaste the count register, and cause |
|
|
* interrupts!!! For now: return as if we just |
|
|
* executed 1 instruction. |
|
|
*/ |
|
|
ninstrs_executed = 1; |
|
|
if (cpu->machine->speed_tricks && cpu->cd.mips.delay_slot && |
|
|
cpu->cd.mips.last_was_jumptoself && |
|
|
cpu->cd.mips.jump_to_self_reg == rt && |
|
|
cpu->cd.mips.jump_to_self_reg == rs) { |
|
|
if ((int64_t)cpu->cd.mips.gpr[rt] > 1 && (int64_t)cpu->cd.mips.gpr[rt] < 0x70000000 |
|
|
&& (imm >= -30000 && imm <= -1)) { |
|
|
if (instruction_trace_cached) |
|
|
debug("changing r%i from %016llx to", rt, (long long)cpu->cd.mips.gpr[rt]); |
|
|
|
|
|
while ((int64_t)cpu->cd.mips.gpr[rt] > 0 && ninstrs_executed < 1000 |
|
|
&& ((int64_t)cpu->cd.mips.gpr[rt] + (int64_t)imm) > 0) { |
|
|
cpu->cd.mips.gpr[rt] += (int64_t)imm; |
|
|
ninstrs_executed += 2; |
|
|
} |
|
|
|
|
|
if (instruction_trace_cached) |
|
|
debug(" %016llx\n", (long long)cpu->cd.mips.gpr[rt]); |
|
|
|
|
|
/* TODO: return value, cpu->cd.mips.gpr[rt] * 2; */ |
|
|
} |
|
|
if ((int64_t)cpu->cd.mips.gpr[rt] > -0x70000000 && (int64_t)cpu->cd.mips.gpr[rt] < -1 |
|
|
&& (imm >= 1 && imm <= 30000)) { |
|
|
if (instruction_trace_cached) |
|
|
debug("changing r%i from %016llx to", rt, (long long)cpu->cd.mips.gpr[rt]); |
|
|
|
|
|
while ((int64_t)cpu->cd.mips.gpr[rt] < 0 && ninstrs_executed < 1000 |
|
|
&& ((int64_t)cpu->cd.mips.gpr[rt] + (int64_t)imm) < 0) { |
|
|
cpu->cd.mips.gpr[rt] += (int64_t)imm; |
|
|
ninstrs_executed += 2; |
|
|
} |
|
|
|
|
|
if (instruction_trace_cached) |
|
|
debug(" %016llx\n", (long long)cpu->cd.mips.gpr[rt]); |
|
|
} |
|
|
} |
|
|
|
|
|
if (hi6 == HI6_ADDI || hi6 == HI6_ADDIU) { |
|
|
/* Sign-extend: */ |
|
|
cpu->cd.mips.gpr[rt] &= 0xffffffffULL; |
|
|
if (cpu->cd.mips.gpr[rt] & 0x80000000ULL) |
|
|
cpu->cd.mips.gpr[rt] |= 0xffffffff00000000ULL; |
|
|
} |
|
|
return ninstrs_executed; |
|
|
case HI6_BEQ: |
|
|
case HI6_BNE: |
|
|
case HI6_BGTZ: |
|
|
case HI6_BGTZL: |
|
|
case HI6_BLEZ: |
|
|
case HI6_BLEZL: |
|
|
case HI6_BEQL: |
|
|
case HI6_BNEL: |
|
|
if (cpu->cd.mips.delay_slot) { |
|
|
fatal("b*: jump inside a jump's delay slot, or similar. TODO\n"); |
|
|
cpu->running = 0; |
|
|
return 1; |
|
|
} |
|
|
likely = cond = 0; |
|
|
switch (hi6) { |
|
|
case HI6_BNEL: likely = 1; |
|
|
case HI6_BNE: cond = (cpu->cd.mips.gpr[rt] != cpu->cd.mips.gpr[rs]); |
|
|
break; |
|
|
case HI6_BEQL: likely = 1; |
|
|
case HI6_BEQ: cond = (cpu->cd.mips.gpr[rt] == cpu->cd.mips.gpr[rs]); |
|
|
break; |
|
|
case HI6_BLEZL: likely = 1; |
|
|
case HI6_BLEZ: cond = ((int64_t)cpu->cd.mips.gpr[rs] <= 0); |
|
|
break; |
|
|
case HI6_BGTZL: likely = 1; |
|
|
case HI6_BGTZ: cond = ((int64_t)cpu->cd.mips.gpr[rs] > 0); |
|
|
break; |
|
|
} |
|
|
|
|
|
if (cond) { |
|
|
cpu->cd.mips.delay_slot = TO_BE_DELAYED; |
|
|
cpu->cd.mips.delay_jmpaddr = cached_pc + (imm << 2); |
|
|
} else { |
|
|
if (likely) |
|
|
cpu->cd.mips.nullify_next = 1; /* nullify delay slot */ |
|
|
} |
|
|
|
|
|
if (imm==-1 && (hi6 == HI6_BGTZ || hi6 == HI6_BLEZ || |
|
|
(hi6 == HI6_BGTZL && cond) || |
|
|
(hi6 == HI6_BLEZL && cond) || |
|
|
(hi6 == HI6_BNE && (rt==0 || rs==0)) || |
|
|
(hi6 == HI6_BEQ && (rt==0 || rs==0)))) { |
|
|
cpu->cd.mips.last_was_jumptoself = 2; |
|
|
if (rs == 0) |
|
|
cpu->cd.mips.jump_to_self_reg = rt; |
|
|
else |
|
|
cpu->cd.mips.jump_to_self_reg = rs; |
|
|
} |
|
|
return 1; |
|
|
case HI6_LUI: |
|
|
cpu->cd.mips.gpr[rt] = (imm << 16); |
|
|
/* No sign-extending necessary, as imm already |
|
|
was sign-extended if it was negative. */ |
|
|
break; |
|
|
case HI6_SLTI: |
|
|
cpu->cd.mips.gpr[rt] = (int64_t)cpu->cd.mips.gpr[rs] < (int64_t)tmpvalue; |
|
|
break; |
|
|
case HI6_SLTIU: |
|
|
cpu->cd.mips.gpr[rt] = cpu->cd.mips.gpr[rs] < (uint64_t)imm; |
|
|
break; |
|
|
case HI6_ANDI: |
|
|
cpu->cd.mips.gpr[rt] = cpu->cd.mips.gpr[rs] & (tmpvalue & 0xffff); |
|
|
break; |
|
|
case HI6_ORI: |
|
|
cpu->cd.mips.gpr[rt] = cpu->cd.mips.gpr[rs] | (tmpvalue & 0xffff); |
|
|
break; |
|
|
case HI6_XORI: |
|
|
cpu->cd.mips.gpr[rt] = cpu->cd.mips.gpr[rs] ^ (tmpvalue & 0xffff); |
|
|
break; |
|
|
case HI6_LB: |
|
|
case HI6_LBU: |
|
|
case HI6_LH: |
|
|
case HI6_LHU: |
|
|
case HI6_LW: |
|
|
case HI6_LWU: |
|
|
case HI6_LD: |
|
|
case HI6_LQ_MDMX: |
|
|
case HI6_LWC1: |
|
|
case HI6_LWC2: |
|
|
case HI6_LWC3: /* pref */ |
|
|
case HI6_LDC1: |
|
|
case HI6_LDC2: |
|
|
case HI6_LL: |
|
|
case HI6_LLD: |
|
|
case HI6_SB: |
|
|
case HI6_SH: |
|
|
case HI6_SW: |
|
|
case HI6_SD: |
|
|
case HI6_SQ: |
|
|
case HI6_SC: |
|
|
case HI6_SCD: |
|
|
case HI6_SWC1: |
|
|
case HI6_SWC2: |
|
|
case HI6_SWC3: |
|
|
case HI6_SDC1: |
|
|
case HI6_SDC2: |
|
|
/* These are the default "assumptions". */ |
|
|
linked = 0; |
|
|
st = 1; |
|
|
signd = 1; |
|
|
wlen = 4; |
|
|
|
|
|
switch (hi6) { |
|
|
/* The most common ones: */ |
|
|
case HI6_LW: { st = 0; } break; |
|
|
case HI6_SW: { signd = 0; } break; |
|
|
|
|
|
case HI6_LB: { wlen = 1; st = 0; } break; |
|
|
case HI6_LBU: { wlen = 1; st = 0; signd = 0; } break; |
|
|
case HI6_SB: { wlen = 1; signd = 0; } break; |
|
|
|
|
|
case HI6_LD: { wlen = 8; st = 0; signd = 0; } break; |
|
|
case HI6_SD: { wlen = 8; signd = 0; } break; |
|
|
|
|
|
case HI6_LQ_MDMX: { wlen = 16; st = 0; signd = 0; } break; /* R5900, otherwise MDMX (TODO) */ |
|
|
case HI6_SQ: { wlen = 16; signd = 0; } break; /* R5900 ? */ |
|
|
|
|
|
/* The rest: */ |
|
|
case HI6_LH: { wlen = 2; st = 0; } break; |
|
|
case HI6_LHU: { wlen = 2; st = 0; signd = 0; } break; |
|
|
case HI6_LWU: { st = 0; signd = 0; } break; |
|
|
case HI6_LWC1: { st = 0; } break; |
|
|
case HI6_LWC2: { st = 0; } break; |
|
|
case HI6_LWC3: { st = 0; } break; |
|
|
case HI6_LDC1: { wlen = 8; st = 0; signd = 0; } break; |
|
|
case HI6_LDC2: { wlen = 8; st = 0; signd = 0; } break; |
|
|
|
|
|
case HI6_SH: { wlen = 2; signd = 0; } break; |
|
|
case HI6_SDC1: |
|
|
case HI6_SDC2: wlen = 8; |
|
|
case HI6_SWC1: |
|
|
case HI6_SWC2: |
|
|
case HI6_SWC3: { signd = 0; } break; |
|
|
|
|
|
case HI6_LL: { st = 0; signd = 1; linked = 1; } break; |
|
|
case HI6_LLD: { wlen = 8; st = 0; signd = 0; linked = 1; } break; |
|
|
|
|
|
case HI6_SC: { signd = 1; linked = 1; } break; |
|
|
case HI6_SCD: { wlen = 8; signd = 0; linked = 1; } break; |
|
|
|
|
|
default: |
|
|
fatal("cannot be here\n"); |
|
|
wlen = 4; st = 0; signd = 0; |
|
|
} |
|
|
|
|
|
/* |
|
|
* In the MIPS IV ISA, the 'lwc3' instruction is changed into 'pref'. |
|
|
* The pref instruction is emulated by not doing anything. :-) TODO |
|
|
*/ |
|
|
if (hi6 == HI6_LWC3 && cpu->cd.mips.cpu_type.isa_level >= 4) { |
|
|
/* Clear the LLbit (at least on R10000): */ |
|
|
cpu->cd.mips.rmw = 0; |
|
|
break; |
|
|
} |
|
|
|
|
|
addr = cpu->cd.mips.gpr[rs] + imm; |
|
|
|
|
|
/* Check for natural alignment: */ |
|
|
if ((addr & (wlen - 1)) != 0) { |
|
|
mips_cpu_exception(cpu, st? EXCEPTION_ADES : EXCEPTION_ADEL, |
|
|
0, addr, 0, 0, 0, 0); |
|
|
break; |
|
|
} |
|
|
|
|
|
#if 0 |
|
|
if (cpu->cd.mips.cpu_type.isa_level == 4 && (imm & (wlen - 1)) != 0) |
|
|
debug("WARNING: low bits of imm value not zero! (MIPS IV) " |
|
|
"pc=%016llx", (long long)cpu->cd.mips.pc_last); |
|
|
#endif |
|
|
|
|
|
/* |
|
|
* Load Linked: This initiates a Read-Modify-Write |
|
|
* sequence. |
|
|
*/ |
|
|
if (linked) { |
|
|
if (st==0) { |
|
|
/* st == 0: Load */ |
|
|
cpu->cd.mips.rmw = 1; |
|
|
cpu->cd.mips.rmw_addr = addr; |
|
|
cpu->cd.mips.rmw_len = wlen; |
|
|
|
|
|
/* |
|
|
* COP0_LLADDR is updated for |
|
|
* diagnostic purposes, except for |
|
|
* CPUs in the R10000 family. |
|
|
*/ |
|
|
if (cpu->cd.mips.cpu_type.exc_model != MMU10K) |
|
|
cp0->reg[COP0_LLADDR] = |
|
|
(addr >> 4) & 0xffffffffULL; |
|
|
} else { |
|
|
/* |
|
|
* st == 1: Store |
|
|
* If rmw is 0, then the store failed. |
|
|
* (This cache-line was written to by |
|
|
* someone else.) |
|
|
*/ |
|
|
if (cpu->cd.mips.rmw == 0 || |
|
|
cpu->cd.mips.rmw_addr != addr || |
|
|
cpu->cd.mips.rmw_len != wlen) { |
|
|
/* The store failed: */ |
|
|
cpu->cd.mips.gpr[rt] = 0; |
|
|
if (instruction_trace_cached) |
|
|
debug(" [COLLISION] "); |
|
|
break; |
|
|
} |
|
|
} |
|
|
} else { |
|
|
/* |
|
|
* If any kind of load or store occurs between |
|
|
* an ll and an sc, then the ll-sc sequence |
|
|
* should fail. (This is local to each cpu.) |
|
|
*/ |
|
|
cpu->cd.mips.rmw = 0; |
|
|
} |
|
|
|
|
|
value_hi = 0; |
|
|
|
|
|
if (st) { |
|
|
/* store: */ |
|
|
int cpnr, success; |
|
|
|
|
|
if (hi6 == HI6_SWC3 || hi6 == HI6_SWC2 || |
|
|
hi6 == HI6_SDC1 || hi6 == HI6_SWC1) { |
|
|
cpnr = 1; |
|
|
switch (hi6) { |
|
|
case HI6_SWC3: cpnr++; /* fallthrough */ |
|
|
case HI6_SWC2: cpnr++; |
|
|
case HI6_SDC1: |
|
|
case HI6_SWC1: if (cpu->cd.mips.coproc[cpnr] == NULL || |
|
|
(!(cp0->reg[COP0_STATUS] & ((1 << cpnr) << STATUS_CU_SHIFT))) ) { |
|
|
mips_cpu_exception(cpu, EXCEPTION_CPU, 0, 0, cpnr, 0, 0, 0); |
|
|
cpnr = -1; |
|
|
break; |
|
|
} else { |
|
|
/* Special handling of 64-bit stores |
|
|
on 32-bit CPUs, and on newer CPUs |
|
|
in 32-bit compatiblity mode: */ |
|
|
if ((hi6==HI6_SDC1 || hi6==HI6_SDC2) && |
|
|
(cpu->cd.mips.cpu_type.isa_level <= 2 || |
|
|
!(cp0->reg[COP0_STATUS] & STATUS_FR))) { |
|
|
uint64_t a, b; |
|
|
coproc_register_read(cpu, |
|
|
cpu->cd.mips.coproc[cpnr], rt, &a, 0); |
|
|
coproc_register_read(cpu, |
|
|
cpu->cd.mips.coproc[cpnr], rt^1, &b, 0); |
|
|
if (rt & 1) |
|
|
fatal("WARNING: SDCx in 32-bit mode from odd register!\n"); |
|
|
value = (a & 0xffffffffULL) |
|
|
| (b << 32); |
|
|
} else |
|
|
coproc_register_read(cpu, cpu->cd.mips.coproc[cpnr], rt, &value, 0); |
|
|
} |
|
|
break; |
|
|
default: |
|
|
; |
|
|
} |
|
|
if (cpnr < 0) |
|
|
break; |
|
|
} else |
|
|
value = cpu->cd.mips.gpr[rt]; |
|
|
|
|
|
if (wlen == 4) { |
|
|
/* Special case for 32-bit stores... (perhaps not worth it) */ |
|
|
if (cpu->byte_order == EMUL_LITTLE_ENDIAN) { |
|
|
d[0] = value & 0xff; d[1] = (value >> 8) & 0xff; |
|
|
d[2] = (value >> 16) & 0xff; d[3] = (value >> 24) & 0xff; |
|
|
} else { |
|
|
d[3] = value & 0xff; d[2] = (value >> 8) & 0xff; |
|
|
d[1] = (value >> 16) & 0xff; d[0] = (value >> 24) & 0xff; |
|
|
} |
|
|
} else if (wlen == 16) { |
|
|
value_hi = cpu->cd.mips.gpr_quadhi[rt]; |
|
|
/* Special case for R5900 128-bit stores: */ |
|
|
if (cpu->byte_order == EMUL_LITTLE_ENDIAN) |
|
|
for (i=0; i<8; i++) { |
|
|
d[i] = (value >> (i*8)) & 255; |
|
|
d[i+8] = (value_hi >> (i*8)) & 255; |
|
|
} |
|
|
else |
|
|
for (i=0; i<8; i++) { |
|
|
d[i] = (value >> ((wlen-1-i)*8)) & 255; |
|
|
d[i + 8] = (value_hi >> ((wlen-1-i)*8)) & 255; |
|
|
} |
|
|
} else if (wlen == 1) { |
|
|
d[0] = value & 0xff; |
|
|
} else { |
|
|
/* General case: */ |
|
|
uint64_t v = value; |
|
|
if (cpu->byte_order == |
|
|
EMUL_LITTLE_ENDIAN) |
|
|
for (i=0; i<wlen; i++) { |
|
|
d[i] = v & 255; |
|
|
v >>= 8; |
|
|
} |
|
|
else |
|
|
for (i=0; i<wlen; i++) { |
|
|
d[wlen-1-i] = v & 255; |
|
|
v >>= 8; |
|
|
} |
|
|
} |
|
|
|
|
|
success = cpu->memory_rw(cpu, cpu->mem, addr, |
|
|
d, wlen, MEM_WRITE, CACHE_DATA); |
|
|
if (!success) { |
|
|
/* The store failed, and might have caused an exception. */ |
|
|
if (instruction_trace_cached) |
|
|
debug("(failed)]\n"); |
|
|
break; |
|
|
} |
|
|
} else { |
|
|
/* load: */ |
|
|
int cpnr = 1; |
|
|
int success; |
|
|
|
|
|
success = cpu->memory_rw(cpu, cpu->mem, addr, |
|
|
d, wlen, MEM_READ, CACHE_DATA); |
|
|
if (!success) { |
|
|
/* The load failed, and might have caused an exception. */ |
|
|
if (instruction_trace_cached) |
|
|
debug("(failed)]\n"); |
|
|
break; |
|
|
} |
|
|
|
|
|
if (wlen == 1) |
|
|
value = d[0] | (signd && (d[0]&128)? (-1 << 8) : 0); |
|
|
else if (wlen != 16) { |
|
|
/* General case (except for 128-bit): */ |
|
|
int i; |
|
|
value = 0; |
|
|
if (cpu->byte_order == EMUL_LITTLE_ENDIAN) { |
|
|
if (signd && (d[wlen-1] & 128)!=0) /* sign extend */ |
|
|
value = -1; |
|
|
for (i=wlen-1; i>=0; i--) { |
|
|
value <<= 8; |
|
|
value += d[i]; |
|
|
} |
|
|
} else { |
|
|
if (signd && (d[0] & 128)!=0) /* sign extend */ |
|
|
value = -1; |
|
|
for (i=0; i<wlen; i++) { |
|
|
value <<= 8; |
|
|
value += d[i]; |
|
|
} |
|
|
} |
|
|
} else { |
|
|
/* R5900 128-bit quadword: */ |
|
|
int i; |
|
|
value_hi = 0; |
|
|
value = 0; |
|
|
if (cpu->byte_order == EMUL_LITTLE_ENDIAN) { |
|
|
for (i=wlen-1; i>=0; i--) { |
|
|
value_hi <<= 8; |
|
|
value_hi += (value >> 56) & 255; |
|
|
value <<= 8; |
|
|
value += d[i]; |
|
|
} |
|
|
} else { |
|
|
for (i=0; i<wlen; i++) { |
|
|
value_hi <<= 8; |
|
|
value_hi += (value >> 56) & 255; |
|
|
value <<= 8; |
|
|
value += d[i]; |
|
|
} |
|
|
} |
|
|
cpu->cd.mips.gpr_quadhi[rt] = value_hi; |
|
|
} |
|
|
|
|
|
switch (hi6) { |
|
|
case HI6_LWC3: cpnr++; /* fallthrough */ |
|
|
case HI6_LDC2: |
|
|
case HI6_LWC2: cpnr++; |
|
|
case HI6_LDC1: |
|
|
case HI6_LWC1: if (cpu->cd.mips.coproc[cpnr] == NULL || |
|
|
(!(cp0->reg[COP0_STATUS] & ((1 << cpnr) << STATUS_CU_SHIFT))) ) { |
|
|
mips_cpu_exception(cpu, EXCEPTION_CPU, 0, 0, cpnr, 0, 0, 0); |
|
|
} else { |
|
|
/* Special handling of 64-bit loads |
|
|
on 32-bit CPUs, and on newer CPUs |
|
|
in 32-bit compatiblity mode: */ |
|
|
if ((hi6==HI6_LDC1 || hi6==HI6_LDC2) && |
|
|
(cpu->cd.mips.cpu_type.isa_level <= 2 || |
|
|
!(cp0->reg[COP0_STATUS] & STATUS_FR))) { |
|
|
uint64_t a, b; |
|
|
a = (int64_t)(int32_t) (value & 0xffffffffULL); |
|
|
b = (int64_t)(int32_t) (value >> 32); |
|
|
coproc_register_write(cpu, |
|
|
cpu->cd.mips.coproc[cpnr], rt, &a, |
|
|
hi6==HI6_LDC1 || hi6==HI6_LDC2, 0); |
|
|
coproc_register_write(cpu, |
|
|
cpu->cd.mips.coproc[cpnr], rt ^ 1, &b, |
|
|
hi6==HI6_LDC1 || hi6==HI6_LDC2, 0); |
|
|
if (rt & 1) |
|
|
fatal("WARNING: LDCx in 32-bit mode to odd register!\n"); |
|
|
} else { |
|
|
coproc_register_write(cpu, |
|
|
cpu->cd.mips.coproc[cpnr], rt, &value, |
|
|
hi6==HI6_LDC1 || hi6==HI6_LDC2, 0); |
|
|
} |
|
|
} |
|
|
break; |
|
|
default: if (rt != 0) |
|
|
cpu->cd.mips.gpr[rt] = value; |
|
|
} |
|
|
} |
|
|
|
|
|
if (linked && st==1) { |
|
|
/* |
|
|
* The store succeeded. Invalidate any other |
|
|
* cpu's store to this cache line, and then |
|
|
* return 1 in gpr rt: |
|
|
* |
|
|
* (this is a semi-ugly hack using global |
|
|
* 'cpus') |
|
|
* |
|
|
* TODO: How about invalidating other CPUs |
|
|
* stores to this cache line, even if this |
|
|
* was _NOT_ a linked store? |
|
|
*/ |
|
|
for (i=0; i<cpu->machine->ncpus; i++) { |
|
|
if (cpu->machine->cpus[i]->cd.mips.rmw) { |
|
|
uint64_t yaddr = addr; |
|
|
uint64_t xaddr = |
|
|
cpu->machine->cpus[i]->cd.mips.rmw_addr; |
|
|
uint64_t mask; |
|
|
mask = ~(cpu->machine->cpus[i]-> |
|
|
cd.mips.cache_linesize[CACHE_DATA] |
|
|
- 1); |
|
|
xaddr &= mask; |
|
|
yaddr &= mask; |
|
|
if (xaddr == yaddr) { |
|
|
cpu->machine->cpus[i]->cd.mips.rmw = 0; |
|
|
cpu->machine->cpus[i]->cd.mips.rmw_addr = 0; |
|
|
} |
|
|
} |
|
|
} |
|
|
|
|
|
if (rt != 0) |
|
|
cpu->cd.mips.gpr[rt] = 1; |
|
|
|
|
|
if (instruction_trace_cached) |
|
|
debug(" [no collision] "); |
|
|
cpu->cd.mips.rmw = 0; |
|
|
} |
|
|
|
|
|
if (instruction_trace_cached) { |
|
|
switch (wlen) { |
|
|
case 2: debug("0x%04x", (int)value); break; |
|
|
case 4: debug("0x%08x", (int)value); break; |
|
|
case 8: debug("0x%016llx", (long long)value); |
|
|
break; |
|
|
case 16:debug("0x%016llx", (long long)value_hi); |
|
|
debug("%016llx", (long long)value); |
|
|
break; |
|
|
default:debug("0x%02x", (int)value); |
|
|
} |
|
|
debug("]\n"); |
|
|
} |
|
|
return 1; |
|
|
case HI6_LWL: /* Unaligned load/store */ |
|
|
case HI6_LWR: |
|
|
case HI6_LDL: |
|
|
case HI6_LDR: |
|
|
case HI6_SWL: |
|
|
case HI6_SWR: |
|
|
case HI6_SDL: |
|
|
case HI6_SDR: |
|
|
/* For L (Left): address is the most significant byte */ |
|
|
/* For R (Right): address is the least significant byte */ |
|
|
addr = cpu->cd.mips.gpr[rs] + imm; |
|
|
|
|
|
is_left = 0; |
|
|
if (hi6 == HI6_SWL || hi6 == HI6_LWL || |
|
|
hi6 == HI6_SDL || hi6 == HI6_LDL) |
|
|
is_left = 1; |
|
|
|
|
|
wlen = 0; st = 0; |
|
|
signd = 0; |
|
|
if (hi6 == HI6_LWL || hi6 == HI6_LWR) |
|
|
signd = 1; |
|
|
|
|
|
if (hi6 == HI6_LWL || hi6 == HI6_LWR) { wlen = 4; st = 0; } |
|
|
if (hi6 == HI6_SWL || hi6 == HI6_SWR) { wlen = 4; st = 1; } |
|
|
if (hi6 == HI6_LDL || hi6 == HI6_LDR) { wlen = 8; st = 0; } |
|
|
if (hi6 == HI6_SDL || hi6 == HI6_SDR) { wlen = 8; st = 1; } |
|
|
|
|
|
dir = 1; /* big endian, Left */ |
|
|
reg_dir = -1; |
|
|
reg_ofs = wlen - 1; /* byte offset in the register */ |
|
|
if (!is_left) { |
|
|
dir = -dir; |
|
|
reg_ofs = 0; |
|
|
reg_dir = 1; |
|
|
} |
|
|
if (cpu->byte_order == EMUL_LITTLE_ENDIAN) |
|
|
dir = -dir; |
|
|
|
|
|
result_value = cpu->cd.mips.gpr[rt]; |
|
|
|
|
|
if (st) { |
|
|
/* Store: */ |
|
|
uint64_t aligned_addr = addr & ~(wlen-1); |
|
|
unsigned char aligned_word[8]; |
|
|
uint64_t oldpc = cpu->pc; |
|
|
/* |
|
|
* NOTE (this is ugly): The memory_rw() |
|
|
* call generates a TLBL exception, if there |
|
|
* is a tlb refill exception. However, since |
|
|
* this is a Store, the exception is converted |
|
|
* to a TLBS: |
|
|
*/ |
|
|
int ok = cpu->memory_rw(cpu, cpu->mem, |
|
|
aligned_addr, &aligned_word[0], wlen, |
|
|
MEM_READ, CACHE_DATA); |
|
|
if (!ok) { |
|
|
if (cpu->pc != oldpc) { |
|
|
cp0->reg[COP0_CAUSE] &= ~CAUSE_EXCCODE_MASK; |
|
|
cp0->reg[COP0_CAUSE] |= (EXCEPTION_TLBS << CAUSE_EXCCODE_SHIFT); |
|
|
} |
|
|
return 1; |
|
|
} |
|
|
|
|
|
for (i=0; i<wlen; i++) { |
|
|
tmpaddr = addr + i*dir; |
|
|
/* Have we moved into another word/dword? Then stop: */ |
|
|
if ( (tmpaddr & ~(wlen-1)) != (addr & ~(wlen-1)) ) |
|
|
break; |
|
|
|
|
|
/* debug("unaligned byte at %016llx, reg_ofs=%i reg=0x%016llx\n", |
|
|
tmpaddr, reg_ofs, (long long)result_value); */ |
|
|
|
|
|
/* Store one byte: */ |
|
|
aligned_word[tmpaddr & (wlen-1)] = (result_value >> (reg_ofs * 8)) & 255; |
|
|
|
|
|
reg_ofs += reg_dir; |
|
|
} |
|
|
|
|
|
ok = cpu->memory_rw(cpu, cpu->mem, |
|
|
aligned_addr, &aligned_word[0], wlen, |
|
|
MEM_WRITE, CACHE_DATA); |
|
|
if (!ok) |
|
|
return 1; |
|
|
} else { |
|
|
/* Load: */ |
|
|
uint64_t aligned_addr = addr & ~(wlen-1); |
|
|
unsigned char aligned_word[8], databyte; |
|
|
int ok = cpu->memory_rw(cpu, cpu->mem, |
|
|
aligned_addr, &aligned_word[0], wlen, |
|
|
MEM_READ, CACHE_DATA); |
|
|
if (!ok) |
|
|
return 1; |
|
|
|
|
|
for (i=0; i<wlen; i++) { |
|
|
tmpaddr = addr + i*dir; |
|
|
/* Have we moved into another word/dword? Then stop: */ |
|
|
if ( (tmpaddr & ~(wlen-1)) != (addr & ~(wlen-1)) ) |
|
|
break; |
|
|
|
|
|
/* debug("unaligned byte at %016llx, reg_ofs=%i reg=0x%016llx\n", |
|
|
tmpaddr, reg_ofs, (long long)result_value); */ |
|
|
|
|
|
/* Load one byte: */ |
|
|
databyte = aligned_word[tmpaddr & (wlen-1)]; |
|
|
result_value &= ~((uint64_t)0xff << (reg_ofs * 8)); |
|
|
result_value |= (uint64_t)databyte << (reg_ofs * 8); |
|
|
|
|
|
reg_ofs += reg_dir; |
|
|
} |
|
|
|
|
|
if (rt != 0) |
|
|
cpu->cd.mips.gpr[rt] = result_value; |
|
|
} |
|
|
|
|
|
/* Sign extend for 32-bit load lefts: */ |
|
|
if (!st && signd && wlen == 4) { |
|
|
cpu->cd.mips.gpr[rt] &= 0xffffffffULL; |
|
|
if (cpu->cd.mips.gpr[rt] & 0x80000000ULL) |
|
|
cpu->cd.mips.gpr[rt] |= 0xffffffff00000000ULL; |
|
|
} |
|
|
|
|
|
if (instruction_trace_cached) { |
|
|
char *t; |
|
|
switch (wlen) { |
|
|
case 2: t = "0x%04llx"; break; |
|
|
case 4: t = "0x%08llx"; break; |
|
|
case 8: t = "0x%016llx"; break; |
|
|
default: t = "0x%02llx"; |
|
|
} |
|
|
debug(t, (long long)cpu->cd.mips.gpr[rt]); |
|
|
debug("]\n"); |
|
|
} |
|
|
|
|
|
return 1; |
|
|
} |
|
|
return 1; |
|
|
case HI6_REGIMM: |
|
|
regimm5 = instr[2] & 0x1f; |
|
|
|
|
|
if (show_opcode_statistics) |
|
|
cpu->cd.mips.stats__regimm[regimm5] ++; |
|
|
|
|
|
switch (regimm5) { |
|
|
case REGIMM_BLTZ: |
|
|
case REGIMM_BGEZ: |
|
|
case REGIMM_BLTZL: |
|
|
case REGIMM_BGEZL: |
|
|
case REGIMM_BLTZAL: |
|
|
case REGIMM_BLTZALL: |
|
|
case REGIMM_BGEZAL: |
|
|
case REGIMM_BGEZALL: |
|
|
rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7); |
|
|
imm = (instr[1] << 8) + instr[0]; |
|
|
if (imm >= 32768) /* signed 16-bit */ |
|
|
imm -= 65536; |
|
|
|
|
|
cond = and_link = likely = 0; |
|
|
|
|
|
switch (regimm5) { |
|
|
case REGIMM_BLTZL: likely = 1; |
|
|
case REGIMM_BLTZ: cond = (cpu->cd.mips.gpr[rs] & ((uint64_t)1 << 63)) != 0; |
|
|
break; |
|
|
case REGIMM_BGEZL: likely = 1; |
|
|
case REGIMM_BGEZ: cond = (cpu->cd.mips.gpr[rs] & ((uint64_t)1 << 63)) == 0; |
|
|
break; |
|
|
|
|
|
case REGIMM_BLTZALL: likely = 1; |
|
|
case REGIMM_BLTZAL: and_link = 1; |
|
|
cond = (cpu->cd.mips.gpr[rs] & ((uint64_t)1 << 63)) != 0; |
|
|
break; |
|
|
case REGIMM_BGEZALL: likely = 1; |
|
|
case REGIMM_BGEZAL: and_link = 1; |
|
|
cond = (cpu->cd.mips.gpr[rs] & ((uint64_t)1 << 63)) == 0; |
|
|
break; |
|
|
} |
|
|
|
|
|
if (and_link) |
|
|
cpu->cd.mips.gpr[31] = cached_pc + 4; |
|
|
|
|
|
if (cond) { |
|
|
cpu->cd.mips.delay_slot = TO_BE_DELAYED; |
|
|
cpu->cd.mips.delay_jmpaddr = cached_pc + (imm << 2); |
|
|
} else { |
|
|
if (likely) |
|
|
cpu->cd.mips.nullify_next = 1; /* nullify delay slot */ |
|
|
} |
|
|
|
|
|
return 1; |
|
|
default: |
|
|
if (!instruction_trace_cached) { |
|
|
fatal("cpu%i @ %016llx: %02x%02x%02x%02x%s\t", |
|
|
cpu->cpu_id, (long long)cpu->cd.mips.pc_last, |
|
|
instr[3], instr[2], instr[1], instr[0], cpu_flags(cpu)); |
|
|
} |
|
|
fatal("unimplemented regimm5 = 0x%02x\n", regimm5); |
|
|
cpu->running = 0; |
|
|
return 1; |
|
|
} |
|
|
/* NOT REACHED */ |
|
|
case HI6_J: |
|
|
case HI6_JAL: |
|
|
if (cpu->cd.mips.delay_slot) { |
|
|
fatal("j/jal: jump inside a jump's delay slot, or similar. TODO\n"); |
|
|
cpu->running = 0; |
|
|
return 1; |
|
|
} |
|
|
imm = ((instr[3] & 3) << 24) + (instr[2] << 16) + (instr[1] << 8) + instr[0]; |
|
|
imm <<= 2; |
|
|
|
|
|
if (hi6 == HI6_JAL) |
|
|
cpu->cd.mips.gpr[31] = cached_pc + 4; /* pc already increased by 4 earlier */ |
|
|
|
|
|
addr = cached_pc & ~((1 << 28) - 1); |
|
|
addr |= imm; |
|
|
|
|
|
cpu->cd.mips.delay_slot = TO_BE_DELAYED; |
|
|
cpu->cd.mips.delay_jmpaddr = addr; |
|
|
|
|
|
if (cpu->machine->show_trace_tree && hi6 == HI6_JAL) { |
|
|
cpu->cd.mips.show_trace_delay = 2; |
|
|
cpu->cd.mips.show_trace_addr = addr; |
|
|
} |
|
|
|
|
|
return 1; |
|
|
case HI6_COP0: |
|
|
case HI6_COP1: |
|
|
case HI6_COP2: |
|
|
case HI6_COP3: |
|
|
imm = (instr[3] << 24) + (instr[2] << 16) + (instr[1] << 8) + instr[0]; |
|
|
imm &= ((1 << 26) - 1); |
|
|
|
|
|
cpnr = 0; |
|
|
if (hi6 == HI6_COP0) cpnr = 0; |
|
|
if (hi6 == HI6_COP1) cpnr = 1; |
|
|
if (hi6 == HI6_COP2) cpnr = 2; |
|
|
if (hi6 == HI6_COP3) cpnr = 3; |
|
|
|
|
|
/* |
|
|
* If there is no coprocessor nr cpnr, or we are running in |
|
|
* userland and the coprocessor is not marked as Useable in |
|
|
* the status register of CP0, then we get an exception. |
|
|
* |
|
|
* An exception (hehe) to this rule is that the kernel should |
|
|
* always be able to access CP0. |
|
|
*/ |
|
|
/* Set tmp = 1 if we're in user mode. */ |
|
|
tmp = 0; |
|
|
switch (cpu->cd.mips.cpu_type.exc_model) { |
|
|
case EXC3K: |
|
|
/* |
|
|
* NOTE: If the KU bit is checked, Linux crashes. |
|
|
* It is the PC that counts. TODO: Check whether |
|
|
* this is true or not for R4000 as well. |
|
|
*/ |
|
|
if (cached_pc <= 0x7fffffff) /* if (cp0->reg[COP0_STATUS] & MIPS1_SR_KU_CUR) */ |
|
|
tmp = 1; |
|
|
break; |
|
|
default: |
|
|
/* R4000 etc: (TODO: How about supervisor mode?) */ |
|
|
if (((cp0->reg[COP0_STATUS] & STATUS_KSU_MASK) >> STATUS_KSU_SHIFT) != KSU_KERNEL) |
|
|
tmp = 1; |
|
|
if (cp0->reg[COP0_STATUS] & STATUS_ERL) |
|
|
tmp = 0; |
|
|
if (cp0->reg[COP0_STATUS] & STATUS_EXL) |
|
|
tmp = 0; |
|
|
break; |
|
|
} |
|
|
if (cpu->cd.mips.coproc[cpnr] == NULL || |
|
|
(tmp && !(cp0->reg[COP0_STATUS] & ((1 << cpnr) << STATUS_CU_SHIFT))) || |
|
|
(!tmp && cpnr >= 1 && !(cp0->reg[COP0_STATUS] & ((1 << cpnr) << STATUS_CU_SHIFT))) |
|
|
) { |
|
|
if (instruction_trace_cached) |
|
|
debug("cop%i\t0x%08x => coprocessor unusable\n", cpnr, (int)imm); |
|
|
mips_cpu_exception(cpu, EXCEPTION_CPU, 0, 0, cpnr, 0, 0, 0); |
|
|
} else { |
|
|
/* |
|
|
* Execute the coprocessor function. The |
|
|
* coproc_function code outputs instruction |
|
|
* trace, if necessary. |
|
|
*/ |
|
|
coproc_function(cpu, cpu->cd.mips.coproc[cpnr], |
|
|
cpnr, imm, 0, 1); |
|
|
} |
|
|
return 1; |
|
|
case HI6_CACHE: |
|
|
rt = ((instr[3] & 3) << 3) + (instr[2] >> 5); /* base */ |
|
|
copz = instr[2] & 31; |
|
|
imm = (instr[1] << 8) + instr[0]; |
|
|
|
|
|
cache_op = copz >> 2; |
|
|
which_cache = copz & 3; |
|
|
|
|
|
/* |
|
|
* TODO: The cache instruction is implementation dependant. |
|
|
*/ |
|
|
|
|
|
/* |
|
|
* Clear the LLbit (at least on R10000): |
|
|
* TODO: How about R4000? |
|
|
*/ |
|
|
cpu->cd.mips.rmw = 0; |
|
|
|
|
|
return 1; |
|
|
case HI6_SPECIAL2: |
|
|
special6 = instr[0] & 0x3f; |
|
|
|
|
|
if (show_opcode_statistics) |
|
|
cpu->cd.mips.stats__special2[special6] ++; |
|
|
|
|
|
instrword = (instr[3] << 24) + (instr[2] << 16) + (instr[1] << 8) + instr[0]; |
|
|
|
|
|
rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7); |
|
|
rt = instr[2] & 31; |
|
|
rd = (instr[1] >> 3) & 31; |
|
|
|
|
|
/* printf("special2 %08x rs=0x%02x rt=0x%02x rd=0x%02x\n", instrword, rs,rt,rd); */ |
|
|
|
|
|
/* |
|
|
* Many of these can be found in the R5000 docs, or figured out |
|
|
* by studying binutils source code for MIPS instructions. |
|
|
*/ |
|
|
|
|
|
if ((instrword & 0xfc0007ffULL) == 0x70000000) { |
|
|
{ |
|
|
int32_t a, b; |
|
|
int64_t c; |
|
|
a = (int32_t)cpu->cd.mips.gpr[rs]; |
|
|
b = (int32_t)cpu->cd.mips.gpr[rt]; |
|
|
c = a * b; |
|
|
c += (cpu->cd.mips.lo & 0xffffffffULL) |
|
|
+ (cpu->cd.mips.hi << 32); |
|
|
cpu->cd.mips.lo = (int64_t)((int32_t)c); |
|
|
cpu->cd.mips.hi = (int64_t)((int32_t)(c >> 32)); |
|
|
|
|
|
/* |
|
|
* The R5000 manual says that rd should be all zeros, |
|
|
* but it isn't on R5900. I'm just guessing here that |
|
|
* it stores the value in register rd, in addition to hi/lo. |
|
|
* TODO |
|
|
*/ |
|
|
if (rd != 0) |
|
|
cpu->cd.mips.gpr[rd] = cpu->cd.mips.lo; |
|
|
} |
|
|
} else if ((instrword & 0xffff07ffULL) == 0x70000209 |
|
|
|| (instrword & 0xffff07ffULL) == 0x70000249) { |
|
|
/* |
|
|
* This is just a guess for R5900, I've not found any docs on this one yet. |
|
|
* |
|
|
* pmfhi/pmflo rd |
|
|
* |
|
|
* If the lowest 8 bits of the instruction word are 0x09, it's a pmfhi. |
|
|
* If the lowest bits are 0x49, it's a pmflo. |
|
|
* |
|
|
* A wild guess is that this is a 128-bit version of mfhi/mflo. |
|
|
* For now, this is implemented as 64-bit only. (TODO) |
|
|
*/ |
|
|
if (instr[0] == 0x49) { |
|
|
cpu->cd.mips.gpr[rd] = cpu->cd.mips.lo; |
|
|
} else { |
|
|
cpu->cd.mips.gpr[rd] = cpu->cd.mips.hi; |
|
|
} |
|
|
} else if ((instrword & 0xfc1fffff) == 0x70000269 || (instrword & 0xfc1fffff) == 0x70000229) { |
|
|
/* |
|
|
* This is just a guess for R5900, I've not found any docs on this one yet. |
|
|
* |
|
|
* pmthi/pmtlo rs (pmtlo = 269, pmthi = 229) |
|
|
* |
|
|
* A wild guess is that this is a 128-bit version of mthi/mtlo. |
|
|
* For now, this is implemented as 64-bit only. (TODO) |
|
|
*/ |
|
|
if (instr[0] == 0x69) { |
|
|
cpu->cd.mips.lo = cpu->cd.mips.gpr[rs]; |
|
|
} else { |
|
|
cpu->cd.mips.hi = cpu->cd.mips.gpr[rs]; |
|
|
} |
|
|
} else if ((instrword & 0xfc0007ff) == 0x700004a9) { |
|
|
/* |
|
|
* This is just a guess for R5900, I've not found any docs on this one yet. |
|
|
* |
|
|
* por dst,src,src2 ==> rs=src rt=src2 rd=dst |
|
|
* |
|
|
* A wild guess is that this is a 128-bit "or" between two registers. |
|
|
* For now, let's just or using 64-bits. (TODO) |
|
|
*/ |
|
|
cpu->cd.mips.gpr[rd] = cpu->cd.mips.gpr[rs] | cpu->cd.mips.gpr[rt]; |
|
|
} else if ((instrword & 0xfc0007ff) == 0x70000488) { |
|
|
/* |
|
|
* R5900 "undocumented" pextlw. TODO: find out if this is correct. |
|
|
* It seems that this instruction is used to combine two 32-bit |
|
|
* words into a 64-bit dword, typically before a sd (store dword). |
|
|
*/ |
|
|
cpu->cd.mips.gpr[rd] = |
|
|
((cpu->cd.mips.gpr[rs] & 0xffffffffULL) << 32) /* TODO: switch rt and rs? */ |
|
|
| (cpu->cd.mips.gpr[rt] & 0xffffffffULL); |
|
|
} else if (special6 == SPECIAL2_MUL) { |
|
|
cpu->cd.mips.gpr[rd] = (int64_t)cpu->cd.mips.gpr[rt] * |
|
|
(int64_t)cpu->cd.mips.gpr[rs]; |
|
|
} else if (special6 == SPECIAL2_CLZ) { |
|
|
/* clz: count leading zeroes */ |
|
|
int i, n=0; |
|
|
for (i=31; i>=0; i--) { |
|
|
if (cpu->cd.mips.gpr[rs] & ((uint32_t)1 << i)) |
|
|
break; |
|
|
else |
|
|
n++; |
|
|
} |
|
|
cpu->cd.mips.gpr[rd] = n; |
|
|
} else if (special6 == SPECIAL2_CLO) { |
|
|
/* clo: count leading ones */ |
|
|
int i, n=0; |
|
|
for (i=31; i>=0; i--) { |
|
|
if (cpu->cd.mips.gpr[rs] & ((uint32_t)1 << i)) |
|
|
n++; |
|
|
else |
|
|
break; |
|
|
} |
|
|
cpu->cd.mips.gpr[rd] = n; |
|
|
} else if (special6 == SPECIAL2_DCLZ) { |
|
|
/* dclz: count leading zeroes */ |
|
|
int i, n=0; |
|
|
for (i=63; i>=0; i--) { |
|
|
if (cpu->cd.mips.gpr[rs] & ((uint64_t)1 << i)) |
|
|
break; |
|
|
else |
|
|
n++; |
|
|
} |
|
|
cpu->cd.mips.gpr[rd] = n; |
|
|
} else if (special6 == SPECIAL2_DCLO) { |
|
|
/* dclo: count leading ones */ |
|
|
int i, n=0; |
|
|
for (i=63; i>=0; i--) { |
|
|
if (cpu->cd.mips.gpr[rs] & ((uint64_t)1 << i)) |
|
|
n++; |
|
|
else |
|
|
break; |
|
|
} |
|
|
cpu->cd.mips.gpr[rd] = n; |
|
|
} else { |
|
|
if (!instruction_trace_cached) { |
|
|
fatal("cpu%i @ %016llx: %02x%02x%02x%02x%s\t", |
|
|
cpu->cpu_id, (long long)cpu->cd.mips.pc_last, |
|
|
instr[3], instr[2], instr[1], instr[0], cpu_flags(cpu)); |
|
|
} |
|
|
fatal("unimplemented special_2 = 0x%02x, rs=0x%02x rt=0x%02x rd=0x%02x\n", |
|
|
special6, rs, rt, rd); |
|
|
cpu->running = 0; |
|
|
return 1; |
|
|
} |
|
|
return 1; |
|
|
default: |
|
|
if (!instruction_trace_cached) { |
|
|
fatal("cpu%i @ %016llx: %02x%02x%02x%02x%s\t", |
|
|
cpu->cpu_id, (long long)cpu->cd.mips.pc_last, |
|
|
instr[3], instr[2], instr[1], instr[0], cpu_flags(cpu)); |
|
|
} |
|
|
fatal("unimplemented hi6 = 0x%02x\n", hi6); |
|
|
cpu->running = 0; |
|
|
return 1; |
|
|
} |
|
|
|
|
|
/* NOTREACHED */ |
|
|
} |
|
|
|
|
|
|
|
|
#define CPU_RUN mips_cpu_run |
|
|
#define CPU_RUN_MIPS |
|
|
#define CPU_RINSTR mips_cpu_run_instr |
|
|
#include "cpu_run.c" |
|
|
#undef CPU_RINSTR |
|
|
#undef CPU_RUN_MIPS |
|
|
#undef CPU_RUN |
|
|
|
|
|
|
|
|
/* |
|
|
* mips_cpu_dumpinfo(): |
|
|
* |
|
|
* Debug dump of MIPS-specific CPU data for specific CPU. |
|
|
*/ |
|
|
void mips_cpu_dumpinfo(struct cpu *cpu) |
|
|
{ |
|
|
int iadd = 4; |
|
|
struct mips_cpu_type_def *ct = &cpu->cd.mips.cpu_type; |
|
|
|
|
|
debug_indentation(iadd); |
|
|
|
|
|
debug("\n%i-bit %s (MIPS", |
|
|
cpu->is_32bit? 32 : 64, |
|
|
cpu->byte_order == EMUL_BIG_ENDIAN? "BE" : "LE"); |
|
|
|
|
|
switch (ct->isa_level) { |
|
|
case 1: debug(" ISA I"); break; |
|
|
case 2: debug(" ISA II"); break; |
|
|
case 3: debug(" ISA III"); break; |
|
|
case 4: debug(" ISA IV"); break; |
|
|
case 5: debug(" ISA V"); break; |
|
|
case 32: |
|
|
case 64:debug("%i", ct->isa_level); break; |
|
|
default:debug(" ISA level %i", ct->isa_level); |
|
|
} |
|
|
|
|
|
debug("), "); |
|
|
if (ct->nr_of_tlb_entries) |
|
|
debug("%i TLB entries", ct->nr_of_tlb_entries); |
|
|
else |
|
|
debug("no TLB"); |
|
|
debug("\n"); |
|
|
|
|
|
if (ct->picache) { |
|
|
debug("L1 I-cache: %i KB", (1 << ct->picache) / 1024); |
|
|
if (ct->pilinesize) |
|
|
debug(", %i bytes per line", 1 << ct->pilinesize); |
|
|
if (ct->piways > 1) |
|
|
debug(", %i-way", ct->piways); |
|
|
else |
|
|
debug(", direct-mapped"); |
|
|
debug("\n"); |
|
|
} |
|
|
|
|
|
if (ct->pdcache) { |
|
|
debug("L1 D-cache: %i KB", (1 << ct->pdcache) / 1024); |
|
|
if (ct->pdlinesize) |
|
|
debug(", %i bytes per line", 1 << ct->pdlinesize); |
|
|
if (ct->pdways > 1) |
|
|
debug(", %i-way", ct->pdways); |
|
|
else |
|
|
debug(", direct-mapped"); |
|
|
debug("\n"); |
|
|
} |
|
|
|
|
|
if (ct->scache) { |
|
|
int kb = (1 << ct->scache) / 1024; |
|
|
debug("L2 cache: %i %s", |
|
|
kb >= 1024? kb / 1024 : kb, kb >= 1024? "MB":"KB"); |
|
|
if (ct->slinesize) |
|
|
debug(", %i bytes per line", 1 << ct->slinesize); |
|
|
if (ct->sways > 1) |
|
|
debug(", %i-way", ct->sways); |
|
|
else |
|
|
debug(", direct-mapped"); |
|
|
debug("\n"); |
|
2118 |
} |
} |
|
|
|
|
debug_indentation(-iadd); |
|
2119 |
} |
} |
2120 |
|
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2121 |
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2122 |
/* |
#include "memory_mips.c" |
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* mips_cpu_list_available_types(): |
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* |
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* Print a list of available MIPS CPU types. |
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*/ |
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void mips_cpu_list_available_types(void) |
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{ |
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int i, j; |
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struct mips_cpu_type_def cpu_type_defs[] = MIPS_CPU_TYPE_DEFS; |
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i = 0; |
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while (cpu_type_defs[i].name != NULL) { |
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|
debug("%s", cpu_type_defs[i].name); |
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for (j=10 - strlen(cpu_type_defs[i].name); j>0; j--) |
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|
debug(" "); |
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|
i++; |
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|
if ((i % 6) == 0 || cpu_type_defs[i].name == NULL) |
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|
debug("\n"); |
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} |
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} |
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|
2123 |
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|
|
CPU_FAMILY_INIT(mips,"MIPS") |
|
2124 |
|
|
2125 |
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#include "tmp_mips_tail.c" |
2126 |
|
|
|
#endif /* ENABLE_MIPS */ |
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