25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: cpu_mips.c,v 1.4 2005/10/07 23:13:51 debug Exp $ |
* $Id: cpu_mips.c,v 1.6 2005/10/26 14:37:02 debug Exp $ |
29 |
* |
* |
30 |
* MIPS core CPU emulation. |
* MIPS core CPU emulation. |
31 |
*/ |
*/ |
158 |
cpu->byte_order = EMUL_LITTLE_ENDIAN; |
cpu->byte_order = EMUL_LITTLE_ENDIAN; |
159 |
cpu->cd.mips.gpr[MIPS_GPR_SP] = INITIAL_STACK_POINTER; |
cpu->cd.mips.gpr[MIPS_GPR_SP] = INITIAL_STACK_POINTER; |
160 |
cpu->update_translation_table = mips_update_translation_table; |
cpu->update_translation_table = mips_update_translation_table; |
161 |
cpu->invalidate_translation_caches_paddr = |
cpu->invalidate_translation_caches = |
162 |
mips_invalidate_translation_caches_paddr; |
mips_invalidate_translation_caches_paddr; |
163 |
|
|
164 |
if (cpu->cd.mips.cpu_type.isa_level <= 2 || |
if (cpu->cd.mips.cpu_type.isa_level <= 2 || |
1468 |
* Acknowledge an interrupt. If irq_nr is 2..7, then it is a MIPS hardware |
* Acknowledge an interrupt. If irq_nr is 2..7, then it is a MIPS hardware |
1469 |
* interrupt. Interrupts 0..1 are ignored (software interrupts). |
* interrupt. Interrupts 0..1 are ignored (software interrupts). |
1470 |
* |
* |
1471 |
* If irq_nr is >= 8, then it is machine dependant, and md_interrupt() is |
* If irq_nr is >= 8, then it is machine dependent, and md_interrupt() is |
1472 |
* called. |
* called. |
1473 |
*/ |
*/ |
1474 |
int mips_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr) |
int mips_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr) |