src/cpus/cpu_m88k_instr.c

/*
 *  Copyright (C) 2007  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *
 *
 *  $Id: cpu_m88k_instr.c,v 1.5 2007/04/28 09:19:51 debug Exp $
 *
 *  M88K instructions.
 *
 *  Individual functions should keep track of cpu->n_translated_instrs.
 *  (If no instruction was executed, then it should be decreased. If, say, 4
 *  instructions were combined into one function and executed, then it should
 *  be increased by 3.)
 */


/*
 *  nop:  Do nothing.
 */
X(nop)
{
}


/*
 *  br_samepage:  Branch (to within the same translated page)
 *
 *  arg[0] = pointer to new instr_call
 */
X(br_samepage)
{
        cpu->cd.m88k.next_ic = (struct m88k_instr_call *) ic->arg[0];
}


/*
 *  br:  Branch (to a different translated page)
 *
 *  arg[0] = relative offset from start of page
 */
X(br)
{
        cpu->pc = (uint32_t)((cpu->pc & 0xfffff000) + (int32_t)ic->arg[0]);

        /*  Find the new physical page and update the translation pointers:  */
        quick_pc_to_pointers(cpu);
}


/*
 *  or_imm:     d = s1 | imm
 *  or_r0_imm:  d = imm         (optimized case when s1 = r0)
 *
 *  arg[0] = pointer to register d
 *  arg[1] = pointer to register s1
 *  arg[2] = imm
 */
X(or_imm)
{
        reg(ic->arg[0]) = reg(ic->arg[1]) | ic->arg[2];
}
X(or_r0_imm)
{
        reg(ic->arg[0]) = ic->arg[2];
}


/*****************************************************************************/


X(end_of_page)
{
        /*  Update the PC:  (offset 0, but on the next page)  */
        cpu->pc &= ~((M88K_IC_ENTRIES_PER_PAGE-1) <<
            M88K_INSTR_ALIGNMENT_SHIFT);
        cpu->pc += (M88K_IC_ENTRIES_PER_PAGE << M88K_INSTR_ALIGNMENT_SHIFT);

        /*  end_of_page doesn't count as an executed instruction:  */
        cpu->n_translated_instrs --;

        /*
         *  Find the new physpage and update translation pointers.
         *
         *  Note: This may cause an exception, if e.g. the new page is
         *  not accessible.
         */
        quick_pc_to_pointers(cpu);

        /*  Simple jump to the next page (if we are lucky):  */
        if (cpu->delay_slot == NOT_DELAYED)
                return;

        /*
         *  If we were in a delay slot, and we got an exception while doing
         *  quick_pc_to_pointers, then return. The function which called
         *  end_of_page should handle this case.
         */
        if (cpu->delay_slot == EXCEPTION_IN_DELAY_SLOT)
                return;

        /*
         *  Tricky situation; the delay slot is on the next virtual page.
         *  Calling to_be_translated will translate one instruction manually,
         *  execute it, and then discard it.
         */
        /*  fatal("[ end_of_page: delay slot across page boundary! ]\n");  */

        instr(to_be_translated)(cpu, cpu->cd.m88k.next_ic);

        /*  The instruction in the delay slot has now executed.  */
        /*  fatal("[ end_of_page: back from executing the delay slot, %i ]\n",
            cpu->delay_slot);  */

        /*  Find the physpage etc of the instruction in the delay slot
            (or, if there was an exception, the exception handler):  */
        quick_pc_to_pointers(cpu);
}


X(end_of_page2)
{
        /*  Synchronize PC on the _second_ instruction on the next page:  */
        int low_pc = ((size_t)ic - (size_t)cpu->cd.m88k.cur_ic_page)
            / sizeof(struct m88k_instr_call);
        cpu->pc &= ~((M88K_IC_ENTRIES_PER_PAGE-1)
            << M88K_INSTR_ALIGNMENT_SHIFT);
        cpu->pc += (low_pc << M88K_INSTR_ALIGNMENT_SHIFT);

        /*  This doesn't count as an executed instruction.  */
        cpu->n_translated_instrs --;

        quick_pc_to_pointers(cpu);

        if (cpu->delay_slot == NOT_DELAYED)
                return;

        fatal("end_of_page2: fatal error, we're in a delay slot\n");
        exit(1);
}


/*****************************************************************************/


/*
 *  m88k_instr_to_be_translated():
 *
 *  Translate an instruction word into a m88k_instr_call. ic is filled in with
 *  valid data for the translated instruction, or a "nothing" instruction if
 *  there was a translation failure. The newly translated instruction is then
 *  executed.
 */
X(to_be_translated)
{
        uint32_t addr, low_pc, iword;
        unsigned char *page;
        unsigned char ib[4];
        uint32_t op26, op10, op11, d, s1, s2, w5, imm16;
        int32_t d16, d26, simm16;
        int offset, shift;
        int in_crosspage_delayslot = 0;
        void (*samepage_function)(struct cpu *, struct m88k_instr_call *);

        /*  Figure out the (virtual) address of the instruction:  */
        low_pc = ((size_t)ic - (size_t)cpu->cd.m88k.cur_ic_page)
            / sizeof(struct m88k_instr_call);

        /*  Special case for branch with delayslot on the next page:  */
        if (cpu->delay_slot == TO_BE_DELAYED && low_pc == 0) {
                /*  fatal("[ delay-slot translation across page "
                    "boundary ]\n");  */
                in_crosspage_delayslot = 1;
        }

        addr = cpu->pc & ~((M88K_IC_ENTRIES_PER_PAGE-1)
            << M88K_INSTR_ALIGNMENT_SHIFT);
        addr += (low_pc << M88K_INSTR_ALIGNMENT_SHIFT);
        cpu->pc = (MODE_int_t)addr;
        addr &= ~((1 << M88K_INSTR_ALIGNMENT_SHIFT) - 1);

        /*  Read the instruction word from memory:  */
        page = cpu->cd.m88k.host_load[(uint32_t)addr >> 12];

        if (page != NULL) {
                /*  fatal("TRANSLATION HIT!\n");  */
                memcpy(ib, page + (addr & 0xffc), sizeof(ib));
        } else {
                /*  fatal("TRANSLATION MISS!\n");  */
                if (!cpu->memory_rw(cpu, cpu->mem, addr, ib,
                    sizeof(ib), MEM_READ, CACHE_INSTRUCTION)) {
                        fatal("to_be_translated(): read failed: TODO\n");
                        goto bad;
                }
        }

        iword = *((uint32_t *)&ib[0]);
        if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
                iword = LE32_TO_HOST(iword);
        else
                iword = BE32_TO_HOST(iword);


#define DYNTRANS_TO_BE_TRANSLATED_HEAD
#include "cpu_dyntrans.c"
#undef  DYNTRANS_TO_BE_TRANSLATED_HEAD


        /*
         *  Translate the instruction:
         *
         *  NOTE: _NEVER_ allow writes to the zero register; all instructions
         *  that use the zero register as their destination should be treated
         *  as NOPs, except those that access memory (they should use the
         *  scratch register instead).
         */

        op26   = (iword >> 26) & 0x3f;
        op11   = (iword >> 11) & 0x1f;
        op10   = (iword >> 10) & 0x3f;
        d      = (iword >> 21) & 0x1f;
        s1     = (iword >> 16) & 0x1f;
        s2     =  iword        & 0x1f;
        imm16  =  iword        & 0xffff;
        simm16 = (int16_t) (iword & 0xffff);
        w5     = (iword >>  5) & 0x1f;
        d16    = ((int16_t) (iword & 0xffff)) * 4;
        d26    = ((int32_t)((iword & 0x03ffffff) << 6)) >> 4;

        switch (op26) {

        case 0x16:      /*  or   imm  */
        case 0x17:      /*  or.u imm  */
                shift = 0;
                switch (op26) {
                case 0x16: ic->f = instr(or_imm); break;
                case 0x17: ic->f = instr(or_imm); shift = 16; break;
                }

                ic->arg[0] = (size_t) &cpu->cd.m88k.r[d];
                ic->arg[1] = (size_t) &cpu->cd.m88k.r[s1];
                ic->arg[2] = imm16 << shift;

                /*  Optimization for  or d,r0,imm  */
                if (s1 == M88K_ZERO_REG && ic->f == instr(or_imm))
                        ic->f = instr(or_r0_imm);

                if (d == M88K_ZERO_REG)
                        ic->f = instr(nop);
                break;

        case 0x30:      /*  br  */
                ic->f = instr(br);
                samepage_function = instr(br_samepage);

                offset = (addr & 0xffc) + d26;
                if (offset >= 0 && offset <= 0xffc) {
                        /*  Same page:  */
                        ic->arg[0] = (size_t) ( cpu->cd.m88k.cur_ic_page +
                            (offset >> M88K_INSTR_ALIGNMENT_SHIFT) );
                        ic->f = samepage_function;
                } else {
                        /*  Different page:  */
                        ic->arg[0] = offset;
                }
                break;

        default:goto bad;
        }


#define DYNTRANS_TO_BE_TRANSLATED_TAIL
#include "cpu_dyntrans.c" 
#undef  DYNTRANS_TO_BE_TRANSLATED_TAIL
}

1	dpavlin	40	/*
2			* Copyright (C) 2007 Anders Gavare. All rights reserved.
3			*
4			* Redistribution and use in source and binary forms, with or without
5			* modification, are permitted provided that the following conditions are met:
6			*
7			* 1. Redistributions of source code must retain the above copyright
8			* notice, this list of conditions and the following disclaimer.
9			* 2. Redistributions in binary form must reproduce the above copyright
10			* notice, this list of conditions and the following disclaimer in the
11			* documentation and/or other materials provided with the distribution.
12			* 3. The name of the author may not be used to endorse or promote products
13			* derived from this software without specific prior written permission.
14			*
15			* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16			* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17			* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18			* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19			* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20			* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21			* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22			* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23			* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24			* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25			* SUCH DAMAGE.
26			*
27			*
28			* $Id: cpu_m88k_instr.c,v 1.5 2007/04/28 09:19:51 debug Exp $
29			*
30			* M88K instructions.
31			*
32			* Individual functions should keep track of cpu->n_translated_instrs.
33			* (If no instruction was executed, then it should be decreased. If, say, 4
34			* instructions were combined into one function and executed, then it should
35			* be increased by 3.)
36			*/
37
38
39			/*
40			* nop: Do nothing.
41			*/
42			X(nop)
43			{
44			}
45
46
47			/*
48			* br_samepage: Branch (to within the same translated page)
49			*
50			* arg[0] = pointer to new instr_call
51			*/
52			X(br_samepage)
53			{
54			cpu->cd.m88k.next_ic = (struct m88k_instr_call *) ic->arg[0];
55			}
56
57
58			/*
59			* br: Branch (to a different translated page)
60			*
61			* arg[0] = relative offset from start of page
62			*/
63			X(br)
64			{
65			cpu->pc = (uint32_t)((cpu->pc & 0xfffff000) + (int32_t)ic->arg[0]);
66
67			/* Find the new physical page and update the translation pointers: */
68			quick_pc_to_pointers(cpu);
69			}
70
71
72			/*
73			* or_imm: d = s1 \| imm
74			* or_r0_imm: d = imm (optimized case when s1 = r0)
75			*
76			* arg[0] = pointer to register d
77			* arg[1] = pointer to register s1
78			* arg[2] = imm
79			*/
80			X(or_imm)
81			{
82			reg(ic->arg[0]) = reg(ic->arg[1]) \| ic->arg[2];
83			}
84			X(or_r0_imm)
85			{
86			reg(ic->arg[0]) = ic->arg[2];
87			}
88
89
90			/*****************************************************************************/
91
92
93			X(end_of_page)
94			{
95			/* Update the PC: (offset 0, but on the next page) */
96			cpu->pc &= ~((M88K_IC_ENTRIES_PER_PAGE-1) <<
97			M88K_INSTR_ALIGNMENT_SHIFT);
98			cpu->pc += (M88K_IC_ENTRIES_PER_PAGE << M88K_INSTR_ALIGNMENT_SHIFT);
99
100			/* end_of_page doesn't count as an executed instruction: */
101			cpu->n_translated_instrs --;
102
103			/*
104			* Find the new physpage and update translation pointers.
105			*
106			* Note: This may cause an exception, if e.g. the new page is
107			* not accessible.
108			*/
109			quick_pc_to_pointers(cpu);
110
111			/* Simple jump to the next page (if we are lucky): */
112			if (cpu->delay_slot == NOT_DELAYED)
113			return;
114
115			/*
116			* If we were in a delay slot, and we got an exception while doing
117			* quick_pc_to_pointers, then return. The function which called
118			* end_of_page should handle this case.
119			*/
120			if (cpu->delay_slot == EXCEPTION_IN_DELAY_SLOT)
121			return;
122
123			/*
124			* Tricky situation; the delay slot is on the next virtual page.
125			* Calling to_be_translated will translate one instruction manually,
126			* execute it, and then discard it.
127			*/
128			/* fatal("[ end_of_page: delay slot across page boundary! ]\n"); */
129
130			instr(to_be_translated)(cpu, cpu->cd.m88k.next_ic);
131
132			/* The instruction in the delay slot has now executed. */
133			/* fatal("[ end_of_page: back from executing the delay slot, %i ]\n",
134			cpu->delay_slot); */
135
136			/* Find the physpage etc of the instruction in the delay slot
137			(or, if there was an exception, the exception handler): */
138			quick_pc_to_pointers(cpu);
139			}
140
141
142			X(end_of_page2)
143			{
144			/* Synchronize PC on the _second_ instruction on the next page: */
145			int low_pc = ((size_t)ic - (size_t)cpu->cd.m88k.cur_ic_page)
146			/ sizeof(struct m88k_instr_call);
147			cpu->pc &= ~((M88K_IC_ENTRIES_PER_PAGE-1)
148			<< M88K_INSTR_ALIGNMENT_SHIFT);
149			cpu->pc += (low_pc << M88K_INSTR_ALIGNMENT_SHIFT);
150
151			/* This doesn't count as an executed instruction. */
152			cpu->n_translated_instrs --;
153
154			quick_pc_to_pointers(cpu);
155
156			if (cpu->delay_slot == NOT_DELAYED)
157			return;
158
159			fatal("end_of_page2: fatal error, we're in a delay slot\n");
160			exit(1);
161			}
162
163
164			/*****************************************************************************/
165
166
167			/*
168			* m88k_instr_to_be_translated():
169			*
170			* Translate an instruction word into a m88k_instr_call. ic is filled in with
171			* valid data for the translated instruction, or a "nothing" instruction if
172			* there was a translation failure. The newly translated instruction is then
173			* executed.
174			*/
175			X(to_be_translated)
176			{
177			uint32_t addr, low_pc, iword;
178			unsigned char *page;
179			unsigned char ib[4];
180			uint32_t op26, op10, op11, d, s1, s2, w5, imm16;
181			int32_t d16, d26, simm16;
182			int offset, shift;
183			int in_crosspage_delayslot = 0;
184			void (samepage_function)(struct cpu , struct m88k_instr_call *);
185
186			/* Figure out the (virtual) address of the instruction: */
187			low_pc = ((size_t)ic - (size_t)cpu->cd.m88k.cur_ic_page)
188			/ sizeof(struct m88k_instr_call);
189
190			/* Special case for branch with delayslot on the next page: */
191			if (cpu->delay_slot == TO_BE_DELAYED && low_pc == 0) {
192			/* fatal("[ delay-slot translation across page "
193			"boundary ]\n"); */
194			in_crosspage_delayslot = 1;
195			}
196
197			addr = cpu->pc & ~((M88K_IC_ENTRIES_PER_PAGE-1)
198			<< M88K_INSTR_ALIGNMENT_SHIFT);
199			addr += (low_pc << M88K_INSTR_ALIGNMENT_SHIFT);
200			cpu->pc = (MODE_int_t)addr;
201			addr &= ~((1 << M88K_INSTR_ALIGNMENT_SHIFT) - 1);
202
203			/* Read the instruction word from memory: */
204			page = cpu->cd.m88k.host_load[(uint32_t)addr >> 12];
205
206			if (page != NULL) {
207			/* fatal("TRANSLATION HIT!\n"); */
208			memcpy(ib, page + (addr & 0xffc), sizeof(ib));
209			} else {
210			/* fatal("TRANSLATION MISS!\n"); */
211			if (!cpu->memory_rw(cpu, cpu->mem, addr, ib,
212			sizeof(ib), MEM_READ, CACHE_INSTRUCTION)) {
213			fatal("to_be_translated(): read failed: TODO\n");
214			goto bad;
215			}
216			}
217
218			iword = ((uint32_t )&ib[0]);
219			if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
220			iword = LE32_TO_HOST(iword);
221			else
222			iword = BE32_TO_HOST(iword);
223
224
225			#define DYNTRANS_TO_BE_TRANSLATED_HEAD
226			#include "cpu_dyntrans.c"
227			#undef DYNTRANS_TO_BE_TRANSLATED_HEAD
228
229
230			/*
231			* Translate the instruction:
232			*
233			* NOTE: _NEVER_ allow writes to the zero register; all instructions
234			* that use the zero register as their destination should be treated
235			* as NOPs, except those that access memory (they should use the
236			* scratch register instead).
237			*/
238
239			op26 = (iword >> 26) & 0x3f;
240			op11 = (iword >> 11) & 0x1f;
241			op10 = (iword >> 10) & 0x3f;
242			d = (iword >> 21) & 0x1f;
243			s1 = (iword >> 16) & 0x1f;
244			s2 = iword & 0x1f;
245			imm16 = iword & 0xffff;
246			simm16 = (int16_t) (iword & 0xffff);
247			w5 = (iword >> 5) & 0x1f;
248			d16 = ((int16_t) (iword & 0xffff)) * 4;
249			d26 = ((int32_t)((iword & 0x03ffffff) << 6)) >> 4;
250
251			switch (op26) {
252
253			case 0x16: /* or imm */
254			case 0x17: /* or.u imm */
255			shift = 0;
256			switch (op26) {
257			case 0x16: ic->f = instr(or_imm); break;
258			case 0x17: ic->f = instr(or_imm); shift = 16; break;
259			}
260
261			ic->arg[0] = (size_t) &cpu->cd.m88k.r[d];
262			ic->arg[1] = (size_t) &cpu->cd.m88k.r[s1];
263			ic->arg[2] = imm16 << shift;
264
265			/* Optimization for or d,r0,imm */
266			if (s1 == M88K_ZERO_REG && ic->f == instr(or_imm))
267			ic->f = instr(or_r0_imm);
268
269			if (d == M88K_ZERO_REG)
270			ic->f = instr(nop);
271			break;
272
273			case 0x30: /* br */
274			ic->f = instr(br);
275			samepage_function = instr(br_samepage);
276
277			offset = (addr & 0xffc) + d26;
278			if (offset >= 0 && offset <= 0xffc) {
279			/* Same page: */
280			ic->arg[0] = (size_t) ( cpu->cd.m88k.cur_ic_page +
281			(offset >> M88K_INSTR_ALIGNMENT_SHIFT) );
282			ic->f = samepage_function;
283			} else {
284			/* Different page: */
285			ic->arg[0] = offset;
286			}
287			break;
288
289			default:goto bad;
290			}
291
292
293			#define DYNTRANS_TO_BE_TRANSLATED_TAIL
294			#include "cpu_dyntrans.c"
295			#undef DYNTRANS_TO_BE_TRANSLATED_TAIL
296			}
297