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dpavlin |
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/* |
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* Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: cpu_m88k.c,v 1.7 2007/04/28 09:19:51 debug Exp $ |
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* |
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* M88K CPU emulation. |
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*/ |
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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#include <ctype.h> |
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#include "cpu.h" |
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#include "interrupt.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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#include "settings.h" |
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#include "symbol.h" |
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#define DYNTRANS_32 |
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#define DYNTRANS_DELAYSLOT |
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#include "tmp_m88k_head.c" |
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static char *memop[4] = { ".d", "", ".h", ".b" }; |
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void m88k_irq_interrupt_assert(struct interrupt *interrupt); |
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void m88k_irq_interrupt_deassert(struct interrupt *interrupt); |
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/* |
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* m88k_cpu_new(): |
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* |
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* Create a new M88K cpu object by filling the CPU struct. |
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* Return 1 on success, 0 if cpu_type_name isn't a valid M88K processor. |
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*/ |
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int m88k_cpu_new(struct cpu *cpu, struct memory *mem, |
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struct machine *machine, int cpu_id, char *cpu_type_name) |
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{ |
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int i, found; |
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struct m88k_cpu_type_def cpu_type_defs[] = M88K_CPU_TYPE_DEFS; |
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/* Scan the list for this cpu type: */ |
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i = 0; found = -1; |
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while (i >= 0 && cpu_type_defs[i].name != NULL) { |
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if (strcasecmp(cpu_type_defs[i].name, cpu_type_name) == 0) { |
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found = i; |
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break; |
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} |
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i++; |
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} |
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if (found == -1) |
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return 0; |
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cpu->run_instr = m88k_run_instr; |
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cpu->memory_rw = m88k_memory_rw; |
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cpu->update_translation_table = m88k_update_translation_table; |
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cpu->invalidate_translation_caches = |
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m88k_invalidate_translation_caches; |
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cpu->invalidate_code_translation = m88k_invalidate_code_translation; |
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/* cpu->translate_v2p = m88k_translate_v2p; */ |
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cpu->cd.m88k.cpu_type = cpu_type_defs[found]; |
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cpu->name = cpu->cd.m88k.cpu_type.name; |
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cpu->is_32bit = 1; |
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cpu->byte_order = EMUL_BIG_ENDIAN; |
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cpu->instruction_has_delayslot = m88k_cpu_instruction_has_delayslot; |
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/* Only show name and caches etc for CPU nr 0: */ |
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if (cpu_id == 0) { |
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debug("%s", cpu->name); |
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} |
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CPU_SETTINGS_ADD_REGISTER64("pc", cpu->pc); |
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for (i=0; i<N_M88K_REGS - 1; i++) { |
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char name[10]; |
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snprintf(name, sizeof(name), "r%i", i); |
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CPU_SETTINGS_ADD_REGISTER32(name, cpu->cd.m88k.r[i]); |
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} |
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/* Register the CPU interrupt pin: */ |
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{ |
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struct interrupt template; |
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char name[50]; |
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snprintf(name, sizeof(name), "%s.irq", cpu->path); |
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memset(&template, 0, sizeof(template)); |
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template.line = 0; |
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template.name = name; |
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template.extra = cpu; |
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template.interrupt_assert = m88k_irq_interrupt_assert; |
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template.interrupt_deassert = m88k_irq_interrupt_deassert; |
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interrupt_handler_register(&template); |
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} |
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return 1; |
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} |
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/* |
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* m88k_cpu_dumpinfo(): |
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*/ |
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void m88k_cpu_dumpinfo(struct cpu *cpu) |
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{ |
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/* struct m88k_cpu_type_def *ct = &cpu->cd.m88k.cpu_type; */ |
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debug(", %s-endian", |
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cpu->byte_order == EMUL_BIG_ENDIAN? "Big" : "Little"); |
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debug("\n"); |
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} |
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/* |
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* m88k_cpu_list_available_types(): |
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* |
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* Print a list of available M88K CPU types. |
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*/ |
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void m88k_cpu_list_available_types(void) |
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{ |
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int i, j; |
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struct m88k_cpu_type_def tdefs[] = M88K_CPU_TYPE_DEFS; |
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i = 0; |
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while (tdefs[i].name != NULL) { |
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debug("%s", tdefs[i].name); |
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for (j=13 - strlen(tdefs[i].name); j>0; j--) |
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debug(" "); |
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i++; |
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if ((i % 5) == 0 || tdefs[i].name == NULL) |
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debug("\n"); |
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} |
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} |
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/* |
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* m88k_cpu_instruction_has_delayslot(): |
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* |
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* Return 1 if an opcode is a branch, 0 otherwise. |
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*/ |
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int m88k_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib) |
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{ |
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uint32_t iword = *((uint32_t *)&ib[0]); |
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if (cpu->byte_order == EMUL_LITTLE_ENDIAN) |
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iword = LE32_TO_HOST(iword); |
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else |
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iword = BE32_TO_HOST(iword); |
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switch (iword >> 26) { |
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case 0x31: /* br.n */ |
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case 0x33: /* bsr.n */ |
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case 0x35: /* bb0.n */ |
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case 0x37: /* bb1.n */ |
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return 1; |
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/* TODO: jsr.n, jmp.n */ |
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} |
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return 0; |
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} |
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/* |
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* m88k_cpu_register_dump(): |
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* |
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* Dump cpu registers in a relatively readable format. |
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* |
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* gprs: set to non-zero to dump GPRs and some special-purpose registers. |
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* coprocs: set bit 0..3 to dump registers in coproc 0..3. |
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*/ |
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void m88k_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs) |
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{ |
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char *symbol; |
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uint64_t offset; |
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int i, x = cpu->cpu_id; |
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if (gprs) { |
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symbol = get_symbol_name(&cpu->machine->symbol_context, |
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cpu->pc, &offset); |
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debug("cpu%i: pc = 0x%08"PRIx32, x, (uint32_t)cpu->pc); |
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debug(" <%s>\n", symbol != NULL? symbol : " no symbol "); |
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for (i=0; i<N_M88K_REGS; i++) { |
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if ((i % 4) == 0) |
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debug("cpu%i:", x); |
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if (i == 0) |
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debug(" "); |
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else |
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debug(" r%-2i = 0x%08x", i, |
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(int)cpu->cd.m88k.r[i]); |
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if ((i % 4) == 3) |
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debug("\n"); |
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} |
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} |
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} |
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/* |
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* m88k_cpu_tlbdump(): |
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* |
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* Called from the debugger to dump the TLB in a readable format. |
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* x is the cpu number to dump, or -1 to dump all CPUs. |
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* |
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* If rawflag is nonzero, then the TLB contents isn't formated nicely, |
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* just dumped. |
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*/ |
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void m88k_cpu_tlbdump(struct machine *m, int x, int rawflag) |
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{ |
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} |
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/* |
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* m88k_irq_interrupt_assert(): |
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* m88k_irq_interrupt_deassert(): |
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*/ |
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void m88k_irq_interrupt_assert(struct interrupt *interrupt) |
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{ |
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struct cpu *cpu = (struct cpu *) interrupt->extra; |
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cpu->cd.m88k.irq_asserted = 1; |
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} |
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void m88k_irq_interrupt_deassert(struct interrupt *interrupt) |
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{ |
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struct cpu *cpu = (struct cpu *) interrupt->extra; |
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cpu->cd.m88k.irq_asserted = 0; |
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} |
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/* |
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* m88k_cpu_disassemble_instr(): |
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* |
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* Convert an instruction word into human readable format, for instruction |
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* tracing. |
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* |
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* If running is 1, cpu->pc should be the address of the instruction. |
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* |
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* If running is 0, things that depend on the runtime environment (eg. |
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* register contents) will not be shown, and addr will be used instead of |
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* cpu->pc for relative addresses. |
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*/ |
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int m88k_cpu_disassemble_instr(struct cpu *cpu, unsigned char *ib, |
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int running, uint64_t dumpaddr) |
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{ |
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uint32_t iw; |
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char *symbol, *mnem = NULL; |
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uint64_t offset; |
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uint32_t op26, op10, op11, d, s1, s2, w5, imm16; |
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int32_t d16, d26, simm16; |
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if (running) |
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dumpaddr = cpu->pc; |
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symbol = get_symbol_name(&cpu->machine->symbol_context, |
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dumpaddr, &offset); |
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if (symbol != NULL && offset == 0) |
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debug("<%s>\n", symbol); |
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if (cpu->machine->ncpus > 1 && running) |
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debug("cpu%i:\t", cpu->cpu_id); |
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debug("%08x: ", (int)dumpaddr); |
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if (cpu->byte_order == EMUL_LITTLE_ENDIAN) |
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iw = ib[0] + (ib[1]<<8) + (ib[2]<<16) + (ib[3]<<24); |
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else |
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iw = ib[3] + (ib[2]<<8) + (ib[1]<<16) + (ib[0]<<24); |
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debug("%08"PRIx32, (uint32_t) iw); |
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if (running && cpu->delay_slot) |
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debug(" (d)"); |
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debug("\t"); |
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op26 = (iw >> 26) & 0x3f; |
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op11 = (iw >> 11) & 0x1f; |
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op10 = (iw >> 10) & 0x3f; |
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d = (iw >> 21) & 0x1f; |
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s1 = (iw >> 16) & 0x1f; |
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s2 = iw & 0x1f; |
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imm16 = iw & 0xffff; |
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simm16 = (int16_t) (iw & 0xffff); |
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w5 = (iw >> 5) & 0x1f; |
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d16 = ((int16_t) (iw & 0xffff)) * 4; |
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d26 = ((int32_t)((iw & 0x03ffffff) << 6)) >> 4; |
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| 315 |
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switch (op26) { |
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| 317 |
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case 0x04: /* ld.d */ |
| 318 |
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case 0x05: /* ld */ |
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case 0x06: /* ld.h */ |
| 320 |
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case 0x07: /* ld.b */ |
| 321 |
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case 0x08: /* st.d */ |
| 322 |
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case 0x09: /* st */ |
| 323 |
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case 0x0a: /* st.h */ |
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case 0x0b: /* st.b */ |
| 325 |
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debug("%s%s\tr%i,r%i,%i", |
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op26 >= 0x08? "st" : "ld", |
| 327 |
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memop[op26 & 3], d, s1, imm16); |
| 328 |
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if (running) { |
| 329 |
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uint32_t tmpaddr = cpu->cd.m88k.r[s1] + imm16; |
| 330 |
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symbol = get_symbol_name(&cpu->machine->symbol_context, |
| 331 |
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tmpaddr, &offset); |
| 332 |
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if (symbol != NULL) |
| 333 |
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debug("\t; [<%s>]", symbol); |
| 334 |
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else |
| 335 |
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debug("\t; [0x%08"PRIx32"]", tmpaddr); |
| 336 |
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if (op26 >= 0x08) { |
| 337 |
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/* Store: */ |
| 338 |
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debug(" = "); |
| 339 |
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switch (op26 & 3) { |
| 340 |
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case 0: /* TODO: Endianness!!! */ |
| 341 |
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debug("0x%016"PRIx64, (uint64_t) |
| 342 |
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((((uint64_t) cpu->cd.m88k.r[d]) |
| 343 |
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<< 32) + ((uint64_t) |
| 344 |
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cpu->cd.m88k.r[d+1])) ); |
| 345 |
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break; |
| 346 |
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case 1: debug("0x%08"PRIx32, |
| 347 |
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(uint32_t) cpu->cd.m88k.r[d]); |
| 348 |
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break; |
| 349 |
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case 2: debug("0x%08"PRIx16, |
| 350 |
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(uint16_t) cpu->cd.m88k.r[d]); |
| 351 |
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break; |
| 352 |
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case 3: debug("0x%08"PRIx8, |
| 353 |
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(uint8_t) cpu->cd.m88k.r[d]); |
| 354 |
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break; |
| 355 |
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} |
| 356 |
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} else { |
| 357 |
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/* Load: */ |
| 358 |
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/* TODO */ |
| 359 |
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} |
| 360 |
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} else { |
| 361 |
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/* |
| 362 |
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* Not running, but the following instruction |
| 363 |
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|
* sequence is quite common: |
| 364 |
|
|
* |
| 365 |
|
|
* or.u rX,r0,A |
| 366 |
|
|
* st_or_st rY,rX,B |
| 367 |
|
|
*/ |
| 368 |
|
|
|
| 369 |
|
|
/* Try loading the instruction before the |
| 370 |
|
|
current one. */ |
| 371 |
|
|
uint32_t iw2 = 0; |
| 372 |
|
|
cpu->memory_rw(cpu, cpu->mem, |
| 373 |
|
|
dumpaddr - sizeof(uint32_t), (unsigned char *)&iw2, |
| 374 |
|
|
sizeof(iw2), MEM_READ, CACHE_INSTRUCTION |
| 375 |
|
|
| NO_EXCEPTIONS); |
| 376 |
|
|
if (cpu->byte_order == EMUL_LITTLE_ENDIAN) |
| 377 |
|
|
iw2 = LE32_TO_HOST(iw2); |
| 378 |
|
|
else |
| 379 |
|
|
iw2 = BE32_TO_HOST(iw2); |
| 380 |
|
|
if ((iw2 >> 26) == 0x17 && /* or.u */ |
| 381 |
|
|
((iw2 >> 21) & 0x1f) == s1) { |
| 382 |
|
|
uint32_t tmpaddr = (iw2 << 16) + imm16; |
| 383 |
|
|
symbol = get_symbol_name( |
| 384 |
|
|
&cpu->machine->symbol_context, |
| 385 |
|
|
tmpaddr, &offset); |
| 386 |
|
|
if (symbol != NULL) |
| 387 |
|
|
debug("\t; [<%s>]", symbol); |
| 388 |
|
|
else |
| 389 |
|
|
debug("\t; [0x%08"PRIx32"]", tmpaddr); |
| 390 |
|
|
} |
| 391 |
|
|
} |
| 392 |
|
|
debug("\n"); |
| 393 |
|
|
break; |
| 394 |
|
|
|
| 395 |
|
|
case 0x10: /* and */ |
| 396 |
|
|
case 0x11: /* and.u */ |
| 397 |
|
|
case 0x12: /* mask */ |
| 398 |
|
|
case 0x13: /* mask.u */ |
| 399 |
|
|
case 0x14: /* xor */ |
| 400 |
|
|
case 0x15: /* xor.u */ |
| 401 |
|
|
case 0x16: /* or */ |
| 402 |
|
|
case 0x17: /* or.u */ |
| 403 |
|
|
switch (op26) { |
| 404 |
|
|
case 0x10: |
| 405 |
|
|
case 0x11: mnem = "and"; break; |
| 406 |
|
|
case 0x12: |
| 407 |
|
|
case 0x13: mnem = "mask"; break; |
| 408 |
|
|
case 0x14: |
| 409 |
|
|
case 0x15: mnem = "xor"; break; |
| 410 |
|
|
case 0x16: |
| 411 |
|
|
case 0x17: mnem = "or"; break; |
| 412 |
|
|
} |
| 413 |
|
|
debug("%s%s\t", mnem, op26 & 1? ".u" : ""); |
| 414 |
|
|
debug("r%i,r%i,0x%x\n", d, s1, imm16); |
| 415 |
|
|
break; |
| 416 |
|
|
|
| 417 |
|
|
case 0x18: /* addu */ |
| 418 |
|
|
case 0x19: /* subu */ |
| 419 |
|
|
case 0x1a: /* divu */ |
| 420 |
|
|
case 0x1b: /* mulu */ |
| 421 |
|
|
switch (op26) { |
| 422 |
|
|
case 0x18: mnem = "addu"; break; |
| 423 |
|
|
case 0x19: mnem = "subu"; break; |
| 424 |
|
|
case 0x1a: mnem = "divu"; break; |
| 425 |
|
|
case 0x1b: mnem = "mulu"; break; |
| 426 |
|
|
} |
| 427 |
|
|
debug("%s\tr%i,r%i,%i\n", mnem, d, s1, imm16); |
| 428 |
|
|
break; |
| 429 |
|
|
|
| 430 |
|
|
case 0x1c: /* add */ |
| 431 |
|
|
case 0x1d: /* sub */ |
| 432 |
|
|
case 0x1e: /* div */ |
| 433 |
|
|
case 0x1f: /* cmp */ |
| 434 |
|
|
switch (op26) { |
| 435 |
|
|
case 0x1c: mnem = "add"; break; |
| 436 |
|
|
case 0x1d: mnem = "sub"; break; |
| 437 |
|
|
case 0x1e: mnem = "div"; break; |
| 438 |
|
|
case 0x1f: mnem = "cmp"; break; |
| 439 |
|
|
} |
| 440 |
|
|
debug("%s\tr%i,r%i,%i\n", mnem, d, s1, simm16); |
| 441 |
|
|
break; |
| 442 |
|
|
|
| 443 |
|
|
case 0x30: |
| 444 |
|
|
case 0x31: |
| 445 |
|
|
case 0x32: |
| 446 |
|
|
case 0x33: |
| 447 |
|
|
debug("b%sr%s\t", |
| 448 |
|
|
op26 >= 0x32? "s" : "", |
| 449 |
|
|
op26 & 1? ".n" : ""); |
| 450 |
|
|
debug("0x%08"PRIx32, (uint32_t) (dumpaddr + d26)); |
| 451 |
|
|
symbol = get_symbol_name(&cpu->machine->symbol_context, |
| 452 |
|
|
dumpaddr + d26, &offset); |
| 453 |
|
|
if (symbol != NULL) |
| 454 |
|
|
debug("\t; <%s>", symbol); |
| 455 |
|
|
debug("\n"); |
| 456 |
|
|
break; |
| 457 |
|
|
|
| 458 |
|
|
case 0x34: /* bb0 */ |
| 459 |
|
|
case 0x35: /* bb0.n */ |
| 460 |
|
|
case 0x36: /* bb1 */ |
| 461 |
|
|
case 0x37: /* bb1.n */ |
| 462 |
|
|
debug("bb%s%s\t", |
| 463 |
|
|
op26 >= 0x36? "1" : "0", |
| 464 |
|
|
op26 & 1? ".n" : ""); |
| 465 |
|
|
debug("%i,r%i,0x%08"PRIx32, d, s1, (uint32_t) (dumpaddr + d16)); |
| 466 |
|
|
symbol = get_symbol_name(&cpu->machine->symbol_context, |
| 467 |
|
|
dumpaddr + d16, &offset); |
| 468 |
|
|
if (symbol != NULL) |
| 469 |
|
|
debug("\t; <%s>", symbol); |
| 470 |
|
|
debug("\n"); |
| 471 |
|
|
break; |
| 472 |
|
|
|
| 473 |
|
|
case 0x3d: |
| 474 |
|
|
if ((iw & 0x03fff3e0) == 0x0000c000) { |
| 475 |
|
|
debug("%s%s\t(r%i)\n", |
| 476 |
|
|
op11 & 1? "jsr" : "jmp", |
| 477 |
|
|
iw & 0x400? ".n" : "", |
| 478 |
|
|
s2); |
| 479 |
|
|
if (running) { |
| 480 |
|
|
uint32_t tmpaddr = cpu->cd.m88k.r[s2]; |
| 481 |
|
|
symbol = get_symbol_name(&cpu->machine-> |
| 482 |
|
|
symbol_context, tmpaddr, &offset); |
| 483 |
|
|
debug("\t; "); |
| 484 |
|
|
if (symbol != NULL) |
| 485 |
|
|
debug("<%s>", symbol); |
| 486 |
|
|
else |
| 487 |
|
|
debug("0x%08"PRIx32, tmpaddr); |
| 488 |
|
|
} |
| 489 |
|
|
} else if ((iw & 0x0000ffe0) == 0x00000000) { |
| 490 |
|
|
debug("xmem\tr%i,r%i,r%i\n", d, s1, s2); |
| 491 |
|
|
} else { |
| 492 |
|
|
debug("UNIMPLEMENTED 0x3d\n"); |
| 493 |
|
|
} |
| 494 |
|
|
break; |
| 495 |
|
|
|
| 496 |
|
|
default:debug("UNIMPLEMENTED\n"); |
| 497 |
|
|
} |
| 498 |
|
|
|
| 499 |
|
|
return sizeof(uint32_t); |
| 500 |
|
|
} |
| 501 |
|
|
|
| 502 |
|
|
|
| 503 |
|
|
#include "tmp_m88k_tail.c" |
| 504 |
|
|
|
| 505 |
|
|
|
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| 
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