/[gxemul]/trunk/src/cpus/cpu_m68k.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Contents of /trunk/src/cpus/cpu_m68k.c

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Revision 24 - (show annotations)
Mon Oct 8 16:19:56 2007 UTC (13 years, 3 months ago) by dpavlin
File MIME type: text/plain
File size: 7752 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1256 2006/06/23 20:43:44 debug Exp $
20060219	Various minor updates. Removing the old MIPS16 skeleton code,
		because it will need to be rewritten for dyntrans anyway.
20060220-22	Removing the non-working dyntrans backend support.
		Continuing on the 64-bit dyntrans virtual memory generalization.
20060223	More work on the 64-bit vm generalization.
20060225	Beginning on MIPS dyntrans load/store instructions.
		Minor PPC updates (64-bit load/store, etc).
		Fixes for the variable-instruction-length framework, some
		minor AVR updates (a simple Hello World program works!).
		Beginning on a skeleton for automatically generating documen-
		tation (for devices etc.).
20060226	PPC updates (adding some more 64-bit instructions, etc).
		AVR updates (more instructions).
		FINALLY found and fixed the zs bug, making NetBSD/macppc
		accept the serial console.
20060301	Adding more AVR instructions.
20060304	Continuing on AVR-related stuff. Beginning on a framework for
		cycle-accurate device emulation. Adding an experimental "PAL
		TV" device (just a dummy so far).
20060305	Adding more AVR instructions.
		Adding a dummy epcom serial controller (for TS7200 emulation).
20060310	Removing the emul() command from configuration files, so only
		net() and machine() are supported.
		Minor progress on the MIPS dyntrans rewrite.
20060311	Continuing on the MIPS dyntrans rewrite (adding more
		instructions, etc).
20060315	Adding more instructions (sllv, srav, srlv, bgtz[l], blez[l],
		beql, bnel, slti[u], various loads and stores).
20060316	Removing the ALWAYS_SIGNEXTEND_32 option, since it was rarely
		used.
		Adding more MIPS dyntrans instructions, and fixing bugs.
20060318	Implementing fast loads/stores for MIPS dyntrans (big/little
		endian, 32-bit and 64-bit modes).
20060320	Making MIPS dyntrans the default configure option; use
		"--enable-oldmips" to use the old bintrans system.
		Adding MIPS dyntrans dmult[u]; minor updates.
20060322	Continuing... adding some more instructions.
		Adding a simple skeleton for demangling C++ "_ZN" symbols.
20060323	Moving src/debugger.c into a new directory (src/debugger/).
20060324	Fixing the hack used to load PPC ELFs (useful for relocated
		Linux/ppc kernels), and adding a dummy G3 machine mode.
20060325-26	Beginning to experiment with GDB remote serial protocol
		connections; adding a -G command line option for selecting
		which TCP port to listen to.
20060330	Beginning a major cleanup to replace things like "0x%016llx"
		with more correct "0x%016"PRIx64, etc.
		Continuing on the GDB remote serial protocol support.
20060331	More cleanup, and some minor GDB remote progress.
20060402	Adding a hack to the configure script, to allow compilation
		on systems that lack PRIx64 etc.
20060406	Removing the temporary FreeBSD/arm hack in dev_ns16550.c and
		replacing it with a better fix from Olivier Houchard.
20060407	A remote debugger (gdb or ddd) can now start and stop the
		emulator using the GDB remote serial protocol, and registers
		and memory can be read. MIPS only for now.
20060408	More GDB progress: single-stepping also works, and also adding
		support for ARM, PowerPC, and Alpha targets.
		Continuing on the delay-slot-across-page-boundary issue.
20060412	Minor update: beginning to add support for the SPARC target
		to the remote GDB functionality.
20060414	Various MIPS updates: adding more instructions for dyntrans
		(eret, add), and making some exceptions work. Fixing a bug
		in dmult[u].
		Implementing the first SPARC instructions (sethi, or).
20060415	Adding "magic trap" instructions so that PROM calls can be
		software emulated in MIPS dyntrans.
		Adding more MIPS dyntrans instructions (ddiv, dadd) and
		fixing another bug in dmult.
20060416	More MIPS dyntrans progress: adding [d]addi, movn, movz, dsllv,
		rfi, an ugly hack for supporting R2000/R3000 style faked caches,
		preliminary interrupt support, and various other updates and
		bugfixes.
20060417	Adding more SPARC instructions (add, sub, sll[x], sra[x],
		srl[x]), and useful SPARC header definitions.
		Adding the first (trivial) x86/AMD64 dyntrans instructions (nop,
		cli/sti, stc/clc, std/cld, simple mov, inc ax). Various other
		x86 updates related to variable instruction length stuff.
		Adding unaligned loads/stores to the MIPS dyntrans mode (but
		still using the pre-dyntrans (slow) imlementation).
20060419	Fixing a MIPS dyntrans exception-in-delay-slot bug.
		Removing the old "show opcode statistics" functionality, since
		it wasn't really useful and isn't implemented for dyntrans.
		Single-stepping (or running with instruction trace) now looks
		ok with dyntrans with delay-slot architectures.
20060420	Minor hacks (removing the -B command line option when compiled
		for non-bintrans, and some other very minor updates).
		Adding (slow) MIPS dyntrans load-linked/store-conditional.
20060422	Applying fixes for bugs discovered by Nils Weller's nwcc
		(static DEC memmap => now per machine, and adding an extern
		keyword in cpu_arm_instr.c).
		Finally found one of the MIPS dyntrans bugs that I've been
		looking for (copy/paste spelling error BIG vs LITTLE endian in
		cpu_mips_instr_loadstore.c for 16-bit fast stores).
		FINALLY found the major MIPS dyntrans bug: slti vs sltiu
		signed/unsigned code in cpu_mips_instr.c. :-)
		Adding more MIPS dyntrans instructions (lwc1, swc1, bgezal[l],
		ctc1, tlt[u], tge[u], tne, beginning on rdhwr).
		NetBSD/hpcmips can now reach userland when using dyntrans :-)
		Adding some more x86 dyntrans instructions.
		Finally removed the old Alpha-specific virtual memory code,
		and replaced it with the generic 64-bit version.
		Beginning to add disassembly support for SPECIAL3 MIPS opcodes.
20060423	Continuing on the delay-slot-across-page-boundary issue;
		adding an end_of_page2 ic slot (like I had planned before, but
		had removed for some reason).
		Adding a quick-and-dirty fallback to legacy coprocessor 1
		code (i.e. skipping dyntrans implementation for now).
		NetBSD/hpcmips and NetBSD/pmax (when running on an emulated
		R4400) can now be installed and run. :-)  (Many bugs left
		to fix, though.)
		Adding more MIPS dyntrans instructions: madd[u], msub[u].
		Cleaning up the SPECIAL2 vs R5900/TX79/C790 "MMI" opcode
		maps somewhat (disassembly and dyntrans instruction decoding).
20060424	Adding an isa_revision field to mips_cpu_types.h, and making
		sure that SPECIAL3 opcodes cause Reserved Instruction
		exceptions on MIPS32/64 revisions lower than 2.
		Adding the SPARC 'ba', 'call', 'jmpl/retl', 'and', and 'xor'
		instructions.
20060425	Removing the -m command line option ("run at most x 
		instructions") and -T ("single_step_on_bad_addr"), because
		they never worked correctly with dyntrans anyway.
		Freshening up the man page.
20060428	Adding more MIPS dyntrans instructions: bltzal[l], idle.
		Enabling MIPS dyntrans compare interrupts.
20060429	FINALLY found the weird dyntrans bug, causing NetBSD etc. to
		behave strangely: some floating point code (conditional
		coprocessor branches) could not be reused from the old
		non-dyntrans code. The "quick-and-dirty fallback" only appeared
		to work. Fixing by implementing bc1* for MIPS dyntrans.
		More MIPS instructions: [d]sub, sdc1, ldc1, dmtc1, dmfc1, cfc0.
		Freshening up MIPS floating point disassembly appearance.
20060430	Continuing on C790/R5900/TX79 disassembly; implementing 128-bit
		"por" and "pextlw".
20060504	Disabling -u (userland emulation) unless compiled as unstable
		development version.
		Beginning on freshening up the testmachine include files,
		to make it easier to reuse those files (placing them in
		src/include/testmachine/), and beginning on a set of "demos"
		or "tutorials" for the testmachine functionality.
		Minor updates to the MIPS GDB remote protocol stub.
		Refreshing doc/experiments.html and gdb_remote.html.
		Enabling Alpha emulation in the stable release configuration,
		even though no guest OSes for Alpha can run yet.
20060505	Adding a generic 'settings' object, which will contain
		references to settable variables (which will later be possible
		to access using the debugger).
20060506	Updating dev_disk and corresponding demo/documentation (and
		switching from SCSI to IDE disk types, so it actually works
		with current test machines :-).
20060510	Adding a -D_LARGEFILE_SOURCE hack for 64-bit Linux hosts,
		so that fseeko() doesn't give a warning.
		Updating the section about how dyntrans works (the "runnable
		IR") in doc/intro.html.
		Instruction updates (some x64=1 checks, some more R5900
		dyntrans stuff: better mul/mult separation from MIPS32/64,
		adding ei and di).
		Updating MIPS cpuregs.h to a newer one (from NetBSD).
		Adding more MIPS dyntrans instructions: deret, ehb.
20060514	Adding disassembly and beginning implementation of SPARC wr
		and wrpr instructions.
20060515	Adding a SUN SPARC machine mode, with dummy SS20 and Ultra1
		machines. Adding the 32-bit "rd psr" instruction.
20060517	Disassembly support for the general SPARC rd instruction.
		Partial implementation of the cmp (subcc) instruction.
		Some other minor updates (making sure that R5900 processors
		start up with the EIE bit enabled, otherwise Linux/playstation2
		receives no interrupts).
20060519	Minor MIPS updates/cleanups.
20060521	Moving the MeshCube machine into evbmips; this seems to work
		reasonably well with a snapshot of a NetBSD MeshCube kernel.
		Cleanup/fix of MIPS config0 register initialization.
20060529	Minor MIPS fixes, including a sign-extension fix to the
		unaligned load/store code, which makes NetBSD/pmax on R3000
		work better with dyntrans. (Ultrix and Linux/DECstation still
		don't work, though.)
20060530	Minor updates to the Alpha machine mode: adding an AlphaBook
		mode, an LCA bus (forwarding accesses to an ISA bus), etc.
20060531	Applying a bugfix for the MIPS dyntrans sc[d] instruction from
		Ondrej Palkovsky. (Many thanks.)
20060601	Minifix to allow ARM immediate msr instruction to not give
		an error for some valid values.
		More Alpha updates.
20060602	Some minor Alpha updates.
20060603	Adding the Alpha cmpbge instruction. NetBSD/alpha prints its
		first boot messages :-) on an emulated Alphabook 1.
20060612	Minor updates; adding a dev_ether.h include file for the
		testmachine ether device. Continuing the hunt for the dyntrans
		bug which makes Linux and Ultrix on DECstation behave
		strangely... FINALLY found it! It seems to be related to
		invalidation of the translation cache, on tlbw{r,i}. There
		also seems to be some remaining interrupt-related problems.
20060614	Correcting the implementation of ldc1/sdc1 for MIPS dyntrans
		(so that it uses 16 32-bit registers if the FR bit in the
		status register is not set).
20060616	REMOVING BINTRANS COMPLETELY!
		Removing the old MIPS interpretation mode.
		Removing the MFHILO_DELAY and instruction delay stuff, because
		they wouldn't work with dyntrans anyway.
20060617	Some documentation updates (adding "NetBSD-archive" to some
		URLs, and new Debian/DECstation installation screenshots).
		Removing the "tracenull" and "enable-caches" configure options.
		Improving MIPS dyntrans performance somewhat (only invalidate
		translations if necessary, on writes to the entryhi register,
		instead of doing it for all cop0 writes).
20060618	More cleanup after the removal of the old MIPS emulation.
		Trying to fix the MIPS dyntrans performance bugs/bottlenecks;
		only semi-successful so far (for R3000).
20060620	Minor update to allow clean compilation again on Tru64/Alpha.
20060622	MIPS cleanup and fixes (removing the pc_last stuff, which
		doesn't make sense with dyntrans anyway, and fixing a cross-
		page-delay-slot-with-exception case in end_of_page).
		Removing the old max_random_cycles_per_chunk stuff, and the
		concept of cycles vs instructions for MIPS emulation.
		FINALLY found and fixed the bug which caused NetBSD/pmax
		clocks to behave strangely (it was a load to the zero register,
		which was treated as a NOP; now it is treated as a load to a
		dummy scratch register).
20060623	Increasing the dyntrans chunk size back to
		N_SAFE_DYNTRANS_LIMIT, instead of N_SAFE_DYNTRANS_LIMIT/2.
		Preparing for a quick release, even though there are known
		bugs, and performance for non-R3000 MIPS emulation is very
		poor. :-/
		Reverting to half the dyntrans chunk size again, because
		NetBSD/cats seemed less stable with full size chunks. :(
		NetBSD/sgimips 3.0 can now run :-)  (With release 0.3.8, only
		NetBSD/sgimips 2.1 worked, not 3.0.)

==============  RELEASE 0.4.0  ==============


1 /*
2 * Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: cpu_m68k.c,v 1.10 2006/06/16 18:31:25 debug Exp $
29 *
30 * Motorola 68K CPU emulation.
31 */
32
33 #include <stdio.h>
34 #include <stdlib.h>
35 #include <string.h>
36 #include <ctype.h>
37
38 #include "cpu.h"
39 #include "machine.h"
40 #include "memory.h"
41 #include "misc.h"
42 #include "symbol.h"
43
44
45 #define DYNTRANS_32
46 #define DYNTRANS_VARIABLE_INSTRUCTION_LENGTH
47 #include "tmp_m68k_head.c"
48
49
50 static char *m68k_aname[] = { "a0", "a1", "a2", "a3", "a4", "a5", "fp", "a7" };
51
52
53 /*
54 * m68k_cpu_new():
55 *
56 * Create a new M68K cpu object.
57 *
58 * Returns 1 on success, 0 if there was no matching M68K processor with
59 * this cpu_type_name.
60 */
61 int m68k_cpu_new(struct cpu *cpu, struct memory *mem, struct machine *machine,
62 int cpu_id, char *cpu_type_name)
63 {
64 if (strcasecmp(cpu_type_name, "68020") != 0)
65 return 0;
66
67 cpu->memory_rw = m68k_memory_rw;
68 cpu->update_translation_table = m68k_update_translation_table;
69 cpu->invalidate_translation_caches =
70 m68k_invalidate_translation_caches;
71 cpu->invalidate_code_translation = m68k_invalidate_code_translation;
72 cpu->is_32bit = 1;
73
74 cpu->byte_order = EMUL_BIG_ENDIAN;
75
76 /* Only show name and caches etc for CPU nr 0 (in SMP machines): */
77 if (cpu_id == 0) {
78 debug("%s", cpu->name);
79 }
80
81 return 1;
82 }
83
84
85 /*
86 * m68k_cpu_list_available_types():
87 *
88 * Print a list of available M68K CPU types.
89 */
90 void m68k_cpu_list_available_types(void)
91 {
92 debug("68020\n");
93 /* TODO */
94 }
95
96
97 /*
98 * m68k_cpu_dumpinfo():
99 */
100 void m68k_cpu_dumpinfo(struct cpu *cpu)
101 {
102 /* TODO */
103 debug("\n");
104 }
105
106
107 /*
108 * m68k_cpu_register_dump():
109 *
110 * Dump cpu registers in a relatively readable format.
111 *
112 * gprs: set to non-zero to dump GPRs and some special-purpose registers.
113 * coprocs: set bit 0..3 to dump registers in coproc 0..3.
114 */
115 void m68k_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs)
116 {
117 char *symbol;
118 uint64_t offset;
119 int x = cpu->cpu_id;
120
121 if (gprs) {
122 /* Special registers (pc, ...) first: */
123 symbol = get_symbol_name(&cpu->machine->symbol_context,
124 cpu->pc, &offset);
125
126 debug("cpu%i: pc = 0x%08x", x, (int)cpu->pc);
127 debug(" <%s>\n", symbol != NULL? symbol : " no symbol ");
128 }
129 }
130
131
132 /*
133 * m68k_cpu_register_match():
134 */
135 void m68k_cpu_register_match(struct machine *m, char *name,
136 int writeflag, uint64_t *valuep, int *match_register)
137 {
138 int cpunr = 0;
139
140 /* CPU number: */
141
142 /* TODO */
143
144 /* Register name: */
145 if (strcasecmp(name, "pc") == 0) {
146 if (writeflag) {
147 m->cpus[cpunr]->pc = *valuep;
148 } else
149 *valuep = m->cpus[cpunr]->pc;
150 *match_register = 1;
151 }
152 }
153
154
155 /*
156 * m68k_cpu_tlbdump():
157 *
158 * Called from the debugger to dump the TLB in a readable format.
159 * x is the cpu number to dump, or -1 to dump all CPUs.
160 *
161 * If rawflag is nonzero, then the TLB contents isn't formated nicely,
162 * just dumped.
163 */
164 void m68k_cpu_tlbdump(struct machine *m, int x, int rawflag)
165 {
166 }
167
168
169 /*
170 * m68k_cpu_gdb_stub():
171 *
172 * Execute a "remote GDB" command. Returns a newly allocated response string
173 * on success, NULL on failure.
174 */
175 char *m68k_cpu_gdb_stub(struct cpu *cpu, char *cmd)
176 {
177 fatal("m68k_cpu_gdb_stub(): TODO\n");
178 return NULL;
179 }
180
181
182 /*
183 * m68k_cpu_interrupt():
184 */
185 int m68k_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr)
186 {
187 fatal("m68k_cpu_interrupt(): TODO\n");
188 return 0;
189 }
190
191
192 /*
193 * m68k_cpu_interrupt_ack():
194 */
195 int m68k_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr)
196 {
197 /* fatal("m68k_cpu_interrupt_ack(): TODO\n"); */
198 return 0;
199 }
200
201
202 /* Helper functions: */
203 static void print_two(unsigned char *instr, int *len)
204 { debug(" %02x%02x", instr[*len], instr[*len+1]); (*len) += 2; }
205 static void print_spaces(int len) { int i; debug(" "); for (i=0; i<16-len/2*5;
206 i++) debug(" "); }
207
208
209 /*
210 * m68k_cpu_disassemble_instr():
211 *
212 * Convert an instruction word into human readable format, for instruction
213 * tracing.
214 *
215 * If running is 1, cpu->pc should be the address of the instruction.
216 *
217 * If running is 0, things that depend on the runtime environment (eg.
218 * register contents) will not be shown, and addr will be used instead of
219 * cpu->pc for relative addresses.
220 */
221 int m68k_cpu_disassemble_instr(struct cpu *cpu, unsigned char *ib,
222 int running, uint64_t dumpaddr)
223 {
224 uint64_t offset;
225 int len = 0;
226 char *symbol;
227
228 if (running)
229 dumpaddr = cpu->pc;
230
231 symbol = get_symbol_name(&cpu->machine->symbol_context,
232 dumpaddr, &offset);
233 if (symbol != NULL && offset==0)
234 debug("<%s>\n", symbol);
235
236 if (cpu->machine->ncpus > 1 && running)
237 debug("cpu%i: ", cpu->cpu_id);
238
239 debug("0x%08x: ", (int)dumpaddr);
240
241 print_two(ib, &len);
242
243 if (ib[0] == 0x48) {
244 if (ib[1] >= 0x40 && ib[1] <= 0x47) {
245 print_spaces(len);
246 debug("swap\td%i\n", ib[1] & 7);
247 } else if (ib[1] >= 0x48 && ib[1] <= 0x4f) {
248 print_spaces(len);
249 debug("bkpt\t#%i\n", ib[1] & 7);
250 } else {
251 print_spaces(len);
252 debug("UNIMPLEMENTED 0x%02x%02x\n", ib[0], ib[1]);
253 }
254 } else if (ib[0] == 0x4a) {
255 if (ib[1] == 0xfc) {
256 print_spaces(len);
257 debug("illegal\n");
258 } else {
259 print_spaces(len);
260 debug("UNIMPLEMENTED 0x%02x%02x\n", ib[0], ib[1]);
261 }
262 } else if (ib[0] == 0x4e) {
263 if (ib[1] >= 0x40 && ib[1] <= 0x4f) {
264 print_spaces(len);
265 debug("trap\t#%i\n", ib[1] & 15);
266 } else if (ib[1] >= 0x50 && ib[1] <= 0x57) {
267 print_two(ib, &len);
268 print_spaces(len);
269 debug("linkw\t%%%s,#%i\n", m68k_aname[ib[1] & 7],
270 ((ib[2] << 8) + ib[3]));
271 } else if (ib[1] >= 0x58 && ib[1] <= 0x5f) {
272 print_spaces(len);
273 debug("unlk\t%%%s\n", m68k_aname[ib[1] & 7]);
274 } else if (ib[1] == 0x70) {
275 print_spaces(len);
276 debug("reset\n");
277 } else if (ib[1] == 0x71) {
278 print_spaces(len);
279 debug("nop\n");
280 } else if (ib[1] == 0x72) {
281 print_two(ib, &len);
282 print_spaces(len);
283 debug("stop\t#0x%04x\n", ((ib[2] << 8) + ib[3]));
284 } else if (ib[1] == 0x73) {
285 print_spaces(len);
286 debug("rte\n");
287 } else if (ib[1] == 0x74) {
288 print_two(ib, &len);
289 print_spaces(len);
290 debug("rtd\t#0x%04x\n", ((ib[2] << 8) + ib[3]));
291 } else if (ib[1] == 0x75) {
292 print_spaces(len);
293 debug("rts\n");
294 } else {
295 print_spaces(len);
296 debug("UNIMPLEMENTED 0x%02x%02x\n", ib[0], ib[1]);
297 }
298 } else {
299 print_spaces(len);
300 debug("UNIMPLEMENTED 0x%02x%02x\n", ib[0], ib[1]);
301 }
302
303 return len;
304 }
305
306
307 #include "tmp_m68k_tail.c"
308

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