/[gxemul]/trunk/src/cpus/cpu_m68k.c
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Annotation of /trunk/src/cpus/cpu_m68k.c

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Revision 34 - (hide annotations)
Mon Oct 8 16:21:17 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 8139 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1480 2007/02/19 01:34:42 debug Exp $
20061029	Changing usleep(1) calls in the debugger to usleep(10000)
20061107	Adding a new disk image option (-d o...) which sets the ISO9660
		filesystem base offset; also making some other hacks to allow
		NetBSD/dreamcast and homebrew demos/games to boot directly
		from a filesystem image.
		Moving Dreamcast-specific stuff in the documentation to its
		own page (dreamcast.html).
		Adding a border to the Dreamcast PVR framebuffer.
20061108	Adding a -T command line option (again?), for halting the
		emulator on unimplemented memory accesses.
20061109	Continuing on various SH4 and Dreamcast related things.
		The emulator should now halt on more unimplemented device
		accesses, instead of just printing a warning, forcing me to
		actually implement missing stuff :)
20061111	Continuing on SH4 and Dreamcast stuff.
		Adding a bogus Landisk (SH4) machine mode.
20061112	Implementing some parts of the Dreamcast GDROM device. With
		some ugly hacks, NetBSD can (barely) mount an ISO image.
20061113	NetBSD/dreamcast now starts booting from the Live CD image,
		but crashes randomly quite early on in the boot process.
20061122	Beginning on a skeleton interrupt.h and interrupt.c for the
		new interrupt subsystem.
20061124	Continuing on the new interrupt system; taking the first steps
		to attempt to connect CPUs (SuperH and MIPS) and devices
		(dev_cons and SH4 timer interrupts) to it. Many things will
		probably break from now on.
20061125	Converting dev_ns16550, dev_8253 to the new interrupt system.
		Attempting to begin to convert the ISA bus.
20061130	Incorporating a patch from Brian Foley for the configure
		script, which checks for X11 libs in /usr/X11R6/lib64 (which
		is used on some Linux systems).
20061227	Adding a note in the man page about booting from Dreamcast
		CDROM images (i.e. that no external kernel is needed).
20061229	Continuing on the interrupt system rewrite: beginning to
		convert more devices, adding abort() calls for legacy interrupt
		system calls so that everything now _has_ to be rewritten!
		Almost all machine modes are now completely broken.
20061230	More progress on removing old interrupt code, mostly related
		to the ISA bus + devices, the LCA bus (on AlphaBook1), and
		the Footbridge bus (for CATS). And some minor PCI stuff.
		Connecting the ARM cpu to the new interrupt system.
		The CATS, NetWinder, and QEMU_MIPS machine modes now work with
		the new interrupt system :)
20061231	Connecting PowerPC CPUs to the new interrupt system.
		Making PReP machines (IBM 6050) work again.
		Beginning to convert the GT PCI controller (for e.g. Malta
		and Cobalt emulation). Some things work, but not everything.
		Updating Copyright notices for 2007.
20070101	Converting dev_kn02 from legacy style to devinit; the 3max
		machine mode now works with the new interrupt system :-]
20070105	Beginning to convert the SGI O2 machine to the new interrupt
		system; finally converting O2 (IP32) devices to devinit, etc.
20070106	Continuing on the interrupt system redesign/rewrite; KN01
		(PMAX), KN230, and Dreamcast ASIC interrupts should work again,
		moving out stuff from machine.h and devices.h into the
		corresponding devices, beginning the rewrite of i80321
		interrupts, etc.
20070107	Beginning on the rewrite of Eagle interrupt stuff (PReP, etc).
20070117	Beginning the rewrite of Algor (V3) interrupts (finally
		changing dev_v3 into devinit style).
20070118	Removing the "bus" registry concept from machine.h, because
		it was practically meaningless.
		Continuing on the rewrite of Algor V3 ISA interrupts.
20070121	More work on Algor interrupts; they are now working again,
		well enough to run NetBSD/algor. :-)
20070122	Converting VR41xx (HPCmips) interrupts. NetBSD/hpcmips
		can be installed using the new interrupt system :-)
20070123	Making the testmips mode work with the new interrupt system.
20070127	Beginning to convert DEC5800 devices to devinit, and to the
		new interrupt system.
		Converting Playstation 2 devices to devinit, and converting
		the interrupt system. Also fixing a severe bug: the interrupt
		mask register on Playstation 2 is bitwise _toggled_ on writes.
20070128	Removing the dummy NetGear machine mode and the 8250 device
		(which was only used by the NetGear machine).
		Beginning to convert the MacPPC GC (Grand Central) interrupt
		controller to the new interrupt system.
		Converting Jazz interrupts (PICA61 etc.) to the new interrupt
		system. NetBSD/arc can be installed again :-)
		Fixing the JAZZ timer (hardcoding it at 100 Hz, works with
		NetBSD and it is better than a completely dummy timer as it
		was before).
		Converting dev_mp to the new interrupt system, although I
		haven't had time to actually test it yet.
		Completely removing src/machines/interrupts.c, cpu_interrupt
		and cpu_interrupt_ack in src/cpu.c, and
		src/include/machine_interrupts.h! Adding fatal error messages
		+ abort() in the few places that are left to fix.
		Converting dev_z8530 to the new interrupt system.
		FINALLY removing the md_int struct completely from the
		machine struct.
		SH4 fixes (adding a PADDR invalidation in the ITLB replacement
		code in memory_sh.c); the NetBSD/dreamcast LiveCD now runs
		all the way to the login prompt, and can be interacted with :-)
		Converting the CPC700 controller (PCI and interrupt controller
		for PM/PPC) to the new interrupt system.
20070129	Fixing MACE ISA interrupts (SGI IP32 emulation). Both NetBSD/
		sgimips' and OpenBSD/sgi's ramdisk kernels can now be
		interacted with again.
20070130	Moving out the MIPS multi_lw and _sw instruction combinations
		so that they are auto-generated at compile time instead.
20070131	Adding detection of amd64/x86_64 hosts in the configure script,
		for doing initial experiments (again :-) with native code
		generation.
		Adding a -k command line option to set the size of the dyntrans
		cache, and a -B command line option to disable native code
		generation, even if GXemul was compiled with support for
		native code generation for the specific host CPU architecture.
20070201	Experimenting with a skeleton for native code generation.
		Changing the default behaviour, so that native code generation
		is now disabled by default, and has to be enabled by using
		-b on the command line.
20070202	Continuing the native code generation experiments.
		Making PCI interrupts work for Footbridge again.
20070203	More native code generation experiments.
		Removing most of the native code generation experimental code,
		it does not make sense to include any quick hacks like this.
		Minor cleanup/removal of some more legacy MIPS interrupt code.
20070204	Making i80321 interrupts work again (for NetBSD/evbarm etc.),
		and fixing the timer at 100 Hz.
20070206	Experimenting with removing the wdc interrupt slowness hack.
20070207	Lowering the number of dyntrans TLB entries for MIPS from
		192 to 128, resulting in a minor speed improvement.
		Minor optimization to the code invalidation routine in
		cpu_dyntrans.c.
20070208	Increasing (experimentally) the nr of dyntrans instructions per
		loop from 60 to 120.
20070210	Commenting out (experimentally) the dyntrans_device_danger
		detection in memory_rw.c.
		Changing the testmips and baremips machines to use a revision 2
		MIPS64 CPU by default, instead of revision 1.
		Removing the dummy i960, IA64, x86, AVR32, and HP PA-RISC
		files, the PC bios emulation, and the Olivetti M700 (ARC) and
		db64360 emulation modes.
20070211	Adding an "mp" demo to the demos directory, which tests the
		SMP functionality of the testmips machine.
		Fixing PReP interrupts some more. NetBSD/prep now boots again.
20070216	Adding a "nop workaround" for booting Mach/PMAX to the
		documentation; thanks to Artur Bujdoso for the values.
		Converting more of the MacPPC interrupt stuff to the new
		system.
		Beginning to convert BeBox interrupts to the new system.
		PPC603e should NOT have the PPC_NO_DEC flag! Removing it.
		Correcting BeBox clock speed (it was set to 100 in the NetBSD
		bootinfo block, but should be 33000000/4), allowing NetBSD
		to start without using the (incorrect) PPC_NO_DEC hack.
20070217	Implementing (slow) AltiVec vector loads and stores, allowing
		NetBSD/macppc to finally boot using the GENERIC kernel :-)
		Updating the documentation with install instructions for
		NetBSD/macppc.
20070218-19	Regression testing for the release.

==============  RELEASE 0.4.4  ==============


1 dpavlin 14 /*
2 dpavlin 34 * Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
3 dpavlin 14 *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 34 * $Id: cpu_m68k.c,v 1.16 2006/12/30 13:30:54 debug Exp $
29 dpavlin 14 *
30     * Motorola 68K CPU emulation.
31     */
32    
33     #include <stdio.h>
34     #include <stdlib.h>
35     #include <string.h>
36     #include <ctype.h>
37    
38     #include "cpu.h"
39     #include "machine.h"
40     #include "memory.h"
41     #include "misc.h"
42 dpavlin 32 #include "settings.h"
43 dpavlin 14 #include "symbol.h"
44    
45    
46     #define DYNTRANS_32
47     #define DYNTRANS_VARIABLE_INSTRUCTION_LENGTH
48     #include "tmp_m68k_head.c"
49    
50    
51     static char *m68k_aname[] = { "a0", "a1", "a2", "a3", "a4", "a5", "fp", "a7" };
52 dpavlin 32 static char *m68k_dname[] = { "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7" };
53 dpavlin 14
54    
55     /*
56     * m68k_cpu_new():
57     *
58     * Create a new M68K cpu object.
59     *
60     * Returns 1 on success, 0 if there was no matching M68K processor with
61     * this cpu_type_name.
62     */
63     int m68k_cpu_new(struct cpu *cpu, struct memory *mem, struct machine *machine,
64     int cpu_id, char *cpu_type_name)
65     {
66 dpavlin 32 int i = 0;
67     struct m68k_cpu_type_def cpu_type_defs[] = M68K_CPU_TYPE_DEFS;
68    
69     /* Scan the cpu_type_defs list for this cpu type: */
70     while (cpu_type_defs[i].name != NULL) {
71     if (strcasecmp(cpu_type_defs[i].name, cpu_type_name) == 0) {
72     break;
73     }
74     i++;
75     }
76     if (cpu_type_defs[i].name == NULL)
77 dpavlin 14 return 0;
78    
79 dpavlin 28 cpu->run_instr = m68k_run_instr;
80 dpavlin 14 cpu->memory_rw = m68k_memory_rw;
81     cpu->update_translation_table = m68k_update_translation_table;
82 dpavlin 18 cpu->invalidate_translation_caches =
83     m68k_invalidate_translation_caches;
84 dpavlin 14 cpu->invalidate_code_translation = m68k_invalidate_code_translation;
85     cpu->is_32bit = 1;
86     cpu->byte_order = EMUL_BIG_ENDIAN;
87    
88 dpavlin 32 cpu->cd.m68k.cpu_type = cpu_type_defs[i];
89    
90 dpavlin 14 /* Only show name and caches etc for CPU nr 0 (in SMP machines): */
91     if (cpu_id == 0) {
92     debug("%s", cpu->name);
93     }
94    
95 dpavlin 32 /* Add all register names to the settings: */
96     CPU_SETTINGS_ADD_REGISTER64("pc", cpu->pc);
97     for (i=0; i<N_M68K_AREGS; i++)
98     CPU_SETTINGS_ADD_REGISTER32(m68k_aname[i], cpu->cd.m68k.a[i]);
99     /* Both "fp" and "a6" should map to the same register: */
100     CPU_SETTINGS_ADD_REGISTER32("a6", cpu->cd.m68k.a[6]);
101     for (i=0; i<N_M68K_DREGS; i++)
102     CPU_SETTINGS_ADD_REGISTER32(m68k_dname[i], cpu->cd.m68k.d[i]);
103    
104 dpavlin 14 return 1;
105     }
106    
107    
108     /*
109     * m68k_cpu_list_available_types():
110     *
111     * Print a list of available M68K CPU types.
112     */
113     void m68k_cpu_list_available_types(void)
114     {
115 dpavlin 32 int i = 0, j;
116     struct m68k_cpu_type_def tdefs[] = M68K_CPU_TYPE_DEFS;
117    
118     while (tdefs[i].name != NULL) {
119     debug("%s", tdefs[i].name);
120     for (j=10 - strlen(tdefs[i].name); j>0; j--)
121     debug(" ");
122     i++;
123     if ((i % 6) == 0 || tdefs[i].name == NULL)
124     debug("\n");
125     }
126 dpavlin 14 }
127    
128    
129     /*
130     * m68k_cpu_dumpinfo():
131     */
132     void m68k_cpu_dumpinfo(struct cpu *cpu)
133     {
134     /* TODO */
135     debug("\n");
136     }
137    
138    
139     /*
140     * m68k_cpu_register_dump():
141     *
142     * Dump cpu registers in a relatively readable format.
143     *
144     * gprs: set to non-zero to dump GPRs and some special-purpose registers.
145     * coprocs: set bit 0..3 to dump registers in coproc 0..3.
146     */
147     void m68k_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs)
148     {
149     char *symbol;
150     uint64_t offset;
151 dpavlin 32 int x = cpu->cpu_id, i;
152 dpavlin 14
153     if (gprs) {
154     /* Special registers (pc, ...) first: */
155     symbol = get_symbol_name(&cpu->machine->symbol_context,
156     cpu->pc, &offset);
157    
158 dpavlin 32 debug("cpu%i: pc = 0x%08"PRIx32, x, (uint32_t)cpu->pc);
159 dpavlin 14 debug(" <%s>\n", symbol != NULL? symbol : " no symbol ");
160    
161 dpavlin 32 for (i=0; i<N_M68K_AREGS; i++) {
162     if ((i % 4) == 0)
163     debug("cpu%i:", x);
164     debug(" %s = 0x%08"PRIx32" ",
165     m68k_aname[i], cpu->cd.m68k.a[i]);
166     if ((i % 4) == 3)
167     debug("\n");
168     }
169 dpavlin 14
170 dpavlin 32 for (i=0; i<N_M68K_DREGS; i++) {
171     if ((i % 4) == 0)
172     debug("cpu%i:", x);
173     debug(" %s = 0x%08"PRIx32" ",
174     m68k_dname[i], cpu->cd.m68k.d[i]);
175     if ((i % 4) == 3)
176     debug("\n");
177     }
178 dpavlin 14 }
179     }
180    
181    
182     /*
183 dpavlin 24 * m68k_cpu_tlbdump():
184     *
185     * Called from the debugger to dump the TLB in a readable format.
186     * x is the cpu number to dump, or -1 to dump all CPUs.
187     *
188     * If rawflag is nonzero, then the TLB contents isn't formated nicely,
189     * just dumped.
190     */
191     void m68k_cpu_tlbdump(struct machine *m, int x, int rawflag)
192     {
193     }
194    
195    
196     /*
197     * m68k_cpu_gdb_stub():
198     *
199     * Execute a "remote GDB" command. Returns a newly allocated response string
200     * on success, NULL on failure.
201     */
202     char *m68k_cpu_gdb_stub(struct cpu *cpu, char *cmd)
203     {
204     fatal("m68k_cpu_gdb_stub(): TODO\n");
205     return NULL;
206     }
207    
208    
209     /*
210 dpavlin 14 * m68k_cpu_interrupt():
211     */
212     int m68k_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr)
213     {
214     fatal("m68k_cpu_interrupt(): TODO\n");
215     return 0;
216     }
217    
218    
219     /*
220     * m68k_cpu_interrupt_ack():
221     */
222     int m68k_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr)
223     {
224     /* fatal("m68k_cpu_interrupt_ack(): TODO\n"); */
225     return 0;
226     }
227    
228    
229     /* Helper functions: */
230     static void print_two(unsigned char *instr, int *len)
231     { debug(" %02x%02x", instr[*len], instr[*len+1]); (*len) += 2; }
232     static void print_spaces(int len) { int i; debug(" "); for (i=0; i<16-len/2*5;
233     i++) debug(" "); }
234    
235    
236     /*
237     * m68k_cpu_disassemble_instr():
238     *
239     * Convert an instruction word into human readable format, for instruction
240     * tracing.
241     *
242     * If running is 1, cpu->pc should be the address of the instruction.
243     *
244     * If running is 0, things that depend on the runtime environment (eg.
245     * register contents) will not be shown, and addr will be used instead of
246     * cpu->pc for relative addresses.
247     */
248     int m68k_cpu_disassemble_instr(struct cpu *cpu, unsigned char *ib,
249 dpavlin 24 int running, uint64_t dumpaddr)
250 dpavlin 14 {
251     uint64_t offset;
252     int len = 0;
253     char *symbol;
254    
255     if (running)
256     dumpaddr = cpu->pc;
257    
258     symbol = get_symbol_name(&cpu->machine->symbol_context,
259     dumpaddr, &offset);
260     if (symbol != NULL && offset==0)
261     debug("<%s>\n", symbol);
262    
263     if (cpu->machine->ncpus > 1 && running)
264     debug("cpu%i: ", cpu->cpu_id);
265    
266     debug("0x%08x: ", (int)dumpaddr);
267    
268     print_two(ib, &len);
269    
270 dpavlin 32 switch (ib[0] >> 4) {
271    
272     case 0x4:
273     switch (ib[0] & 0xf) {
274    
275     case 0xe:
276     if (ib[1] >= 0x50 && ib[1] <= 0x57) {
277     print_two(ib, &len);
278     print_spaces(len);
279 dpavlin 34 debug("linkw\t%%%s,#%i\n",
280     m68k_aname[ib[1] & 7],
281 dpavlin 32 ((ib[2] << 8) + ib[3]));
282     } else if (ib[1] >= 0x58 && ib[1] <= 0x5f) {
283     print_spaces(len);
284     debug("unlk\t%%%s\n", m68k_aname[ib[1] & 7]);
285     } else if (ib[1] == 0x71) {
286     print_spaces(len);
287     debug("nop\n");
288     } else if (ib[1] == 0x73) {
289     print_spaces(len);
290     debug("rte\n");
291     } else if (ib[1] == 0x74) {
292     print_two(ib, &len);
293     print_spaces(len);
294     debug("rtd\t#0x%04x\n", ((ib[2] << 8) + ib[3]));
295     } else if (ib[1] == 0x75) {
296     print_spaces(len);
297     debug("rts\n");
298     } else {
299     print_spaces(len);
300     debug("UNIMPLEMENTED\n");
301     }
302     break;
303    
304     default:print_spaces(len);
305     debug("UNIMPLEMENTED\n");
306 dpavlin 14 }
307 dpavlin 32 break;
308    
309     default:print_spaces(len);
310     debug("UNIMPLEMENTED\n");
311 dpavlin 14 }
312    
313     return len;
314     }
315    
316    
317     #include "tmp_m68k_tail.c"
318    

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