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/* |
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* Copyright (C) 2007 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: cpu_m32r.c,v 1.1 2007/07/20 09:03:33 debug Exp $ |
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* |
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* Mitsubishi/Renesas M32R CPU emulation. |
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*/ |
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|
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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#include <ctype.h> |
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|
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#include "cpu.h" |
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#include "interrupt.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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#include "settings.h" |
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#include "symbol.h" |
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|
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|
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#define DYNTRANS_32 |
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#include "tmp_m32r_head.c" |
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|
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|
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void m32r_pc_to_pointers(struct cpu *); |
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|
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void m32r_irq_interrupt_assert(struct interrupt *interrupt); |
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void m32r_irq_interrupt_deassert(struct interrupt *interrupt); |
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|
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|
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/* |
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* m32r_cpu_new(): |
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* |
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* Create a new M32R cpu object by filling the CPU struct. |
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* Return 1 on success, 0 if cpu_type_name isn't a valid M32R processor. |
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*/ |
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int m32r_cpu_new(struct cpu *cpu, struct memory *mem, |
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struct machine *machine, int cpu_id, char *cpu_type_name) |
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{ |
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int i, found; |
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struct m32r_cpu_type_def cpu_type_defs[] = M32R_CPU_TYPE_DEFS; |
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|
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/* Scan the list for this cpu type: */ |
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i = 0; found = -1; |
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while (i >= 0 && cpu_type_defs[i].name != NULL) { |
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if (strcasecmp(cpu_type_defs[i].name, cpu_type_name) == 0) { |
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found = i; |
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break; |
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} |
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i++; |
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} |
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if (found == -1) |
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return 0; |
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|
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cpu->run_instr = m32r_run_instr; |
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cpu->memory_rw = m32r_memory_rw; |
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cpu->update_translation_table = m32r_update_translation_table; |
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cpu->invalidate_translation_caches = |
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m32r_invalidate_translation_caches; |
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cpu->invalidate_code_translation = m32r_invalidate_code_translation; |
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cpu->translate_v2p = m32r_translate_v2p; |
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|
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cpu->cd.m32r.cpu_type = cpu_type_defs[found]; |
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cpu->name = cpu->cd.m32r.cpu_type.name; |
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cpu->is_32bit = 1; |
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cpu->byte_order = EMUL_BIG_ENDIAN; |
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|
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/* Only show name and caches etc for CPU nr 0: */ |
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if (cpu_id == 0) { |
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debug("%s", cpu->name); |
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} |
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|
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|
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/* |
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* Add register names as settings: |
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*/ |
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|
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CPU_SETTINGS_ADD_REGISTER64("pc", cpu->pc); |
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|
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/* TODO */ |
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|
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/* Register the CPU interrupt pin: */ |
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{ |
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struct interrupt template; |
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char name[50]; |
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snprintf(name, sizeof(name), "%s", cpu->path); |
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|
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memset(&template, 0, sizeof(template)); |
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template.line = 0; |
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template.name = name; |
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template.extra = cpu; |
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template.interrupt_assert = m32r_irq_interrupt_assert; |
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template.interrupt_deassert = m32r_irq_interrupt_deassert; |
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interrupt_handler_register(&template); |
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} |
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|
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return 1; |
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} |
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|
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|
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/* |
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* m32r_cpu_dumpinfo(): |
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*/ |
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void m32r_cpu_dumpinfo(struct cpu *cpu) |
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{ |
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/* struct m32r_cpu_type_def *ct = &cpu->cd.m32r.cpu_type; */ |
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|
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debug(", %s-endian", |
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cpu->byte_order == EMUL_BIG_ENDIAN? "Big" : "Little"); |
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|
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debug("\n"); |
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} |
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|
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|
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/* |
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* m32r_cpu_list_available_types(): |
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* |
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* Print a list of available M32R CPU types. |
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*/ |
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void m32r_cpu_list_available_types(void) |
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{ |
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int i, j; |
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struct m32r_cpu_type_def tdefs[] = M32R_CPU_TYPE_DEFS; |
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|
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i = 0; |
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while (tdefs[i].name != NULL) { |
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debug("%s", tdefs[i].name); |
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for (j=13 - strlen(tdefs[i].name); j>0; j--) |
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debug(" "); |
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i++; |
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if ((i % 5) == 0 || tdefs[i].name == NULL) |
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debug("\n"); |
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} |
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} |
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|
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|
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/* |
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* m32r_cpu_register_dump(): |
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* |
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* Dump cpu registers in a relatively readable format. |
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* |
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* gprs: set to non-zero to dump GPRs and some special-purpose registers. |
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* coprocs: set bit 0..3 to dump registers in coproc 0..3. |
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*/ |
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void m32r_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs) |
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{ |
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char *symbol; |
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uint64_t offset; |
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int i, x = cpu->cpu_id; |
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|
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if (gprs) { |
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symbol = get_symbol_name(&cpu->machine->symbol_context, |
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cpu->pc, &offset); |
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debug("cpu%i: pc = 0x%08"PRIx32, x, (uint32_t)cpu->pc); |
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debug(" <%s>\n", symbol != NULL? symbol : " no symbol "); |
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|
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for (i=0; i<N_M32R_GPRS; i++) { |
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if ((i % 4) == 0) |
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debug("cpu%i:", x); |
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if (i == 0) |
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debug(" "); |
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else |
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debug(" r%-2i = 0x%08"PRIx32, |
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i, cpu->cd.m32r.r[i]); |
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if ((i % 4) == 3) |
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debug("\n"); |
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} |
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} |
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} |
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|
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|
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/* |
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* m32r_cpu_tlbdump(): |
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* |
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* Called from the debugger to dump the TLB in a readable format. |
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* x is the cpu number to dump, or -1 to dump all CPUs. |
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* |
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* If rawflag is nonzero, then the TLB contents isn't formated nicely, |
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* just dumped. |
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*/ |
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void m32r_cpu_tlbdump(struct machine *m, int x, int rawflag) |
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{ |
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} |
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|
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|
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/* |
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* m32r_irq_interrupt_assert(): |
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* m32r_irq_interrupt_deassert(): |
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*/ |
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void m32r_irq_interrupt_assert(struct interrupt *interrupt) |
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{ |
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struct cpu *cpu = (struct cpu *) interrupt->extra; |
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cpu->cd.m32r.irq_asserted = 1; |
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} |
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void m32r_irq_interrupt_deassert(struct interrupt *interrupt) |
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{ |
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struct cpu *cpu = (struct cpu *) interrupt->extra; |
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cpu->cd.m32r.irq_asserted = 0; |
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} |
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|
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|
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/* |
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* m32r_cpu_disassemble_instr(): |
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* |
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* Convert an instruction word into human readable format, for instruction |
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* tracing. |
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* |
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* If running is 1, cpu->pc should be the address of the instruction. |
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* |
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* If running is 0, things that depend on the runtime environment (eg. |
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* register contents) will not be shown, and dumpaddr will be used instead of |
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* cpu->pc for relative addresses. |
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*/ |
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int m32r_cpu_disassemble_instr(struct cpu *cpu, unsigned char *ib, |
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int running, uint64_t dumpaddr) |
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{ |
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uint32_t iw; |
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char *symbol; |
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uint64_t offset; |
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|
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if (running) |
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dumpaddr = cpu->pc; |
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|
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symbol = get_symbol_name(&cpu->machine->symbol_context, |
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dumpaddr, &offset); |
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if (symbol != NULL && offset == 0) |
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debug("<%s>\n", symbol); |
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|
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if (cpu->machine->ncpus > 1 && running) |
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debug("cpu%i:\t", cpu->cpu_id); |
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|
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debug("%08"PRIx32": ", (uint32_t) dumpaddr); |
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|
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if (cpu->byte_order == EMUL_LITTLE_ENDIAN) |
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iw = ib[0] + (ib[1]<<8) + (ib[2]<<16) + (ib[3]<<24); |
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else |
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iw = ib[3] + (ib[2]<<8) + (ib[1]<<16) + (ib[0]<<24); |
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|
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debug("%08"PRIx32"\t", (uint32_t) iw); |
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|
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switch (iw) { |
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|
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default: |
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debug("UNIMPLEMENTED iw=0x%08x\n", iw); |
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} |
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|
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return sizeof(uint32_t); |
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} |
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|
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|
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#include "tmp_m32r_tail.c" |
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|
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|