src/cpus/cpu_m32r.c

/*
 *  Copyright (C) 2007  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *
 *
 *  $Id: cpu_m32r.c,v 1.1 2007/07/20 09:03:33 debug Exp $
 *
 *  Mitsubishi/Renesas M32R CPU emulation.
 */

#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <ctype.h>

#include "cpu.h"
#include "interrupt.h"
#include "machine.h"
#include "memory.h"
#include "misc.h"
#include "settings.h"
#include "symbol.h"


#define DYNTRANS_32
#include "tmp_m32r_head.c"


void m32r_pc_to_pointers(struct cpu *);

void m32r_irq_interrupt_assert(struct interrupt *interrupt);
void m32r_irq_interrupt_deassert(struct interrupt *interrupt);


/*
 *  m32r_cpu_new():
 *
 *  Create a new M32R cpu object by filling the CPU struct.
 *  Return 1 on success, 0 if cpu_type_name isn't a valid M32R processor.
 */
int m32r_cpu_new(struct cpu *cpu, struct memory *mem,
        struct machine *machine, int cpu_id, char *cpu_type_name)
{
        int i, found;
        struct m32r_cpu_type_def cpu_type_defs[] = M32R_CPU_TYPE_DEFS;

        /*  Scan the list for this cpu type:  */
        i = 0; found = -1;
        while (i >= 0 && cpu_type_defs[i].name != NULL) {
                if (strcasecmp(cpu_type_defs[i].name, cpu_type_name) == 0) {
                        found = i;
                        break;
                }
                i++;
        }
        if (found == -1)
                return 0;

        cpu->run_instr = m32r_run_instr;
        cpu->memory_rw = m32r_memory_rw;
        cpu->update_translation_table = m32r_update_translation_table;
        cpu->invalidate_translation_caches =
            m32r_invalidate_translation_caches;
        cpu->invalidate_code_translation = m32r_invalidate_code_translation;
        cpu->translate_v2p = m32r_translate_v2p;

        cpu->cd.m32r.cpu_type = cpu_type_defs[found];
        cpu->name            = cpu->cd.m32r.cpu_type.name;
        cpu->is_32bit        = 1;
        cpu->byte_order      = EMUL_BIG_ENDIAN;

        /*  Only show name and caches etc for CPU nr 0:  */
        if (cpu_id == 0) {
                debug("%s", cpu->name);
        }


        /*
         *  Add register names as settings:
         */

        CPU_SETTINGS_ADD_REGISTER64("pc", cpu->pc);

        /*  TODO  */

        /*  Register the CPU interrupt pin:  */
        {
                struct interrupt template;
                char name[50];
                snprintf(name, sizeof(name), "%s", cpu->path);

                memset(&template, 0, sizeof(template));
                template.line = 0;
                template.name = name;
                template.extra = cpu;
                template.interrupt_assert = m32r_irq_interrupt_assert;
                template.interrupt_deassert = m32r_irq_interrupt_deassert;
                interrupt_handler_register(&template);
        }

        return 1;
}


/*
 *  m32r_cpu_dumpinfo():
 */
void m32r_cpu_dumpinfo(struct cpu *cpu)
{
        /*  struct m32r_cpu_type_def *ct = &cpu->cd.m32r.cpu_type;  */

        debug(", %s-endian",
            cpu->byte_order == EMUL_BIG_ENDIAN? "Big" : "Little");

        debug("\n");
}


/*
 *  m32r_cpu_list_available_types():
 *
 *  Print a list of available M32R CPU types.
 */
void m32r_cpu_list_available_types(void)
{
        int i, j;
        struct m32r_cpu_type_def tdefs[] = M32R_CPU_TYPE_DEFS;

        i = 0;
        while (tdefs[i].name != NULL) {
                debug("%s", tdefs[i].name);
                for (j=13 - strlen(tdefs[i].name); j>0; j--)
                        debug(" ");
                i++;
                if ((i % 5) == 0 || tdefs[i].name == NULL)
                        debug("\n");
        }
}


/*
 *  m32r_cpu_register_dump():
 *
 *  Dump cpu registers in a relatively readable format.
 *  
 *  gprs: set to non-zero to dump GPRs and some special-purpose registers.
 *  coprocs: set bit 0..3 to dump registers in coproc 0..3.
 */
void m32r_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs)
{
        char *symbol;
        uint64_t offset;
        int i, x = cpu->cpu_id;

        if (gprs) {
                symbol = get_symbol_name(&cpu->machine->symbol_context,
                    cpu->pc, &offset);
                debug("cpu%i:  pc  = 0x%08"PRIx32, x, (uint32_t)cpu->pc);
                debug("  <%s>\n", symbol != NULL? symbol : " no symbol ");

                for (i=0; i<N_M32R_GPRS; i++) {
                        if ((i % 4) == 0)
                                debug("cpu%i:", x);
                        if (i == 0)
                                debug("                  ");
                        else
                                debug("  r%-2i = 0x%08"PRIx32,
                                    i, cpu->cd.m32r.r[i]);
                        if ((i % 4) == 3)
                                debug("\n");
                }
        }
}


/*
 *  m32r_cpu_tlbdump():
 *
 *  Called from the debugger to dump the TLB in a readable format.
 *  x is the cpu number to dump, or -1 to dump all CPUs.
 *
 *  If rawflag is nonzero, then the TLB contents isn't formated nicely,
 *  just dumped.
 */
void m32r_cpu_tlbdump(struct machine *m, int x, int rawflag)
{
}


/*
 *  m32r_irq_interrupt_assert():
 *  m32r_irq_interrupt_deassert():
 */
void m32r_irq_interrupt_assert(struct interrupt *interrupt)
{
        struct cpu *cpu = (struct cpu *) interrupt->extra;
        cpu->cd.m32r.irq_asserted = 1;
}
void m32r_irq_interrupt_deassert(struct interrupt *interrupt)
{
        struct cpu *cpu = (struct cpu *) interrupt->extra;
        cpu->cd.m32r.irq_asserted = 0;
}


/*
 *  m32r_cpu_disassemble_instr():
 *
 *  Convert an instruction word into human readable format, for instruction
 *  tracing.
 *              
 *  If running is 1, cpu->pc should be the address of the instruction.
 *
 *  If running is 0, things that depend on the runtime environment (eg.
 *  register contents) will not be shown, and dumpaddr will be used instead of
 *  cpu->pc for relative addresses.
 */                     
int m32r_cpu_disassemble_instr(struct cpu *cpu, unsigned char *ib,
        int running, uint64_t dumpaddr)
{
        uint32_t iw;
        char *symbol;
        uint64_t offset;

        if (running)
                dumpaddr = cpu->pc;

        symbol = get_symbol_name(&cpu->machine->symbol_context,
            dumpaddr, &offset);
        if (symbol != NULL && offset == 0)
                debug("<%s>\n", symbol);

        if (cpu->machine->ncpus > 1 && running)
                debug("cpu%i:\t", cpu->cpu_id);

        debug("%08"PRIx32": ", (uint32_t) dumpaddr);

        if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
                iw = ib[0] + (ib[1]<<8) + (ib[2]<<16) + (ib[3]<<24);
        else
                iw = ib[3] + (ib[2]<<8) + (ib[1]<<16) + (ib[0]<<24);

        debug("%08"PRIx32"\t", (uint32_t) iw);

        switch (iw) {

        default:
                debug("UNIMPLEMENTED iw=0x%08x\n", iw);
        }

        return sizeof(uint32_t);
}


#include "tmp_m32r_tail.c"


1	dpavlin	44	/*
2			* Copyright (C) 2007 Anders Gavare. All rights reserved.
3			*
4			* Redistribution and use in source and binary forms, with or without
5			* modification, are permitted provided that the following conditions are met:
6			*
7			* 1. Redistributions of source code must retain the above copyright
8			* notice, this list of conditions and the following disclaimer.
9			* 2. Redistributions in binary form must reproduce the above copyright
10			* notice, this list of conditions and the following disclaimer in the
11			* documentation and/or other materials provided with the distribution.
12			* 3. The name of the author may not be used to endorse or promote products
13			* derived from this software without specific prior written permission.
14			*
15			* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16			* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17			* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18			* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19			* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20			* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21			* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22			* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23			* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24			* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25			* SUCH DAMAGE.
26			*
27			*
28			* $Id: cpu_m32r.c,v 1.1 2007/07/20 09:03:33 debug Exp $
29			*
30			* Mitsubishi/Renesas M32R CPU emulation.
31			*/
32
33			#include <stdio.h>
34			#include <stdlib.h>
35			#include <string.h>
36			#include <ctype.h>
37
38			#include "cpu.h"
39			#include "interrupt.h"
40			#include "machine.h"
41			#include "memory.h"
42			#include "misc.h"
43			#include "settings.h"
44			#include "symbol.h"
45
46
47			#define DYNTRANS_32
48			#include "tmp_m32r_head.c"
49
50
51			void m32r_pc_to_pointers(struct cpu *);
52
53			void m32r_irq_interrupt_assert(struct interrupt *interrupt);
54			void m32r_irq_interrupt_deassert(struct interrupt *interrupt);
55
56
57			/*
58			* m32r_cpu_new():
59			*
60			* Create a new M32R cpu object by filling the CPU struct.
61			* Return 1 on success, 0 if cpu_type_name isn't a valid M32R processor.
62			*/
63			int m32r_cpu_new(struct cpu cpu, struct memory mem,
64			struct machine machine, int cpu_id, char cpu_type_name)
65			{
66			int i, found;
67			struct m32r_cpu_type_def cpu_type_defs[] = M32R_CPU_TYPE_DEFS;
68
69			/* Scan the list for this cpu type: */
70			i = 0; found = -1;
71			while (i >= 0 && cpu_type_defs[i].name != NULL) {
72			if (strcasecmp(cpu_type_defs[i].name, cpu_type_name) == 0) {
73			found = i;
74			break;
75			}
76			i++;
77			}
78			if (found == -1)
79			return 0;
80
81			cpu->run_instr = m32r_run_instr;
82			cpu->memory_rw = m32r_memory_rw;
83			cpu->update_translation_table = m32r_update_translation_table;
84			cpu->invalidate_translation_caches =
85			m32r_invalidate_translation_caches;
86			cpu->invalidate_code_translation = m32r_invalidate_code_translation;
87			cpu->translate_v2p = m32r_translate_v2p;
88
89			cpu->cd.m32r.cpu_type = cpu_type_defs[found];
90			cpu->name = cpu->cd.m32r.cpu_type.name;
91			cpu->is_32bit = 1;
92			cpu->byte_order = EMUL_BIG_ENDIAN;
93
94			/* Only show name and caches etc for CPU nr 0: */
95			if (cpu_id == 0) {
96			debug("%s", cpu->name);
97			}
98
99
100			/*
101			* Add register names as settings:
102			*/
103
104			CPU_SETTINGS_ADD_REGISTER64("pc", cpu->pc);
105
106			/* TODO */
107
108			/* Register the CPU interrupt pin: */
109			{
110			struct interrupt template;
111			char name[50];
112			snprintf(name, sizeof(name), "%s", cpu->path);
113
114			memset(&template, 0, sizeof(template));
115			template.line = 0;
116			template.name = name;
117			template.extra = cpu;
118			template.interrupt_assert = m32r_irq_interrupt_assert;
119			template.interrupt_deassert = m32r_irq_interrupt_deassert;
120			interrupt_handler_register(&template);
121			}
122
123			return 1;
124			}
125
126
127			/*
128			* m32r_cpu_dumpinfo():
129			*/
130			void m32r_cpu_dumpinfo(struct cpu *cpu)
131			{
132			/* struct m32r_cpu_type_def ct = &cpu->cd.m32r.cpu_type; /
133
134			debug(", %s-endian",
135			cpu->byte_order == EMUL_BIG_ENDIAN? "Big" : "Little");
136
137			debug("\n");
138			}
139
140
141			/*
142			* m32r_cpu_list_available_types():
143			*
144			* Print a list of available M32R CPU types.
145			*/
146			void m32r_cpu_list_available_types(void)
147			{
148			int i, j;
149			struct m32r_cpu_type_def tdefs[] = M32R_CPU_TYPE_DEFS;
150
151			i = 0;
152			while (tdefs[i].name != NULL) {
153			debug("%s", tdefs[i].name);
154			for (j=13 - strlen(tdefs[i].name); j>0; j--)
155			debug(" ");
156			i++;
157			if ((i % 5) == 0 \|\| tdefs[i].name == NULL)
158			debug("\n");
159			}
160			}
161
162
163			/*
164			* m32r_cpu_register_dump():
165			*
166			* Dump cpu registers in a relatively readable format.
167			*
168			* gprs: set to non-zero to dump GPRs and some special-purpose registers.
169			* coprocs: set bit 0..3 to dump registers in coproc 0..3.
170			*/
171			void m32r_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs)
172			{
173			char *symbol;
174			uint64_t offset;
175			int i, x = cpu->cpu_id;
176
177			if (gprs) {
178			symbol = get_symbol_name(&cpu->machine->symbol_context,
179			cpu->pc, &offset);
180			debug("cpu%i: pc = 0x%08"PRIx32, x, (uint32_t)cpu->pc);
181			debug(" <%s>\n", symbol != NULL? symbol : " no symbol ");
182
183			for (i=0; i<N_M32R_GPRS; i++) {
184			if ((i % 4) == 0)
185			debug("cpu%i:", x);
186			if (i == 0)
187			debug(" ");
188			else
189			debug(" r%-2i = 0x%08"PRIx32,
190			i, cpu->cd.m32r.r[i]);
191			if ((i % 4) == 3)
192			debug("\n");
193			}
194			}
195			}
196
197
198			/*
199			* m32r_cpu_tlbdump():
200			*
201			* Called from the debugger to dump the TLB in a readable format.
202			* x is the cpu number to dump, or -1 to dump all CPUs.
203			*
204			* If rawflag is nonzero, then the TLB contents isn't formated nicely,
205			* just dumped.
206			*/
207			void m32r_cpu_tlbdump(struct machine *m, int x, int rawflag)
208			{
209			}
210
211
212			/*
213			* m32r_irq_interrupt_assert():
214			* m32r_irq_interrupt_deassert():
215			*/
216			void m32r_irq_interrupt_assert(struct interrupt *interrupt)
217			{
218			struct cpu cpu = (struct cpu ) interrupt->extra;
219			cpu->cd.m32r.irq_asserted = 1;
220			}
221			void m32r_irq_interrupt_deassert(struct interrupt *interrupt)
222			{
223			struct cpu cpu = (struct cpu ) interrupt->extra;
224			cpu->cd.m32r.irq_asserted = 0;
225			}
226
227
228			/*
229			* m32r_cpu_disassemble_instr():
230			*
231			* Convert an instruction word into human readable format, for instruction
232			* tracing.
233			*
234			* If running is 1, cpu->pc should be the address of the instruction.
235			*
236			* If running is 0, things that depend on the runtime environment (eg.
237			* register contents) will not be shown, and dumpaddr will be used instead of
238			* cpu->pc for relative addresses.
239			*/
240			int m32r_cpu_disassemble_instr(struct cpu cpu, unsigned char ib,
241			int running, uint64_t dumpaddr)
242			{
243			uint32_t iw;
244			char *symbol;
245			uint64_t offset;
246
247			if (running)
248			dumpaddr = cpu->pc;
249
250			symbol = get_symbol_name(&cpu->machine->symbol_context,
251			dumpaddr, &offset);
252			if (symbol != NULL && offset == 0)
253			debug("<%s>\n", symbol);
254
255			if (cpu->machine->ncpus > 1 && running)
256			debug("cpu%i:\t", cpu->cpu_id);
257
258			debug("%08"PRIx32": ", (uint32_t) dumpaddr);
259
260			if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
261			iw = ib[0] + (ib[1]<<8) + (ib[2]<<16) + (ib[3]<<24);
262			else
263			iw = ib[3] + (ib[2]<<8) + (ib[1]<<16) + (ib[0]<<24);
264
265			debug("%08"PRIx32"\t", (uint32_t) iw);
266
267			switch (iw) {
268
269			default:
270			debug("UNIMPLEMENTED iw=0x%08x\n", iw);
271			}
272
273			return sizeof(uint32_t);
274			}
275
276
277			#include "tmp_m32r_tail.c"
278
279