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/* |
/* |
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* Copyright (C) 2005 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: cpu_ia64_instr.c,v 1.2 2005/11/06 22:41:12 debug Exp $ |
* $Id: cpu_ia64_instr.c,v 1.4 2006/02/09 22:40:27 debug Exp $ |
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* |
* |
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* IA64 instructions. |
* IA64 instructions. |
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* |
* |
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X(to_be_translated) |
X(to_be_translated) |
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{ |
{ |
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uint64_t addr, low_pc; |
uint64_t addr, low_pc; |
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struct ia64_vph_page *vph_p; |
#ifdef DYNTRANS_BACKEND |
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unsigned char *page; |
int simple = 0; |
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#endif |
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unsigned char ib[16]; |
unsigned char ib[16]; |
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/* Figure out the (virtual) address of the instruction: */ |
/* Figure out the (virtual) address of the instruction: */ |
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/* Read the instruction word from memory: */ |
/* Read the instruction word from memory: */ |
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#if 0 |
#if 0 |
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if ((addr >> _TOPSHIFT) == 0) { |
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vph_p = cpu->cd.alpha.vph_table0[(addr >> |
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ALPHA_LEVEL0_SHIFT) & 8191]; |
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page = vph_p->host_load[(addr >> ALPHA_LEVEL1_SHIFT) & 8191]; |
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} else if ((addr >> ALPHA_TOPSHIFT) == ALPHA_TOP_KERNEL) { |
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vph_p = cpu->cd.alpha.vph_table0_kernel[(addr >> |
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ALPHA_LEVEL0_SHIFT) & 8191]; |
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page = vph_p->host_load[(addr >> ALPHA_LEVEL1_SHIFT) & 8191]; |
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} else |
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page = NULL; |
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if (page != NULL) { |
if (page != NULL) { |
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/* fatal("TRANSLATION HIT!\n"); */ |
/* fatal("TRANSLATION HIT!\n"); */ |
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memcpy(ib, page + (addr & 8191), sizeof(ib)); |
memcpy(ib, page + (addr & 8191), sizeof(ib)); |