/[gxemul]/trunk/src/cpus/cpu_ia64.c
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Contents of /trunk/src/cpus/cpu_ia64.c

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Revision 26 - (show annotations)
Mon Oct 8 16:20:10 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 5742 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1264 2006/06/25 11:08:04 debug Exp $
20060624	Replacing the error-prone machine type initialization stuff
		with something more reasonable.
		Finally removing the old "cpu_run" kludge; moving around stuff
		in machine.c and emul.c to better suit the dyntrans system.
		Various minor dyntrans cleanups (renaming translate_address to
		translate_v2p, and experimenting with template physpages).
20060625	Removing the speed hack which separated the vph entries into
		two halves (code vs data); things seem a lot more stable now.
		Minor performance hack: R2000/R3000 cache isolation now only
		clears address translations when going into isolation, not
		when going out of it.
		Fixing the MIPS interrupt problems by letting mtc0 immediately
		cause interrupts.

==============  RELEASE 0.4.0.1  ==============


1 /*
2 * Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: cpu_ia64.c,v 1.12 2006/06/24 21:47:23 debug Exp $
29 *
30 * IA64 CPU emulation.
31 *
32 * TODO: Everything.
33 */
34
35 #include <stdio.h>
36 #include <stdlib.h>
37 #include <string.h>
38 #include <ctype.h>
39
40 #include "cpu.h"
41 #include "machine.h"
42 #include "memory.h"
43 #include "misc.h"
44 #include "symbol.h"
45
46 #include "tmp_ia64_head.c"
47
48
49 /*
50 * ia64_cpu_new():
51 *
52 * Create a new IA64 CPU object by filling the CPU struct.
53 * Return 1 on success, 0 if cpu_type_name isn't a valid IA64 processor.
54 */
55 int ia64_cpu_new(struct cpu *cpu, struct memory *mem,
56 struct machine *machine, int cpu_id, char *cpu_type_name)
57 {
58 if (strcasecmp(cpu_type_name, "IA64") != 0)
59 return 0;
60
61 cpu->memory_rw = ia64_memory_rw;
62 cpu->update_translation_table = ia64_update_translation_table;
63 cpu->invalidate_translation_caches =
64 ia64_invalidate_translation_caches;
65 cpu->invalidate_code_translation = ia64_invalidate_code_translation;
66 cpu->is_32bit = 0;
67
68 /* Only show name and caches etc for CPU nr 0: */
69 if (cpu_id == 0) {
70 debug("%s", cpu->name);
71 }
72
73 return 1;
74 }
75
76
77 /*
78 * ia64_cpu_dumpinfo():
79 */
80 void ia64_cpu_dumpinfo(struct cpu *cpu)
81 {
82 /* TODO */
83 debug("\n");
84 }
85
86
87 /*
88 * ia64_cpu_list_available_types():
89 *
90 * Print a list of available IA64 CPU types.
91 */
92 void ia64_cpu_list_available_types(void)
93 {
94 /* TODO */
95
96 debug("IA64\n");
97 }
98
99
100 /*
101 * ia64_cpu_register_match():
102 */
103 void ia64_cpu_register_match(struct machine *m, char *name,
104 int writeflag, uint64_t *valuep, int *match_register)
105 {
106 int cpunr = 0;
107
108 /* CPU number: */
109
110 /* TODO */
111
112 if (strcasecmp(name, "pc") == 0) {
113 if (writeflag) {
114 m->cpus[cpunr]->pc = *valuep;
115 } else
116 *valuep = m->cpus[cpunr]->pc;
117 *match_register = 1;
118 }
119
120 /* TODO */
121 }
122
123
124 /*
125 * ia64_cpu_register_dump():
126 *
127 * Dump cpu registers in a relatively readable format.
128 *
129 * gprs: set to non-zero to dump GPRs and some special-purpose registers.
130 * coprocs: set bit 0..3 to dump registers in coproc 0..3.
131 */
132 void ia64_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs)
133 {
134 char *symbol;
135 uint64_t offset;
136 int x = cpu->cpu_id;
137
138 if (gprs) {
139 symbol = get_symbol_name(&cpu->machine->symbol_context,
140 cpu->pc, &offset);
141 debug("cpu%i:\t pc = 0x%016"PRIx64, x, (uint64_t)cpu->pc);
142 debug(" <%s>\n", symbol != NULL? symbol : " no symbol ");
143
144 /* TODO */
145 }
146 }
147
148
149 /*
150 * mips_cpu_tlbdump():
151 *
152 * Called from the debugger to dump the TLB in a readable format.
153 * x is the cpu number to dump, or -1 to dump all CPUs.
154 *
155 * If rawflag is nonzero, then the TLB contents isn't formated nicely,
156 * just dumped.
157 */
158 void ia64_cpu_tlbdump(struct machine *m, int x, int rawflag)
159 {
160 }
161
162
163 /*
164 * ia64_cpu_gdb_stub():
165 *
166 * Execute a "remote GDB" command. Returns a newly allocated response string
167 * on success, NULL on failure.
168 */
169 char *ia64_cpu_gdb_stub(struct cpu *cpu, char *cmd)
170 {
171 fatal("ia64_cpu_gdb_stub(): TODO\n");
172 return NULL;
173 }
174
175
176 /*
177 * ia64_cpu_interrupt():
178 */
179 int ia64_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr)
180 {
181 fatal("ia64_cpu_interrupt(): TODO\n");
182 return 0;
183 }
184
185
186 /*
187 * ia64_cpu_interrupt_ack():
188 */
189 int ia64_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr)
190 {
191 /* fatal("ia64_cpu_interrupt_ack(): TODO\n"); */
192 return 0;
193 }
194
195
196 /*
197 * ia64_cpu_disassemble_instr():
198 *
199 * Convert an instruction word into human readable format, for instruction
200 * tracing.
201 *
202 * If running is 1, cpu->pc should be the address of the instruction.
203 *
204 * If running is 0, things that depend on the runtime environment (eg.
205 * register contents) will not be shown, and addr will be used instead of
206 * cpu->pc for relative addresses.
207 */
208 int ia64_cpu_disassemble_instr(struct cpu *cpu, unsigned char *ib,
209 int running, uint64_t dumpaddr)
210 {
211 uint64_t offset;
212 char *symbol;
213
214 if (running)
215 dumpaddr = cpu->pc;
216
217 symbol = get_symbol_name(&cpu->machine->symbol_context,
218 dumpaddr, &offset);
219 if (symbol != NULL && offset == 0)
220 debug("<%s>\n", symbol);
221
222 if (cpu->machine->ncpus > 1 && running)
223 debug("cpu%i:\t", cpu->cpu_id);
224
225 debug("%016"PRIx64": ", (uint64_t) dumpaddr);
226
227 debug("TODO\n");
228
229 /* iw = ib[0] + (ib[1]<<8) + (ib[2]<<16) + (ib[3]<<24); */
230
231 return 16;
232 }
233
234
235 #include "tmp_ia64_tail.c"
236

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