/[gxemul]/trunk/src/cpus/cpu_ia64.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Contents of /trunk/src/cpus/cpu_ia64.c

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Revision 22 - (show annotations)
Mon Oct 8 16:19:37 2007 UTC (13 years, 1 month ago) by dpavlin
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File size: 5169 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1121 2006/02/18 21:03:08 debug Exp $
20051126	Cobalt and PReP now work with the 21143 NIC.
		Continuing on Alpha dyntrans things.
		Fixing some more left-shift-by-24 to unsigned.
20051127	Working on OpenFirmware emulation; major cleanup/redesign.
		Progress on MacPPC emulation: NetBSD detects two CPUs (when
		running with -n 2), framebuffer output (for text) works.
		Adding quick-hack Bandit PCI controller and "gc" interrupt
		controller for MacPPC.
20051128	Changing from a Bandit to a Uni-North controller for macppc.
		Continuing on OpenFirmware and MacPPC emulation in general
		(obio controller, and wdc attached to the obio seems to work).
20051129	More work on MacPPC emulation (adding a dummy ADB controller).
		Continuing the PCI bus cleanup (endianness and tag composition)
		and rewriting all PCI controllers' access functions.
20051130	Various minor PPC dyntrans optimizations.
		Manually inlining some parts of the framebuffer redraw routine.
		Slowly beginning the conversion of the old MIPS emulation into
		dyntrans (but this will take quite some time to get right).
		Generalizing quick_pc_to_pointers.
20051201	Documentation update (David Muse has made available a kernel
		which simplifies Debian/DECstation installation).
		Continuing on the ADB bus controller.
20051202	Beginning a rewrite of the Zilog serial controller (dev_zs).
20051203	Continuing on the zs rewrite (now called dev_z8530); conversion
		to devinit style.
		Reworking some of the input-only vs output-only vs input-output
		details of src/console.c, better warning messages, and adding
		a debug dump.
		Removing the concept of "device state"; it wasn't really used.
		Changing some debug output (-vv should now be used to show all
		details about devices and busses; not shown during normal
		startup anymore).
		Beginning on some SPARC instruction disassembly support.
20051204	Minor PPC updates (WALNUT skeleton stuff).
		Continuing on the MIPS dyntrans rewrite.
		More progress on the ADB controller (a keyboard is "detected"
		by NetBSD and OpenBSD).
		Downgrading OpenBSD/arc as a guest OS from "working" to
		"almost working" in the documentation.
		Progress on Algor emulation ("v3" PCI controller).
20051205	Minor updates.
20051207	Sorting devices according to address; this reduces complexity
		of device lookups from O(n) to O(log n) in memory_rw (but no
		real performance increase (yet) in experiments).
20051210	Beginning the work on native dyntrans backends (by making a
		simple skeleton; so far only for Alpha hosts).
20051211	Some very minor SPARC updates.
20051215	Fixing a bug in the MIPS mul (note: not mult) instruction,
		so it also works with non-64-bit emulation. (Thanks to Alec
		Voropay for noticing the problem.)
20051216	More work on the fake/empty/simple/skeleton/whatever backend;
		performance doesn't increase, so this isn't really worth it,
		but it was probably worth it to prepare for a real backend
		later.
20051219	More instr call statistics gathering and analysis stuff.
20051220	Another fix for MIPS 'mul'. Also converting mul and {d,}cl{o,z}
		to dyntrans.
		memory_ppc.c syntax error fix (noticed by Peter Valchev).
		Beginning to move out machines from src/machine.c into
		individual files in src/machines (in a way similar to the
		autodev system for devices).
20051222	Updating the documentation regarding NetBSD/pmax 3.0.
20051223	- " - NetBSD/cats 3.0.
20051225	- " - NetBSD/hpcmips 3.0.
20051226	Continuing on the machine registry redesign.
		Adding support for ARM rrx (33-bit rotate).
		Fixing some signed/unsigned issues (exposed by gcc -W).
20051227	Fixing the bug which prevented a NetBSD/prep 3.0 install kernel
		from starting (triggered when an mtmsr was the last instruction
		on a page). Unfortunately not enough to get the kernel to run
		as well as the 2.1 kernels did.
20051230	Some dyntrans refactoring.
20051231	Continuing on the machine registry redesign.
20060101-10	Continuing... moving more machines. Moving MD interrupt stuff
		from machine.c into a new src/machines/interrupts.c.
20060114	Adding various mvmeppc machine skeletons.
20060115	Continuing on mvme* stuff. NetBSD/mvmeppc prints boot messages
		(for MVME1600) and reaches the root device prompt, but no
		specific hardware devices are emulated yet.
20060116	Minor updates to the mvme1600 emulation mode; the Eagle PCI bus
		seems to work without much modification, and a 21143 can be
		detected, interrupts might work (but untested so far).
		Adding a fake MK48Txx (mkclock) device, for NetBSD/mvmeppc.
20060121	Adding an aux control register for ARM. (A BIG thank you to
		Olivier Houchard for tracking down this bug.)
20060122	Adding more ARM instructions (smulXY), and dev_iq80321_7seg.
20060124	Adding disassembly of more ARM instructions (mia*, mra/mar),
		and some semi-bogus XScale and i80321 registers.
20060201-02	Various minor updates. Moving the last machines out of
		machine.c.
20060204	Adding a -c command line option, for running debugger commands
		before the simulation starts, but after all files have been
		loaded.
		Minor iq80321-related updates.
20060209	Minor hacks (DEVINIT macro, etc).
		Preparing for the generalization of the 64-bit dyntrans address
		translation subsystem.
20060216	Adding ARM ldrd (double-register load).
20060217	Continuing on various ARM-related stuff.
20060218	More progress on the ATA/wdc emulation for NetBSD/iq80321.
		NetBSD/evbarm can now be installed :-)  Updating the docs, etc.
		Continuing on Algor emulation.

==============  RELEASE 0.3.8  ==============


1 /*
2 * Copyright (C) 2005 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: cpu_ia64.c,v 1.4 2006/02/09 22:40:27 debug Exp $
29 *
30 * IA64 CPU emulation.
31 *
32 * TODO: Everything.
33 */
34
35 #include <stdio.h>
36 #include <stdlib.h>
37 #include <string.h>
38 #include <ctype.h>
39
40 #include "cpu.h"
41 #include "machine.h"
42 #include "memory.h"
43 #include "misc.h"
44 #include "symbol.h"
45
46 #include "tmp_ia64_head.c"
47
48
49 /*
50 * ia64_cpu_new():
51 *
52 * Create a new IA64 CPU object by filling the CPU struct.
53 * Return 1 on success, 0 if cpu_type_name isn't a valid IA64 processor.
54 */
55 int ia64_cpu_new(struct cpu *cpu, struct memory *mem,
56 struct machine *machine, int cpu_id, char *cpu_type_name)
57 {
58 if (strcasecmp(cpu_type_name, "IA64") != 0)
59 return 0;
60
61 cpu->memory_rw = ia64_memory_rw;
62 cpu->update_translation_table = ia64_update_translation_table;
63 cpu->invalidate_translation_caches =
64 ia64_invalidate_translation_caches;
65 cpu->invalidate_code_translation = ia64_invalidate_code_translation;
66 cpu->is_32bit = 0;
67
68 /* Only show name and caches etc for CPU nr 0: */
69 if (cpu_id == 0) {
70 debug("%s", cpu->name);
71 }
72
73 return 1;
74 }
75
76
77 /*
78 * ia64_cpu_dumpinfo():
79 */
80 void ia64_cpu_dumpinfo(struct cpu *cpu)
81 {
82 /* TODO */
83 debug("\n");
84 }
85
86
87 /*
88 * ia64_cpu_list_available_types():
89 *
90 * Print a list of available IA64 CPU types.
91 */
92 void ia64_cpu_list_available_types(void)
93 {
94 /* TODO */
95
96 debug("IA64\n");
97 }
98
99
100 /*
101 * ia64_cpu_register_match():
102 */
103 void ia64_cpu_register_match(struct machine *m, char *name,
104 int writeflag, uint64_t *valuep, int *match_register)
105 {
106 int cpunr = 0;
107
108 /* CPU number: */
109
110 /* TODO */
111
112 if (strcasecmp(name, "pc") == 0) {
113 if (writeflag) {
114 m->cpus[cpunr]->pc = *valuep;
115 } else
116 *valuep = m->cpus[cpunr]->pc;
117 *match_register = 1;
118 }
119
120 /* TODO */
121 }
122
123
124 /*
125 * ia64_cpu_register_dump():
126 *
127 * Dump cpu registers in a relatively readable format.
128 *
129 * gprs: set to non-zero to dump GPRs and some special-purpose registers.
130 * coprocs: set bit 0..3 to dump registers in coproc 0..3.
131 */
132 void ia64_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs)
133 {
134 char *symbol;
135 uint64_t offset;
136 int x = cpu->cpu_id;
137
138 if (gprs) {
139 symbol = get_symbol_name(&cpu->machine->symbol_context,
140 cpu->pc, &offset);
141 debug("cpu%i:\t pc = 0x%016llx", x, (long long)cpu->pc);
142 debug(" <%s>\n", symbol != NULL? symbol : " no symbol ");
143
144 /* TODO */
145 }
146 }
147
148
149 /*
150 * ia64_cpu_interrupt():
151 */
152 int ia64_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr)
153 {
154 fatal("ia64_cpu_interrupt(): TODO\n");
155 return 0;
156 }
157
158
159 /*
160 * ia64_cpu_interrupt_ack():
161 */
162 int ia64_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr)
163 {
164 /* fatal("ia64_cpu_interrupt_ack(): TODO\n"); */
165 return 0;
166 }
167
168
169 /*
170 * ia64_cpu_disassemble_instr():
171 *
172 * Convert an instruction word into human readable format, for instruction
173 * tracing.
174 *
175 * If running is 1, cpu->pc should be the address of the instruction.
176 *
177 * If running is 0, things that depend on the runtime environment (eg.
178 * register contents) will not be shown, and addr will be used instead of
179 * cpu->pc for relative addresses.
180 */
181 int ia64_cpu_disassemble_instr(struct cpu *cpu, unsigned char *ib,
182 int running, uint64_t dumpaddr, int bintrans)
183 {
184 uint64_t offset;
185 char *symbol;
186
187 if (running)
188 dumpaddr = cpu->pc;
189
190 symbol = get_symbol_name(&cpu->machine->symbol_context,
191 dumpaddr, &offset);
192 if (symbol != NULL && offset == 0)
193 debug("<%s>\n", symbol);
194
195 if (cpu->machine->ncpus > 1 && running)
196 debug("cpu%i:\t", cpu->cpu_id);
197
198 debug("%016llx: ", (long long)dumpaddr);
199
200 debug("TODO\n");
201
202 /* iw = ib[0] + (ib[1]<<8) + (ib[2]<<16) + (ib[3]<<24); */
203
204 return 16;
205 }
206
207
208 #include "tmp_ia64_tail.c"
209

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