/[gxemul]/trunk/src/cpus/cpu_ia64.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Annotation of /trunk/src/cpus/cpu_ia64.c

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Revision 28 - (hide annotations)
Mon Oct 8 16:20:26 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 5776 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1298 2006/07/22 11:27:46 debug Exp $
20060626	Continuing on SPARC emulation (beginning on the 'save'
		instruction, register windows, etc).
20060629	Planning statistics gathering (new -s command line option),
		and renaming speed_tricks to allow_instruction_combinations.
20060630	Some minor manual page updates.
		Various cleanups.
		Implementing the -s command line option.
20060701	FINALLY found the bug which prevented Linux and Ultrix from
		running without the ugly hack in the R2000/R3000 cache isol
		code; it was the phystranslation hint array which was buggy.
		Removing the phystranslation hint code completely, for now.
20060702	Minor dyntrans cleanups; invalidation of physpages now only
		invalidate those parts of a page that have actually been
		translated. (32 parts per page.)
		Some MIPS non-R3000 speed fixes.
		Experimenting with MIPS instruction combination for some
		addiu+bne+sw loops, and sw+sw+sw.
		Adding support (again) for larger-than-4KB pages in MIPS tlbw*.
		Continuing on SPARC emulation: adding load/store instructions.
20060704	Fixing a virtual vs physical page shift bug in the new tlbw*
		implementation. Problem noticed by Jakub Jermar. (Many thanks.)
		Moving rfe and eret to cpu_mips_instr.c, since that is the
		only place that uses them nowadays.
20060705	Removing the BSD license from the "testmachine" include files,
		placing them in the public domain instead; this enables the
		testmachine stuff to be used from projects which are
		incompatible with the BSD license for some reason.
20060707	Adding instruction combinations for the R2000/R3000 L1
		I-cache invalidation code used by NetBSD/pmax 3.0, lui+addiu,
		various branches followed by addiu or nop, and jr ra followed
		by addiu. The time it takes to perform a full NetBSD/pmax R3000
		install on the laptop has dropped from 573 seconds to 539. :-)
20060708	Adding a framebuffer controller device (dev_fbctrl), which so
		far can be used to change the fb resolution during runtime, but
		in the future will also be useful for accelerated block fill/
		copy, and possibly also simplified character output.
		Adding an instruction combination for NetBSD/pmax' strlen.
20060709	Minor fixes: reading raw files in src/file.c wasn't memblock
		aligned, removing buggy multi_sw MIPS instruction combination,
		etc.
20060711	Adding a machine_qemu.c, which contains a "qemu_mips" machine.
		(It mimics QEMU's MIPS machine mode, so that a test kernel
		made for QEMU_MIPS also can run in GXemul... at least to some
		extent.)  Adding a short section about how to run this mode to
		doc/guestoses.html.
20060714	Misc. minor code cleanups.
20060715	Applying a patch which adds getchar() to promemul/yamon.c
		(from Oleksandr Tymoshenko).
		Adding yamon.h from NetBSD, and rewriting yamon.c to use it
		(instead of ugly hardcoded numbers) + some cleanup.
20060716	Found and fixed the bug which broke single-stepping of 64-bit
		programs between 0.4.0 and 0.4.0.1 (caused by too quick
		refactoring and no testing). Hopefully this fix will not
		break too many other things.
20060718	Continuing on the 8253 PIT; it now works with Linux/QEMU_MIPS.
		Re-adding the sw+sw+sw instr comb (the problem was that I had
		ignored endian issues); however, it doesn't seem to give any
		big performance gain.
20060720	Adding a dummy Transputer mode (T414, T800 etc) skeleton (only
		the 'j' and 'ldc' instructions are implemented so far). :-}
20060721	Adding gtreg.h from NetBSD, updating dev_gt.c to use it, plus
		misc. other updates to get Linux 2.6 for evbmips/malta working
		(thanks to Alec Voropay for the details).
		FINALLY found and fixed the bug which made tlbw* for non-R3000
		buggy; it was a reference count problem in the dyntrans core.
20060722	Testing stuff; things seem stable enough for a new release.

==============  RELEASE 0.4.1  ==============


1 dpavlin 14 /*
2 dpavlin 24 * Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
3 dpavlin 14 *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 28 * $Id: cpu_ia64.c,v 1.13 2006/07/16 13:32:26 debug Exp $
29 dpavlin 14 *
30     * IA64 CPU emulation.
31     *
32     * TODO: Everything.
33     */
34    
35     #include <stdio.h>
36     #include <stdlib.h>
37     #include <string.h>
38     #include <ctype.h>
39    
40     #include "cpu.h"
41     #include "machine.h"
42     #include "memory.h"
43     #include "misc.h"
44     #include "symbol.h"
45    
46     #include "tmp_ia64_head.c"
47    
48    
49     /*
50     * ia64_cpu_new():
51     *
52     * Create a new IA64 CPU object by filling the CPU struct.
53     * Return 1 on success, 0 if cpu_type_name isn't a valid IA64 processor.
54     */
55     int ia64_cpu_new(struct cpu *cpu, struct memory *mem,
56     struct machine *machine, int cpu_id, char *cpu_type_name)
57     {
58     if (strcasecmp(cpu_type_name, "IA64") != 0)
59     return 0;
60    
61 dpavlin 28 cpu->run_instr = ia64_run_instr;
62 dpavlin 14 cpu->memory_rw = ia64_memory_rw;
63     cpu->update_translation_table = ia64_update_translation_table;
64 dpavlin 18 cpu->invalidate_translation_caches =
65     ia64_invalidate_translation_caches;
66 dpavlin 14 cpu->invalidate_code_translation = ia64_invalidate_code_translation;
67     cpu->is_32bit = 0;
68    
69     /* Only show name and caches etc for CPU nr 0: */
70     if (cpu_id == 0) {
71     debug("%s", cpu->name);
72     }
73    
74     return 1;
75     }
76    
77    
78     /*
79     * ia64_cpu_dumpinfo():
80     */
81     void ia64_cpu_dumpinfo(struct cpu *cpu)
82     {
83     /* TODO */
84     debug("\n");
85     }
86    
87    
88     /*
89     * ia64_cpu_list_available_types():
90     *
91     * Print a list of available IA64 CPU types.
92     */
93     void ia64_cpu_list_available_types(void)
94     {
95     /* TODO */
96    
97     debug("IA64\n");
98     }
99    
100    
101     /*
102     * ia64_cpu_register_match():
103     */
104     void ia64_cpu_register_match(struct machine *m, char *name,
105     int writeflag, uint64_t *valuep, int *match_register)
106     {
107     int cpunr = 0;
108    
109     /* CPU number: */
110    
111     /* TODO */
112    
113     if (strcasecmp(name, "pc") == 0) {
114     if (writeflag) {
115     m->cpus[cpunr]->pc = *valuep;
116     } else
117     *valuep = m->cpus[cpunr]->pc;
118     *match_register = 1;
119     }
120    
121     /* TODO */
122     }
123    
124    
125     /*
126     * ia64_cpu_register_dump():
127     *
128     * Dump cpu registers in a relatively readable format.
129     *
130     * gprs: set to non-zero to dump GPRs and some special-purpose registers.
131     * coprocs: set bit 0..3 to dump registers in coproc 0..3.
132     */
133     void ia64_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs)
134     {
135     char *symbol;
136     uint64_t offset;
137     int x = cpu->cpu_id;
138    
139     if (gprs) {
140     symbol = get_symbol_name(&cpu->machine->symbol_context,
141     cpu->pc, &offset);
142 dpavlin 24 debug("cpu%i:\t pc = 0x%016"PRIx64, x, (uint64_t)cpu->pc);
143 dpavlin 14 debug(" <%s>\n", symbol != NULL? symbol : " no symbol ");
144    
145     /* TODO */
146     }
147     }
148    
149    
150     /*
151 dpavlin 24 * mips_cpu_tlbdump():
152     *
153     * Called from the debugger to dump the TLB in a readable format.
154     * x is the cpu number to dump, or -1 to dump all CPUs.
155     *
156     * If rawflag is nonzero, then the TLB contents isn't formated nicely,
157     * just dumped.
158     */
159     void ia64_cpu_tlbdump(struct machine *m, int x, int rawflag)
160     {
161     }
162    
163    
164     /*
165     * ia64_cpu_gdb_stub():
166     *
167     * Execute a "remote GDB" command. Returns a newly allocated response string
168     * on success, NULL on failure.
169     */
170     char *ia64_cpu_gdb_stub(struct cpu *cpu, char *cmd)
171     {
172     fatal("ia64_cpu_gdb_stub(): TODO\n");
173     return NULL;
174     }
175    
176    
177     /*
178 dpavlin 14 * ia64_cpu_interrupt():
179     */
180     int ia64_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr)
181     {
182     fatal("ia64_cpu_interrupt(): TODO\n");
183     return 0;
184     }
185    
186    
187     /*
188     * ia64_cpu_interrupt_ack():
189     */
190     int ia64_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr)
191     {
192     /* fatal("ia64_cpu_interrupt_ack(): TODO\n"); */
193     return 0;
194     }
195    
196    
197     /*
198     * ia64_cpu_disassemble_instr():
199     *
200     * Convert an instruction word into human readable format, for instruction
201     * tracing.
202     *
203     * If running is 1, cpu->pc should be the address of the instruction.
204     *
205     * If running is 0, things that depend on the runtime environment (eg.
206     * register contents) will not be shown, and addr will be used instead of
207     * cpu->pc for relative addresses.
208     */
209     int ia64_cpu_disassemble_instr(struct cpu *cpu, unsigned char *ib,
210 dpavlin 24 int running, uint64_t dumpaddr)
211 dpavlin 14 {
212     uint64_t offset;
213     char *symbol;
214    
215     if (running)
216     dumpaddr = cpu->pc;
217    
218     symbol = get_symbol_name(&cpu->machine->symbol_context,
219     dumpaddr, &offset);
220     if (symbol != NULL && offset == 0)
221     debug("<%s>\n", symbol);
222    
223     if (cpu->machine->ncpus > 1 && running)
224     debug("cpu%i:\t", cpu->cpu_id);
225    
226 dpavlin 24 debug("%016"PRIx64": ", (uint64_t) dumpaddr);
227 dpavlin 14
228     debug("TODO\n");
229    
230     /* iw = ib[0] + (ib[1]<<8) + (ib[2]<<16) + (ib[3]<<24); */
231    
232     return 16;
233     }
234    
235    
236     #include "tmp_ia64_tail.c"
237    

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