/[gxemul]/trunk/src/cpus/cpu_i960.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Contents of /trunk/src/cpus/cpu_i960.c

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Revision 28 - (show annotations)
Mon Oct 8 16:20:26 2007 UTC (12 years, 8 months ago) by dpavlin
File MIME type: text/plain
File size: 6187 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1298 2006/07/22 11:27:46 debug Exp $
20060626	Continuing on SPARC emulation (beginning on the 'save'
		instruction, register windows, etc).
20060629	Planning statistics gathering (new -s command line option),
		and renaming speed_tricks to allow_instruction_combinations.
20060630	Some minor manual page updates.
		Various cleanups.
		Implementing the -s command line option.
20060701	FINALLY found the bug which prevented Linux and Ultrix from
		running without the ugly hack in the R2000/R3000 cache isol
		code; it was the phystranslation hint array which was buggy.
		Removing the phystranslation hint code completely, for now.
20060702	Minor dyntrans cleanups; invalidation of physpages now only
		invalidate those parts of a page that have actually been
		translated. (32 parts per page.)
		Some MIPS non-R3000 speed fixes.
		Experimenting with MIPS instruction combination for some
		addiu+bne+sw loops, and sw+sw+sw.
		Adding support (again) for larger-than-4KB pages in MIPS tlbw*.
		Continuing on SPARC emulation: adding load/store instructions.
20060704	Fixing a virtual vs physical page shift bug in the new tlbw*
		implementation. Problem noticed by Jakub Jermar. (Many thanks.)
		Moving rfe and eret to cpu_mips_instr.c, since that is the
		only place that uses them nowadays.
20060705	Removing the BSD license from the "testmachine" include files,
		placing them in the public domain instead; this enables the
		testmachine stuff to be used from projects which are
		incompatible with the BSD license for some reason.
20060707	Adding instruction combinations for the R2000/R3000 L1
		I-cache invalidation code used by NetBSD/pmax 3.0, lui+addiu,
		various branches followed by addiu or nop, and jr ra followed
		by addiu. The time it takes to perform a full NetBSD/pmax R3000
		install on the laptop has dropped from 573 seconds to 539. :-)
20060708	Adding a framebuffer controller device (dev_fbctrl), which so
		far can be used to change the fb resolution during runtime, but
		in the future will also be useful for accelerated block fill/
		copy, and possibly also simplified character output.
		Adding an instruction combination for NetBSD/pmax' strlen.
20060709	Minor fixes: reading raw files in src/file.c wasn't memblock
		aligned, removing buggy multi_sw MIPS instruction combination,
		etc.
20060711	Adding a machine_qemu.c, which contains a "qemu_mips" machine.
		(It mimics QEMU's MIPS machine mode, so that a test kernel
		made for QEMU_MIPS also can run in GXemul... at least to some
		extent.)  Adding a short section about how to run this mode to
		doc/guestoses.html.
20060714	Misc. minor code cleanups.
20060715	Applying a patch which adds getchar() to promemul/yamon.c
		(from Oleksandr Tymoshenko).
		Adding yamon.h from NetBSD, and rewriting yamon.c to use it
		(instead of ugly hardcoded numbers) + some cleanup.
20060716	Found and fixed the bug which broke single-stepping of 64-bit
		programs between 0.4.0 and 0.4.0.1 (caused by too quick
		refactoring and no testing). Hopefully this fix will not
		break too many other things.
20060718	Continuing on the 8253 PIT; it now works with Linux/QEMU_MIPS.
		Re-adding the sw+sw+sw instr comb (the problem was that I had
		ignored endian issues); however, it doesn't seem to give any
		big performance gain.
20060720	Adding a dummy Transputer mode (T414, T800 etc) skeleton (only
		the 'j' and 'ldc' instructions are implemented so far). :-}
20060721	Adding gtreg.h from NetBSD, updating dev_gt.c to use it, plus
		misc. other updates to get Linux 2.6 for evbmips/malta working
		(thanks to Alec Voropay for the details).
		FINALLY found and fixed the bug which made tlbw* for non-R3000
		buggy; it was a reference count problem in the dyntrans core.
20060722	Testing stuff; things seem stable enough for a new release.

==============  RELEASE 0.4.1  ==============


1 /*
2 * Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: cpu_i960.c,v 1.11 2006/07/20 21:52:59 debug Exp $
29 *
30 * Intel i960 CPU emulation.
31 */
32
33 #include <stdio.h>
34 #include <stdlib.h>
35 #include <string.h>
36 #include <ctype.h>
37
38 #include "cpu.h"
39 #include "machine.h"
40 #include "memory.h"
41 #include "misc.h"
42 #include "symbol.h"
43
44 #define DYNTRANS_32
45 #define DYNTRANS_VARIABLE_INSTRUCTION_LENGTH
46 #include "tmp_i960_head.c"
47
48
49 /*
50 * i960_cpu_new():
51 *
52 * Create a new I960 cpu object.
53 *
54 * Returns 1 on success, 0 if there was no matching I960 processor with
55 * this cpu_type_name.
56 */
57 int i960_cpu_new(struct cpu *cpu, struct memory *mem, struct machine *machine,
58 int cpu_id, char *cpu_type_name)
59 {
60 if (strcasecmp(cpu_type_name, "i960") != 0)
61 return 0;
62
63 cpu->run_instr = i960_run_instr;
64 cpu->memory_rw = i960_memory_rw;
65 cpu->update_translation_table = i960_update_translation_table;
66 cpu->invalidate_translation_caches =
67 i960_invalidate_translation_caches;
68 cpu->invalidate_code_translation = i960_invalidate_code_translation;
69 cpu->is_32bit = 1;
70
71 cpu->byte_order = EMUL_BIG_ENDIAN;
72
73 /* Only show name and caches etc for CPU nr 0 (in SMP machines): */
74 if (cpu_id == 0) {
75 debug("%s", cpu->name);
76 }
77
78 return 1;
79 }
80
81
82 /*
83 * i960_cpu_list_available_types():
84 *
85 * Print a list of available I960 CPU types.
86 */
87 void i960_cpu_list_available_types(void)
88 {
89 debug("i960\n");
90 /* TODO */
91 }
92
93
94 /*
95 * i960_cpu_dumpinfo():
96 */
97 void i960_cpu_dumpinfo(struct cpu *cpu)
98 {
99 /* TODO */
100 debug("\n");
101 }
102
103
104 /*
105 * i960_cpu_register_dump():
106 *
107 * Dump cpu registers in a relatively readable format.
108 *
109 * gprs: set to non-zero to dump GPRs and some special-purpose registers.
110 * coprocs: set bit 0..3 to dump registers in coproc 0..3.
111 */
112 void i960_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs)
113 {
114 char *symbol;
115 uint64_t offset;
116 int x = cpu->cpu_id;
117
118 if (gprs) {
119 /* Special registers (pc, ...) first: */
120 symbol = get_symbol_name(&cpu->machine->symbol_context,
121 cpu->pc, &offset);
122
123 debug("cpu%i: pc = 0x%08"PRIx32, x, (uint32_t)cpu->pc);
124 debug(" <%s>\n", symbol != NULL? symbol : " no symbol ");
125 }
126 }
127
128
129 /*
130 * i960_cpu_register_match():
131 */
132 void i960_cpu_register_match(struct machine *m, char *name,
133 int writeflag, uint64_t *valuep, int *match_register)
134 {
135 int cpunr = 0;
136
137 /* CPU number: */
138
139 /* TODO */
140
141 /* Register name: */
142 if (strcasecmp(name, "pc") == 0) {
143 if (writeflag) {
144 m->cpus[cpunr]->pc = *valuep;
145 } else
146 *valuep = m->cpus[cpunr]->pc;
147 *match_register = 1;
148 }
149 }
150
151
152 /*
153 * i960_cpu_tlbdump():
154 *
155 * Called from the debugger to dump the TLB in a readable format.
156 * x is the cpu number to dump, or -1 to dump all CPUs.
157 *
158 * If rawflag is nonzero, then the TLB contents isn't formated nicely,
159 * just dumped.
160 */
161 void i960_cpu_tlbdump(struct machine *m, int x, int rawflag)
162 {
163 }
164
165
166 /*
167 * i960_cpu_gdb_stub():
168 *
169 * Execute a "remote GDB" command. Returns a newly allocated response string
170 * on success, NULL on failure.
171 */
172 char *i960_cpu_gdb_stub(struct cpu *cpu, char *cmd)
173 {
174 fatal("i960_cpu_gdb_stub(): TODO\n");
175 return NULL;
176 }
177
178
179 /*
180 * i960_cpu_interrupt():
181 */
182 int i960_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr)
183 {
184 fatal("i960_cpu_interrupt(): TODO\n");
185 return 0;
186 }
187
188
189 /*
190 * i960_cpu_interrupt_ack():
191 */
192 int i960_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr)
193 {
194 /* fatal("i960_cpu_interrupt_ack(): TODO\n"); */
195 return 0;
196 }
197
198
199 /* Helper functions: */
200 static void print_four(unsigned char *instr, int *len)
201 { debug(" %02x%02x%02x%02x", instr[*len], instr[*len+1],
202 instr[*len+2], instr[*len+3]); (*len) += 4; }
203 static void print_spaces(int len) { int i; debug(" "); for (i=0; i<16-len/2*5;
204 i++) debug(" "); }
205
206
207 /*
208 * i960_cpu_disassemble_instr():
209 *
210 * Convert an instruction word into human readable format, for instruction
211 * tracing.
212 *
213 * If running is 1, cpu->pc should be the address of the instruction.
214 *
215 * If running is 0, things that depend on the runtime environment (eg.
216 * register contents) will not be shown, and addr will be used instead of
217 * cpu->pc for relative addresses.
218 */
219 int i960_cpu_disassemble_instr(struct cpu *cpu, unsigned char *ib,
220 int running, uint64_t dumpaddr)
221 {
222 uint64_t offset;
223 int len = 0;
224 char *symbol;
225
226 if (running)
227 dumpaddr = cpu->pc;
228
229 symbol = get_symbol_name(&cpu->machine->symbol_context,
230 dumpaddr, &offset);
231 if (symbol != NULL && offset==0)
232 debug("<%s>\n", symbol);
233
234 if (cpu->machine->ncpus > 1 && running)
235 debug("cpu%i: ", cpu->cpu_id);
236
237 debug("0x%08x: ", (int)dumpaddr);
238
239 print_four(ib, &len);
240
241 /* TODO */
242 print_spaces(len);
243 debug("UNIMPLEMENTED 0x%02x%02x\n", ib[0], ib[1]);
244
245 return len;
246 }
247
248
249 #include "tmp_i960_tail.c"
250

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