/[gxemul]/trunk/src/cpus/cpu_hppa.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Annotation of /trunk/src/cpus/cpu_hppa.c

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Revision 28 - (hide annotations)
Mon Oct 8 16:20:26 2007 UTC (13 years, 3 months ago) by dpavlin
File MIME type: text/plain
File size: 7197 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1298 2006/07/22 11:27:46 debug Exp $
20060626	Continuing on SPARC emulation (beginning on the 'save'
		instruction, register windows, etc).
20060629	Planning statistics gathering (new -s command line option),
		and renaming speed_tricks to allow_instruction_combinations.
20060630	Some minor manual page updates.
		Various cleanups.
		Implementing the -s command line option.
20060701	FINALLY found the bug which prevented Linux and Ultrix from
		running without the ugly hack in the R2000/R3000 cache isol
		code; it was the phystranslation hint array which was buggy.
		Removing the phystranslation hint code completely, for now.
20060702	Minor dyntrans cleanups; invalidation of physpages now only
		invalidate those parts of a page that have actually been
		translated. (32 parts per page.)
		Some MIPS non-R3000 speed fixes.
		Experimenting with MIPS instruction combination for some
		addiu+bne+sw loops, and sw+sw+sw.
		Adding support (again) for larger-than-4KB pages in MIPS tlbw*.
		Continuing on SPARC emulation: adding load/store instructions.
20060704	Fixing a virtual vs physical page shift bug in the new tlbw*
		implementation. Problem noticed by Jakub Jermar. (Many thanks.)
		Moving rfe and eret to cpu_mips_instr.c, since that is the
		only place that uses them nowadays.
20060705	Removing the BSD license from the "testmachine" include files,
		placing them in the public domain instead; this enables the
		testmachine stuff to be used from projects which are
		incompatible with the BSD license for some reason.
20060707	Adding instruction combinations for the R2000/R3000 L1
		I-cache invalidation code used by NetBSD/pmax 3.0, lui+addiu,
		various branches followed by addiu or nop, and jr ra followed
		by addiu. The time it takes to perform a full NetBSD/pmax R3000
		install on the laptop has dropped from 573 seconds to 539. :-)
20060708	Adding a framebuffer controller device (dev_fbctrl), which so
		far can be used to change the fb resolution during runtime, but
		in the future will also be useful for accelerated block fill/
		copy, and possibly also simplified character output.
		Adding an instruction combination for NetBSD/pmax' strlen.
20060709	Minor fixes: reading raw files in src/file.c wasn't memblock
		aligned, removing buggy multi_sw MIPS instruction combination,
		etc.
20060711	Adding a machine_qemu.c, which contains a "qemu_mips" machine.
		(It mimics QEMU's MIPS machine mode, so that a test kernel
		made for QEMU_MIPS also can run in GXemul... at least to some
		extent.)  Adding a short section about how to run this mode to
		doc/guestoses.html.
20060714	Misc. minor code cleanups.
20060715	Applying a patch which adds getchar() to promemul/yamon.c
		(from Oleksandr Tymoshenko).
		Adding yamon.h from NetBSD, and rewriting yamon.c to use it
		(instead of ugly hardcoded numbers) + some cleanup.
20060716	Found and fixed the bug which broke single-stepping of 64-bit
		programs between 0.4.0 and 0.4.0.1 (caused by too quick
		refactoring and no testing). Hopefully this fix will not
		break too many other things.
20060718	Continuing on the 8253 PIT; it now works with Linux/QEMU_MIPS.
		Re-adding the sw+sw+sw instr comb (the problem was that I had
		ignored endian issues); however, it doesn't seem to give any
		big performance gain.
20060720	Adding a dummy Transputer mode (T414, T800 etc) skeleton (only
		the 'j' and 'ldc' instructions are implemented so far). :-}
20060721	Adding gtreg.h from NetBSD, updating dev_gt.c to use it, plus
		misc. other updates to get Linux 2.6 for evbmips/malta working
		(thanks to Alec Voropay for the details).
		FINALLY found and fixed the bug which made tlbw* for non-R3000
		buggy; it was a reference count problem in the dyntrans core.
20060722	Testing stuff; things seem stable enough for a new release.

==============  RELEASE 0.4.1  ==============


1 dpavlin 14 /*
2 dpavlin 24 * Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
3 dpavlin 14 *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 dpavlin 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 dpavlin 14 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 28 * $Id: cpu_hppa.c,v 1.15 2006/07/16 13:32:26 debug Exp $
29 dpavlin 14 *
30     * HP PA-RISC CPU emulation.
31     *
32     * TODO
33     */
34    
35     #include <stdio.h>
36     #include <stdlib.h>
37     #include <string.h>
38     #include <ctype.h>
39    
40     #include "cpu.h"
41     #include "machine.h"
42     #include "memory.h"
43     #include "misc.h"
44     #include "symbol.h"
45    
46    
47     #define DYNTRANS_DUALMODE_32
48     #include "tmp_hppa_head.c"
49    
50    
51     /*
52     * hppa_cpu_new():
53     *
54     * Create a new HPPA cpu object.
55     *
56     * Returns 1 on success, 0 if there was no matching HPPA processor with
57     * this cpu_type_name.
58     */
59     int hppa_cpu_new(struct cpu *cpu, struct memory *mem, struct machine *machine,
60     int cpu_id, char *cpu_type_name)
61     {
62     if (strcasecmp(cpu_type_name, "HPPA") != 0)
63     return 0;
64    
65     cpu->memory_rw = hppa_memory_rw;
66    
67     /* TODO: per CPU type? */
68     cpu->byte_order = EMUL_LITTLE_ENDIAN;
69     cpu->is_32bit = 1;
70     cpu->cd.hppa.bits = 32;
71    
72     if (cpu->is_32bit) {
73 dpavlin 28 cpu->run_instr = hppa32_run_instr;
74 dpavlin 14 cpu->update_translation_table = hppa32_update_translation_table;
75 dpavlin 18 cpu->invalidate_translation_caches =
76     hppa32_invalidate_translation_caches;
77 dpavlin 14 cpu->invalidate_code_translation =
78     hppa32_invalidate_code_translation;
79     } else {
80 dpavlin 28 cpu->run_instr = hppa_run_instr;
81 dpavlin 14 cpu->update_translation_table = hppa_update_translation_table;
82 dpavlin 18 cpu->invalidate_translation_caches =
83     hppa_invalidate_translation_caches;
84 dpavlin 14 cpu->invalidate_code_translation =
85     hppa_invalidate_code_translation;
86     }
87    
88 dpavlin 20 /* Only show name and caches etc for CPU nr 0 (in SMP machines): */
89 dpavlin 14 if (cpu_id == 0) {
90     debug("%s", cpu->name);
91     }
92    
93     return 1;
94     }
95    
96    
97     /*
98     * hppa_cpu_list_available_types():
99     *
100     * Print a list of available HPPA CPU types.
101     */
102     void hppa_cpu_list_available_types(void)
103     {
104     debug("HPPA\n");
105     /* TODO */
106     }
107    
108    
109     /*
110     * hppa_cpu_dumpinfo():
111     */
112     void hppa_cpu_dumpinfo(struct cpu *cpu)
113     {
114     debug("\n");
115     /* TODO */
116     }
117    
118    
119     /*
120     * hppa_cpu_register_dump():
121     *
122     * Dump cpu registers in a relatively readable format.
123     *
124     * gprs: set to non-zero to dump GPRs and some special-purpose registers.
125     * coprocs: set bit 0..3 to dump registers in coproc 0..3.
126     */
127     void hppa_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs)
128     {
129     char *symbol;
130 dpavlin 20 uint64_t offset;
131 dpavlin 14 int i, x = cpu->cpu_id, nregs = 32;
132     int bits32 = cpu->cd.hppa.bits == 32;
133    
134     if (gprs) {
135     /* Special registers (pc, ...) first: */
136     symbol = get_symbol_name(&cpu->machine->symbol_context,
137     cpu->pc, &offset);
138    
139     debug("cpu%i: pc = 0x", x);
140     if (bits32)
141 dpavlin 24 debug("%08"PRIx32, (uint32_t) cpu->pc);
142 dpavlin 14 else
143 dpavlin 24 debug("%016"PRIx64, (uint64_t) cpu->pc);
144 dpavlin 14 debug(" <%s>\n", symbol != NULL? symbol : " no symbol ");
145    
146     if (bits32) {
147     /* 32-bit: */
148     for (i=0; i<nregs; i++) {
149     if ((i % 4) == 0)
150     debug("cpu%i:", x);
151 dpavlin 24 debug(" r%02i = 0x%08"PRIx32" ", i,
152     (uint32_t)cpu->cd.hppa.r[i]);
153 dpavlin 14 if ((i % 4) == 3)
154     debug("\n");
155     }
156     } else {
157     /* 64-bit: */
158     for (i=0; i<nregs; i++) {
159     int r = (i >> 1) + ((i & 1) << 4);
160     if ((i % 2) == 0)
161     debug("cpu%i:", x);
162 dpavlin 24 debug(" r%02i = 0x%016"PRIx64" ", r,
163     (uint64_t) cpu->cd.hppa.r[r]);
164 dpavlin 14 if ((i % 2) == 1)
165     debug("\n");
166     }
167     }
168     }
169     }
170    
171    
172     /*
173     * hppa_cpu_register_match():
174     */
175     void hppa_cpu_register_match(struct machine *m, char *name,
176     int writeflag, uint64_t *valuep, int *match_register)
177     {
178     int cpunr = 0;
179    
180     /* CPU number: */
181    
182     /* TODO */
183    
184     /* Register name: */
185     if (strcasecmp(name, "pc") == 0) {
186     if (writeflag) {
187     m->cpus[cpunr]->pc = *valuep;
188     } else
189     *valuep = m->cpus[cpunr]->pc;
190     *match_register = 1;
191     }
192     }
193    
194    
195     /*
196 dpavlin 24 * hppa_cpu_tlbdump():
197     *
198     * Called from the debugger to dump the TLB in a readable format.
199     * x is the cpu number to dump, or -1 to dump all CPUs.
200     *
201     * If rawflag is nonzero, then the TLB contents isn't formated nicely,
202     * just dumped.
203     */
204     void hppa_cpu_tlbdump(struct machine *m, int x, int rawflag)
205     {
206     }
207    
208    
209     /*
210     * hppa_cpu_gdb_stub():
211     *
212     * Execute a "remote GDB" command. Returns a newly allocated response string
213     * on success, NULL on failure.
214     */
215     char *hppa_cpu_gdb_stub(struct cpu *cpu, char *cmd)
216     {
217     fatal("hppa_cpu_gdb_stub(): TODO\n");
218     return NULL;
219     }
220    
221    
222     /*
223 dpavlin 14 * hppa_cpu_interrupt():
224     */
225     int hppa_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr)
226     {
227     fatal("hppa_cpu_interrupt(): TODO\n");
228     return 0;
229     }
230    
231    
232     /*
233     * hppa_cpu_interrupt_ack():
234     */
235     int hppa_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr)
236     {
237     /* fatal("hppa_cpu_interrupt_ack(): TODO\n"); */
238     return 0;
239     }
240    
241    
242     /*
243     * hppa_cpu_disassemble_instr():
244     *
245     * Convert an instruction word into human readable format, for instruction
246     * tracing.
247     *
248 dpavlin 20 * If running is 1, cpu->pc should be the address of the instruction.
249 dpavlin 14 *
250     * If running is 0, things that depend on the runtime environment (eg.
251 dpavlin 20 * register contents) will not be shown, and addr will be used instead of
252 dpavlin 14 * cpu->pc for relative addresses.
253     */
254     int hppa_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr,
255 dpavlin 24 int running, uint64_t dumpaddr)
256 dpavlin 14 {
257 dpavlin 20 uint64_t offset;
258 dpavlin 14 uint32_t iword;
259 dpavlin 20 char *symbol;
260 dpavlin 14
261     if (running)
262     dumpaddr = cpu->pc;
263    
264     symbol = get_symbol_name(&cpu->machine->symbol_context,
265     dumpaddr, &offset);
266     if (symbol != NULL && offset==0)
267     debug("<%s>\n", symbol);
268    
269     if (cpu->machine->ncpus > 1 && running)
270     debug("cpu%i: ", cpu->cpu_id);
271    
272     if (cpu->cd.hppa.bits == 32)
273 dpavlin 24 debug("%08"PRIx32, (uint32_t) dumpaddr);
274 dpavlin 14 else
275 dpavlin 24 debug("%016"PRIx64, (uint64_t) dumpaddr);
276 dpavlin 14
277     if (cpu->byte_order == EMUL_BIG_ENDIAN)
278     iword = (instr[0] << 24) + (instr[1] << 16) + (instr[2] << 8)
279     + instr[3];
280     else
281     iword = (instr[3] << 24) + (instr[2] << 16) + (instr[1] << 8)
282     + instr[0];
283    
284 dpavlin 24 debug(": %08"PRIx32"\t", (uint32_t) iword);
285 dpavlin 14
286     /*
287     * Decode the instruction:
288     */
289    
290     debug("TODO\n");
291    
292     return sizeof(iword);
293     }
294    
295    
296     #include "tmp_hppa_tail.c"
297    

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