25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: cpu_dyntrans.c,v 1.54 2006/02/09 22:55:20 debug Exp $ |
* $Id: cpu_dyntrans.c,v 1.99 2006/06/23 20:43:44 debug Exp $ |
29 |
* |
* |
30 |
* Common dyntrans routines. Included from cpu_*.c. |
* Common dyntrans routines. Included from cpu_*.c. |
31 |
*/ |
*/ |
100 |
if (array_16kpage_in_use[i]) { |
if (array_16kpage_in_use[i]) { |
101 |
for (j=0; j<16384; j++) |
for (j=0; j<16384; j++) |
102 |
if (array[i*16384 + j] > 0) |
if (array[i*16384 + j] > 0) |
103 |
fprintf(f, "%lli\t0x%016llx\n", |
fprintf(f, "%lli\t" |
104 |
(long long)array[i*16384+j], |
"0x%016"PRIx64"\n", |
105 |
(long long)((i*16384+j) << |
(uint64_t)array[i*16384+j], |
106 |
DYNTRANS_INSTR_ALIGNMENT_SHIFT)); |
(uint64_t)((i*16384+j) << |
107 |
|
DYNTRANS_INSTR_ALIGNMENT_SHIFT)); |
108 |
} |
} |
109 |
fclose(f); |
fclose(f); |
110 |
printf("n=0x%08x\n", n); |
printf("n=0x%08x\n", n); |
113 |
} |
} |
114 |
#endif /* PC statistics */ |
#endif /* PC statistics */ |
115 |
|
|
116 |
|
|
117 |
#define S gather_statistics(cpu) |
#define S gather_statistics(cpu) |
118 |
|
|
119 |
|
|
120 |
#ifdef DYNTRANS_VARIABLE_INSTRUCTION_LENGTH |
#ifdef DYNTRANS_VARIABLE_INSTRUCTION_LENGTH |
121 |
#define I ic = cpu->cd.DYNTRANS_ARCH.next_ic; \ |
#define I ic = cpu->cd.DYNTRANS_ARCH.next_ic; \ |
122 |
cpu->cd.DYNTRANS_ARCH.next_ic += ic->arg[0]; \ |
cpu->cd.DYNTRANS_ARCH.next_ic += ic->arg[0]; \ |
123 |
ic->f(cpu, ic); |
ic->f(cpu, ic); |
124 |
#else |
#else |
125 |
#define I ic = cpu->cd.DYNTRANS_ARCH.next_ic ++; ic->f(cpu, ic); |
|
126 |
|
/* The normal instruction execution core: */ |
127 |
|
#define I ic = cpu->cd.DYNTRANS_ARCH.next_ic ++; ic->f(cpu, ic); |
128 |
|
|
129 |
|
/* For heavy debugging: */ |
130 |
|
/* #define I ic = cpu->cd.DYNTRANS_ARCH.next_ic ++; \ |
131 |
|
{ \ |
132 |
|
int low_pc = ((size_t)cpu->cd.DYNTRANS_ARCH.next_ic - \ |
133 |
|
(size_t)cpu->cd.DYNTRANS_ARCH.cur_ic_page) / \ |
134 |
|
sizeof(struct DYNTRANS_IC); \ |
135 |
|
printf("cur_ic_page=%p ic=%p (low_pc=0x%x)\n", \ |
136 |
|
cpu->cd.DYNTRANS_ARCH.cur_ic_page, \ |
137 |
|
ic, low_pc << DYNTRANS_INSTR_ALIGNMENT_SHIFT); \ |
138 |
|
} \ |
139 |
|
ic->f(cpu, ic); */ |
140 |
|
|
141 |
|
/* static long long nr_of_I_calls = 0; */ |
142 |
|
|
143 |
|
/* Temporary hack for finding NULL bugs: */ |
144 |
|
/* #define I ic = cpu->cd.DYNTRANS_ARCH.next_ic ++; \ |
145 |
|
nr_of_I_calls ++; \ |
146 |
|
if (ic->f == NULL) { \ |
147 |
|
int low_pc = ((size_t)cpu->cd.DYNTRANS_ARCH.next_ic - \ |
148 |
|
(size_t)cpu->cd.DYNTRANS_ARCH.cur_ic_page) / \ |
149 |
|
sizeof(struct DYNTRANS_IC); \ |
150 |
|
cpu->pc &= ~((DYNTRANS_IC_ENTRIES_PER_PAGE-1) << \ |
151 |
|
DYNTRANS_INSTR_ALIGNMENT_SHIFT); \ |
152 |
|
cpu->pc += (low_pc << DYNTRANS_INSTR_ALIGNMENT_SHIFT);\ |
153 |
|
printf("Crash at %016"PRIx64"\n", cpu->pc); \ |
154 |
|
printf("nr of I calls: %lli\n", nr_of_I_calls); \ |
155 |
|
printf("Next ic = %p\n", cpu->cd. \ |
156 |
|
DYNTRANS_ARCH.next_ic); \ |
157 |
|
printf("cur ic page = %p\n", cpu->cd. \ |
158 |
|
DYNTRANS_ARCH.cur_ic_page); \ |
159 |
|
cpu->running = 0; \ |
160 |
|
return 0; \ |
161 |
|
} \ |
162 |
|
ic->f(cpu, ic); */ |
163 |
|
|
164 |
|
/* Temporary hack for MIPS, to hunt for 32-bit/64-bit sign-extension bugs: */ |
165 |
|
/* #define I { int k; for (k=1; k<=31; k++) \ |
166 |
|
cpu->cd.mips.gpr[k] = (int32_t)cpu->cd.mips.gpr[k];\ |
167 |
|
if (cpu->cd.mips.gpr[0] != 0) { \ |
168 |
|
fatal("NOOOOOO\n"); exit(1); \ |
169 |
|
} \ |
170 |
|
ic = cpu->cd.DYNTRANS_ARCH.next_ic ++; ic->f(cpu, ic); } |
171 |
|
*/ |
172 |
#endif |
#endif |
173 |
|
|
174 |
|
|
182 |
*/ |
*/ |
183 |
int DYNTRANS_CPU_RUN_INSTR(struct emul *emul, struct cpu *cpu) |
int DYNTRANS_CPU_RUN_INSTR(struct emul *emul, struct cpu *cpu) |
184 |
{ |
{ |
185 |
#ifdef MODE32 |
/* |
186 |
uint32_t cached_pc; |
* TODO: Statistics stuff! |
187 |
#else |
*/ |
188 |
|
int show_opcode_statistics = 0; |
189 |
|
|
190 |
|
#ifdef DYNTRANS_DUALMODE_32 |
191 |
uint64_t cached_pc; |
uint64_t cached_pc; |
192 |
|
#else |
193 |
|
uint32_t cached_pc; |
194 |
#endif |
#endif |
195 |
int low_pc, n_instrs; |
int low_pc, n_instrs; |
196 |
|
|
206 |
* conversion; if the conversion caused an exception of some kind |
* conversion; if the conversion caused an exception of some kind |
207 |
* then interrupts are probably disabled, and the exception will get |
* then interrupts are probably disabled, and the exception will get |
208 |
* priority over device interrupts.) |
* priority over device interrupts.) |
209 |
|
* |
210 |
|
* TODO: Turn this into a family-specific function somewhere... |
211 |
*/ |
*/ |
212 |
#ifdef DYNTRANS_ARM |
#ifdef DYNTRANS_ARM |
213 |
if (cpu->cd.arm.irq_asserted && !(cpu->cd.arm.cpsr & ARM_FLAG_I)) |
if (cpu->cd.arm.irq_asserted && !(cpu->cd.arm.cpsr & ARM_FLAG_I)) |
214 |
arm_exception(cpu, ARM_EXCEPTION_IRQ); |
arm_exception(cpu, ARM_EXCEPTION_IRQ); |
215 |
#endif |
#endif |
216 |
|
#ifdef DYNTRANS_MIPS |
217 |
|
{ |
218 |
|
int enabled, mask; |
219 |
|
int status = cpu->cd.mips.coproc[0]->reg[COP0_STATUS]; |
220 |
|
if (cpu->cd.mips.cpu_type.exc_model == EXC3K) { |
221 |
|
/* R3000: */ |
222 |
|
enabled = status & MIPS_SR_INT_IE; |
223 |
|
} else { |
224 |
|
/* R4000 and others: */ |
225 |
|
enabled = (status & STATUS_IE) |
226 |
|
&& !(status & STATUS_EXL) && !(status & STATUS_ERL); |
227 |
|
/* Special case for R5900/C790/TX79: */ |
228 |
|
if (cpu->cd.mips.cpu_type.rev == MIPS_R5900 && |
229 |
|
!(status & R5900_STATUS_EIE)) |
230 |
|
enabled = 0; |
231 |
|
} |
232 |
|
mask = status & cpu->cd.mips.coproc[0]->reg[COP0_CAUSE] |
233 |
|
& STATUS_IM_MASK; |
234 |
|
|
235 |
|
if (enabled && mask) |
236 |
|
mips_cpu_exception(cpu, EXCEPTION_INT, 0, 0, 0, 0, 0,0); |
237 |
|
} |
238 |
|
#endif |
239 |
#ifdef DYNTRANS_PPC |
#ifdef DYNTRANS_PPC |
240 |
if (cpu->cd.ppc.dec_intr_pending && cpu->cd.ppc.msr & PPC_MSR_EE) { |
if (cpu->cd.ppc.dec_intr_pending && cpu->cd.ppc.msr & PPC_MSR_EE) { |
241 |
ppc_exception(cpu, PPC_EXCEPTION_DEC); |
ppc_exception(cpu, PPC_EXCEPTION_DEC); |
253 |
cpu->cd.DYNTRANS_ARCH.cur_physpage = (void *) |
cpu->cd.DYNTRANS_ARCH.cur_physpage = (void *) |
254 |
cpu->cd.DYNTRANS_ARCH.cur_ic_page; |
cpu->cd.DYNTRANS_ARCH.cur_ic_page; |
255 |
|
|
256 |
if (single_step || cpu->machine->instruction_trace) { |
if (single_step || cpu->machine->instruction_trace |
257 |
|
|| cpu->machine->register_dump) { |
258 |
/* |
/* |
259 |
* Single-step: |
* Single-step: |
260 |
*/ |
*/ |
261 |
struct DYNTRANS_IC *ic = cpu->cd.DYNTRANS_ARCH.next_ic |
struct DYNTRANS_IC *ic = cpu->cd.DYNTRANS_ARCH.next_ic; |
262 |
#ifndef DYNTRANS_VARIABLE_INSTRUCTION_LENGTH |
if (cpu->machine->register_dump) { |
263 |
++ |
debug("\n"); |
264 |
#endif |
cpu_register_dump(cpu->machine, cpu, 1, 0x1); |
265 |
; |
} |
266 |
if (cpu->machine->instruction_trace) { |
if (cpu->machine->instruction_trace) { |
267 |
#ifdef DYNTRANS_X86 |
#ifdef DYNTRANS_X86 |
268 |
unsigned char instr[17]; |
unsigned char instr[17]; |
275 |
unsigned char instr[4]; /* General case... */ |
unsigned char instr[4]; /* General case... */ |
276 |
#endif |
#endif |
277 |
#endif |
#endif |
278 |
|
|
279 |
if (!cpu->memory_rw(cpu, cpu->mem, cached_pc, &instr[0], |
if (!cpu->memory_rw(cpu, cpu->mem, cached_pc, &instr[0], |
280 |
sizeof(instr), MEM_READ, CACHE_INSTRUCTION)) { |
sizeof(instr), MEM_READ, CACHE_INSTRUCTION)) { |
281 |
fatal("XXX_cpu_run_instr(): could not read " |
fatal("XXX_cpu_run_instr(): could not read " |
282 |
"the instruction\n"); |
"the instruction\n"); |
283 |
} else { |
} else { |
284 |
cpu_disassemble_instr(cpu->machine, cpu, |
cpu_disassemble_instr(cpu->machine, cpu, |
285 |
instr, 1, 0, 0); |
instr, 1, 0); |
286 |
#ifdef DYNTRANS_MIPS |
#ifdef DYNTRANS_DELAYSLOT |
|
/* TODO: generalize, not just MIPS */ |
|
287 |
/* Show the instruction in the delay slot, |
/* Show the instruction in the delay slot, |
288 |
if any: */ |
if any: */ |
289 |
fatal("TODO: check for delay slot!\n"); |
if (cpu->instruction_has_delayslot == NULL) |
290 |
|
fatal("WARNING: ihd func not yet" |
291 |
|
" implemented?\n"); |
292 |
|
else if (cpu->instruction_has_delayslot(cpu, |
293 |
|
instr)) { |
294 |
|
int saved_delayslot = cpu->delay_slot; |
295 |
|
cpu->memory_rw(cpu, cpu->mem, cached_pc |
296 |
|
+ sizeof(instr), &instr[0], |
297 |
|
sizeof(instr), MEM_READ, |
298 |
|
CACHE_INSTRUCTION); |
299 |
|
cpu->delay_slot = DELAYED; |
300 |
|
cpu->pc += sizeof(instr); |
301 |
|
cpu_disassemble_instr(cpu->machine, |
302 |
|
cpu, instr, 1, 0); |
303 |
|
cpu->delay_slot = saved_delayslot; |
304 |
|
cpu->pc -= sizeof(instr); |
305 |
|
} |
306 |
#endif |
#endif |
307 |
} |
} |
308 |
} |
} |
311 |
be combined into one. This clears all translations: */ |
be combined into one. This clears all translations: */ |
312 |
if (cpu->cd.DYNTRANS_ARCH.cur_physpage->flags & COMBINATIONS) { |
if (cpu->cd.DYNTRANS_ARCH.cur_physpage->flags & COMBINATIONS) { |
313 |
int i; |
int i; |
314 |
for (i=0; i<DYNTRANS_IC_ENTRIES_PER_PAGE; i++) |
for (i=0; i<DYNTRANS_IC_ENTRIES_PER_PAGE; i++) { |
315 |
cpu->cd.DYNTRANS_ARCH.cur_physpage->ics[i].f = |
cpu->cd.DYNTRANS_ARCH.cur_physpage->ics[i].f = |
316 |
#ifdef DYNTRANS_DUALMODE_32 |
#ifdef DYNTRANS_DUALMODE_32 |
317 |
cpu->is_32bit? |
cpu->is_32bit? |
318 |
instr32(to_be_translated) : |
instr32(to_be_translated) : |
319 |
#endif |
#endif |
320 |
instr(to_be_translated); |
instr(to_be_translated); |
321 |
fatal("[ Note: The translation of physical page 0x%llx" |
#ifdef DYNTRANS_VARIABLE_INSTRUCTION_LENGTH |
322 |
" contained combinations of instructions; these " |
cpu->cd.DYNTRANS_ARCH.cur_physpage->ics[i]. |
323 |
"are now flushed because we are single-stepping." |
arg[0] = 0; |
324 |
" ]\n", (long long)cpu->cd.DYNTRANS_ARCH. |
#endif |
325 |
|
} |
326 |
|
fatal("[ Note: The translation of physical page 0x%" |
327 |
|
PRIx64" contained combinations of instructions; " |
328 |
|
"these are now flushed because we are single-" |
329 |
|
"stepping. ]\n", (long long)cpu->cd.DYNTRANS_ARCH. |
330 |
cur_physpage->physaddr); |
cur_physpage->physaddr); |
331 |
cpu->cd.DYNTRANS_ARCH.cur_physpage->flags &= |
cpu->cd.DYNTRANS_ARCH.cur_physpage->flags &= |
332 |
~(COMBINATIONS | TRANSLATIONS); |
~(COMBINATIONS | TRANSLATIONS); |
336 |
S; |
S; |
337 |
|
|
338 |
/* Execute just one instruction: */ |
/* Execute just one instruction: */ |
339 |
ic->f(cpu, ic); |
I; |
340 |
|
|
341 |
n_instrs = 1; |
n_instrs = 1; |
342 |
|
} else if (cpu->machine->cycle_accurate) { |
343 |
|
/* Executing multiple instructions, and call devices' |
344 |
|
tick functions: */ |
345 |
|
n_instrs = 0; |
346 |
|
for (;;) { |
347 |
|
struct DYNTRANS_IC *ic; |
348 |
|
/* TODO: continue here */ |
349 |
|
int64_t cycles = cpu->cd.avr.extra_cycles; |
350 |
|
I; |
351 |
|
n_instrs += 1; |
352 |
|
cycles = cpu->cd.avr.extra_cycles - cycles + 1; |
353 |
|
/* The instruction took 'cycles' cycles. */ |
354 |
|
/* printf("A\n"); */ |
355 |
|
while (cycles-- > 0) |
356 |
|
cpu->machine->tick_func[1](cpu, cpu->machine->tick_extra[1]); |
357 |
|
/* printf("B\n"); */ |
358 |
|
|
359 |
|
if (!cpu->running_translated || |
360 |
|
n_instrs + cpu->n_translated_instrs >= |
361 |
|
N_SAFE_DYNTRANS_LIMIT / 2) |
362 |
|
break; |
363 |
|
} |
364 |
} else if (show_opcode_statistics) { |
} else if (show_opcode_statistics) { |
365 |
/* Gather statistics while executing multiple instructions: */ |
/* Gather statistics while executing multiple instructions: */ |
366 |
n_instrs = 0; |
n_instrs = 0; |
375 |
n_instrs += 24; |
n_instrs += 24; |
376 |
|
|
377 |
if (!cpu->running_translated || |
if (!cpu->running_translated || |
378 |
n_instrs + cpu->n_translated_instrs >= 16384) |
n_instrs + cpu->n_translated_instrs >= |
379 |
|
N_SAFE_DYNTRANS_LIMIT / 2) |
380 |
break; |
break; |
381 |
} |
} |
382 |
} else { |
} else { |
396 |
n_instrs += 60; |
n_instrs += 60; |
397 |
|
|
398 |
if (!cpu->running_translated || |
if (!cpu->running_translated || |
399 |
n_instrs + cpu->n_translated_instrs >= 16384) |
n_instrs + cpu->n_translated_instrs >= |
400 |
|
N_SAFE_DYNTRANS_LIMIT / 2) |
401 |
break; |
break; |
402 |
} |
} |
403 |
} |
} |
426 |
DYNTRANS_INSTR_ALIGNMENT_SHIFT); |
DYNTRANS_INSTR_ALIGNMENT_SHIFT); |
427 |
} |
} |
428 |
|
|
429 |
|
#ifdef DYNTRANS_MIPS |
430 |
|
/* Update the count register (on everything except EXC3K): */ |
431 |
|
if (cpu->cd.mips.cpu_type.exc_model != EXC3K) { |
432 |
|
uint32_t old = cpu->cd.mips.coproc[0]->reg[COP0_COUNT]; |
433 |
|
int32_t diff1 = cpu->cd.mips.coproc[0]->reg[COP0_COMPARE] - old; |
434 |
|
int32_t diff2; |
435 |
|
cpu->cd.mips.coproc[0]->reg[COP0_COUNT] = |
436 |
|
(int32_t) (old + n_instrs); |
437 |
|
diff2 = cpu->cd.mips.coproc[0]->reg[COP0_COMPARE] - |
438 |
|
cpu->cd.mips.coproc[0]->reg[COP0_COUNT]; |
439 |
|
if (cpu->cd.mips.compare_register_set && diff1>0 && diff2<=0) |
440 |
|
cpu_interrupt(cpu, 7); |
441 |
|
} |
442 |
|
#endif |
443 |
#ifdef DYNTRANS_PPC |
#ifdef DYNTRANS_PPC |
444 |
/* Update the Decrementer and Time base registers: */ |
/* Update the Decrementer and Time base registers: */ |
445 |
{ |
{ |
476 |
char *symbol; |
char *symbol; |
477 |
uint64_t ot; |
uint64_t ot; |
478 |
int x, print_dots = 1, n_args_to_print = |
int x, print_dots = 1, n_args_to_print = |
479 |
#ifdef DYNTRANS_ALPHA |
#if defined(DYNTRANS_ALPHA) || defined(DYNTRANS_SPARC) |
480 |
6 |
6 |
481 |
#else |
#else |
482 |
#ifdef DYNTRANS_SH |
#ifdef DYNTRANS_SH |
558 |
fatal("&%s", symbol); |
fatal("&%s", symbol); |
559 |
else { |
else { |
560 |
if (cpu->is_32bit) |
if (cpu->is_32bit) |
561 |
fatal("0x%x", (int)d); |
fatal("0x%"PRIx32, (uint32_t)d); |
562 |
else |
else |
563 |
fatal("0x%llx", (long long)d); |
fatal("0x%"PRIx64, (uint64_t)d); |
564 |
} |
} |
565 |
|
|
566 |
if (x < n_args_to_print - 1) |
if (x < n_args_to_print - 1) |
610 |
ppp->physaddr = physaddr; |
ppp->physaddr = physaddr; |
611 |
|
|
612 |
/* TODO: Is this faster than copying an entire template page? */ |
/* TODO: Is this faster than copying an entire template page? */ |
613 |
for (i=0; i<DYNTRANS_IC_ENTRIES_PER_PAGE; i++) |
for (i=0; i<DYNTRANS_IC_ENTRIES_PER_PAGE; i++) { |
614 |
ppp->ics[i].f = |
ppp->ics[i].f = |
615 |
#ifdef DYNTRANS_DUALMODE_32 |
#ifdef DYNTRANS_DUALMODE_32 |
616 |
cpu->is_32bit? instr32(to_be_translated) : |
cpu->is_32bit? instr32(to_be_translated) : |
617 |
#endif |
#endif |
618 |
instr(to_be_translated); |
instr(to_be_translated); |
619 |
|
#ifdef DYNTRANS_VARIABLE_INSTRUCTION_LENGTH |
620 |
|
ppp->ics[i].arg[0] = 0; |
621 |
|
#endif |
622 |
|
} |
623 |
|
|
624 |
|
/* End-of-page: */ |
625 |
ppp->ics[DYNTRANS_IC_ENTRIES_PER_PAGE + 0].f = |
ppp->ics[DYNTRANS_IC_ENTRIES_PER_PAGE + 0].f = |
626 |
#ifdef DYNTRANS_DUALMODE_32 |
#ifdef DYNTRANS_DUALMODE_32 |
627 |
cpu->is_32bit? instr32(end_of_page) : |
cpu->is_32bit? instr32(end_of_page) : |
628 |
#endif |
#endif |
629 |
instr(end_of_page); |
instr(end_of_page); |
630 |
|
|
631 |
|
#ifdef DYNTRANS_VARIABLE_INSTRUCTION_LENGTH |
632 |
|
ppp->ics[DYNTRANS_IC_ENTRIES_PER_PAGE + 0].arg[0] = 0; |
633 |
|
#endif |
634 |
|
|
635 |
|
/* End-of-page-2, for delay-slot architectures: */ |
636 |
#ifdef DYNTRANS_DELAYSLOT |
#ifdef DYNTRANS_DELAYSLOT |
637 |
ppp->ics[DYNTRANS_IC_ENTRIES_PER_PAGE + 1].f = |
ppp->ics[DYNTRANS_IC_ENTRIES_PER_PAGE + 1].f = |
638 |
#ifdef DYNTRANS_DUALMODE_32 |
#ifdef DYNTRANS_DUALMODE_32 |
664 |
#else |
#else |
665 |
uint64_t |
uint64_t |
666 |
#endif |
#endif |
667 |
cached_pc, physaddr = 0; |
cached_pc = cpu->pc, physaddr = 0; |
668 |
uint32_t physpage_ofs; |
uint32_t physpage_ofs; |
669 |
int ok, pagenr, table_index; |
int ok, pagenr, table_index; |
670 |
uint32_t *physpage_entryp; |
uint32_t *physpage_entryp; |
671 |
struct DYNTRANS_TC_PHYSPAGE *ppp; |
struct DYNTRANS_TC_PHYSPAGE *ppp; |
672 |
|
|
673 |
#ifdef MODE32 |
#ifdef MODE32 |
674 |
int index; |
int index = DYNTRANS_ADDR_TO_PAGENR(cached_pc); |
|
cached_pc = cpu->pc; |
|
|
index = DYNTRANS_ADDR_TO_PAGENR(cached_pc); |
|
675 |
#else |
#else |
676 |
#ifdef DYNTRANS_ALPHA |
const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1; |
677 |
uint32_t a, b; |
const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1; |
678 |
int kernel = 0; |
const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1; |
679 |
struct alpha_vph_page *vph_p; |
uint32_t x1, x2, x3; |
680 |
cached_pc = cpu->pc; |
struct DYNTRANS_L2_64_TABLE *l2; |
681 |
a = (cached_pc >> ALPHA_LEVEL0_SHIFT) & (ALPHA_LEVEL0 - 1); |
struct DYNTRANS_L3_64_TABLE *l3; |
682 |
b = (cached_pc >> ALPHA_LEVEL1_SHIFT) & (ALPHA_LEVEL1 - 1); |
|
683 |
if ((cached_pc >> ALPHA_TOPSHIFT) == ALPHA_TOP_KERNEL) { |
x1 = (cached_pc >> (64-DYNTRANS_L1N)) & mask1; |
684 |
vph_p = cpu->cd.alpha.vph_table0_kernel[a]; |
x2 = (cached_pc >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2; |
685 |
kernel = 1; |
x3 = (cached_pc >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) & mask3; |
686 |
} else |
/* fatal("X3: cached_pc=%016"PRIx64" x1=%x x2=%x x3=%x\n", |
687 |
vph_p = cpu->cd.alpha.vph_table0[a]; |
(uint64_t)cached_pc, (int)x1, (int)x2, (int)x3); */ |
688 |
#else |
l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1]; |
689 |
fatal("Neither alpha nor 32-bit? 3\n"); |
/* fatal(" l2 = %p\n", l2); */ |
690 |
exit(1); |
l3 = l2->l3[x2]; |
691 |
#endif |
/* fatal(" l3 = %p\n", l3); */ |
692 |
#endif |
#endif |
693 |
|
|
694 |
/* Virtual to physical address translation: */ |
/* Virtual to physical address translation: */ |
699 |
ok = 1; |
ok = 1; |
700 |
} |
} |
701 |
#else |
#else |
702 |
#ifdef DYNTRANS_ALPHA |
if (l3->host_load[x3] != NULL) { |
703 |
if (vph_p->host_load[b] != NULL) { |
physaddr = l3->phys_addr[x3]; |
|
physaddr = vph_p->phys_addr[b]; |
|
704 |
ok = 1; |
ok = 1; |
705 |
} |
} |
|
#else |
|
|
fatal("Neither alpha nor 32-bit? 4\n"); |
|
|
exit(1); |
|
|
#endif |
|
706 |
#endif |
#endif |
707 |
|
|
708 |
if (!ok) { |
if (!ok) { |
715 |
ok = 1; |
ok = 1; |
716 |
} |
} |
717 |
if (!ok) { |
if (!ok) { |
718 |
/* fatal("TODO: instruction vaddr=>paddr translation" |
/* fatal("TODO: instruction vaddr=>paddr translation " |
719 |
" failed. vaddr=0x%llx\n", (long long)cached_pc); |
"failed. vaddr=0x%"PRIx64"\n", (uint64_t)cached_pc); |
720 |
fatal("!! cpu->pc=0x%llx\n", (long long)cpu->pc); */ |
fatal("!! cpu->pc=0x%"PRIx64"\n", (uint64_t)cpu->pc); */ |
721 |
|
|
722 |
ok = cpu->translate_address(cpu, cpu->pc, &paddr, |
ok = cpu->translate_address(cpu, cpu->pc, &paddr, |
723 |
FLAG_INSTR); |
FLAG_INSTR); |
724 |
|
|
725 |
/* printf("EXCEPTION HANDLER: vaddr = 0x%x ==> " |
/* printf("EXCEPTION HANDLER: vaddr = 0x%x ==> " |
726 |
"paddr = 0x%x\n", (int)cpu->pc, (int)paddr); |
"paddr = 0x%x\n", (int)cpu->pc, (int)paddr); |
727 |
fatal("!? cpu->pc=0x%llx\n", (long long)cpu->pc); */ |
fatal("!? cpu->pc=0x%"PRIx64"\n", (uint64_t)cpu->pc); */ |
728 |
|
|
729 |
if (!ok) { |
if (!ok) { |
730 |
fatal("FATAL: could not find physical" |
fatal("FATAL: could not find physical" |
732 |
exit(1); |
exit(1); |
733 |
} |
} |
734 |
} |
} |
735 |
|
|
736 |
|
/* If there was an exception, the PC can have changed. |
737 |
|
Update cached_pc: */ |
738 |
cached_pc = cpu->pc; |
cached_pc = cpu->pc; |
739 |
|
|
740 |
#ifdef MODE32 |
#ifdef MODE32 |
741 |
index = DYNTRANS_ADDR_TO_PAGENR(cached_pc); |
index = DYNTRANS_ADDR_TO_PAGENR(cached_pc); |
742 |
|
#else |
743 |
|
x1 = (cached_pc >> (64-DYNTRANS_L1N)) & mask1; |
744 |
|
x2 = (cached_pc >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2; |
745 |
|
x3 = (cached_pc >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) |
746 |
|
& mask3; |
747 |
#endif |
#endif |
748 |
|
|
749 |
physaddr = paddr; |
physaddr = paddr; |
750 |
} |
} |
751 |
|
|
752 |
#ifdef MODE32 |
#ifdef MODE32 |
753 |
if (cpu->cd.DYNTRANS_ARCH.host_load[index] == NULL) { |
if (cpu->cd.DYNTRANS_ARCH.host_load[index] == NULL) { |
754 |
|
#else |
755 |
|
if (l3->host_load[x3] == NULL) { |
756 |
|
#endif |
757 |
unsigned char *host_page = memory_paddr_to_hostaddr(cpu->mem, |
unsigned char *host_page = memory_paddr_to_hostaddr(cpu->mem, |
758 |
physaddr, MEM_READ); |
physaddr, MEM_READ); |
759 |
if (host_page != NULL) { |
if (host_page != NULL) { |
762 |
((1 << BITS_PER_MEMBLOCK) - 1) & ~q); |
((1 << BITS_PER_MEMBLOCK) - 1) & ~q); |
763 |
cpu->update_translation_table(cpu, cached_pc & ~q, |
cpu->update_translation_table(cpu, cached_pc & ~q, |
764 |
host_page, TLB_CODE, physaddr & ~q); |
host_page, TLB_CODE, physaddr & ~q); |
765 |
|
#ifndef MODE32 |
766 |
|
/* Recalculate l2 and l3, since they might have |
767 |
|
changed now: */ |
768 |
|
l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1]; |
769 |
|
l3 = l2->l3[x2]; |
770 |
|
#endif |
771 |
} |
} |
772 |
} |
} |
|
#endif |
|
773 |
|
|
774 |
if (cpu->translation_cache_cur_ofs >= DYNTRANS_CACHE_SIZE) { |
if (cpu->translation_cache_cur_ofs >= DYNTRANS_CACHE_SIZE) { |
775 |
debug("[ dyntrans: resetting the translation cache ]\n"); |
debug("[ dyntrans: resetting the translation cache ]\n"); |
788 |
ppp = (struct DYNTRANS_TC_PHYSPAGE *)(cpu->translation_cache |
ppp = (struct DYNTRANS_TC_PHYSPAGE *)(cpu->translation_cache |
789 |
+ physpage_ofs); |
+ physpage_ofs); |
790 |
/* If we found the page in the cache, then we're done: */ |
/* If we found the page in the cache, then we're done: */ |
791 |
if (ppp->physaddr == physaddr) |
if (DYNTRANS_ADDR_TO_PAGENR(ppp->physaddr) == pagenr) |
792 |
break; |
break; |
793 |
/* Try the next page in the chain: */ |
/* Try the next page in the chain: */ |
794 |
physpage_ofs = ppp->next_ofs; |
physpage_ofs = ppp->next_ofs; |
798 |
new "default" empty translation page. */ |
new "default" empty translation page. */ |
799 |
|
|
800 |
if (ppp == NULL) { |
if (ppp == NULL) { |
801 |
/* fatal("CREATING page %lli (physaddr 0x%llx), table index " |
/* fatal("CREATING page %lli (physaddr 0x%"PRIx64"), table " |
802 |
"%i\n", (long long)pagenr, (long long)physaddr, |
"index %i\n", (long long)pagenr, (uint64_t)physaddr, |
803 |
(int)table_index); */ |
(int)table_index); */ |
804 |
*physpage_entryp = physpage_ofs = |
*physpage_entryp = physpage_ofs = |
805 |
cpu->translation_cache_cur_ofs; |
cpu->translation_cache_cur_ofs; |
814 |
#ifdef MODE32 |
#ifdef MODE32 |
815 |
if (cpu->cd.DYNTRANS_ARCH.host_load[index] != NULL) |
if (cpu->cd.DYNTRANS_ARCH.host_load[index] != NULL) |
816 |
cpu->cd.DYNTRANS_ARCH.phys_page[index] = ppp; |
cpu->cd.DYNTRANS_ARCH.phys_page[index] = ppp; |
817 |
#endif |
#else |
818 |
|
if (l3->host_load[x3] != NULL) |
819 |
#ifdef DYNTRANS_ALPHA |
l3->phys_page[x3] = ppp; |
|
if (vph_p->host_load[b] != NULL) |
|
|
vph_p->phys_page[b] = ppp; |
|
820 |
#endif |
#endif |
821 |
|
|
822 |
#ifdef MODE32 |
#ifdef MODE32 |
834 |
cpu->cd.DYNTRANS_ARCH.next_ic = cpu->cd.DYNTRANS_ARCH.cur_ic_page + |
cpu->cd.DYNTRANS_ARCH.next_ic = cpu->cd.DYNTRANS_ARCH.cur_ic_page + |
835 |
DYNTRANS_PC_TO_IC_ENTRY(cached_pc); |
DYNTRANS_PC_TO_IC_ENTRY(cached_pc); |
836 |
|
|
837 |
/* printf("cached_pc=0x%016llx pagenr=%lli table_index=%lli, " |
/* printf("cached_pc=0x%016"PRIx64" pagenr=%lli table_index=%lli, " |
838 |
"physpage_ofs=0x%016llx\n", (long long)cached_pc, (long long)pagenr, |
"physpage_ofs=0x%016"PRIx64"\n", (uint64_t)cached_pc, (long long) |
839 |
(long long)table_index, (long long)physpage_ofs); */ |
pagenr, (long long)table_index, (uint64_t)physpage_ofs); */ |
840 |
} |
} |
841 |
|
|
842 |
|
|
870 |
if (ppp != NULL) |
if (ppp != NULL) |
871 |
goto have_it; |
goto have_it; |
872 |
#else |
#else |
873 |
#ifdef DYNTRANS_ALPHA |
const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1; |
874 |
uint32_t a, b; |
const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1; |
875 |
int kernel = 0; |
const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1; |
876 |
struct alpha_vph_page *vph_p; |
uint32_t x1, x2, x3; |
877 |
a = (cached_pc >> ALPHA_LEVEL0_SHIFT) & (ALPHA_LEVEL0 - 1); |
struct DYNTRANS_L2_64_TABLE *l2; |
878 |
b = (cached_pc >> ALPHA_LEVEL1_SHIFT) & (ALPHA_LEVEL1 - 1); |
struct DYNTRANS_L3_64_TABLE *l3; |
879 |
if ((cached_pc >> ALPHA_TOPSHIFT) == ALPHA_TOP_KERNEL) { |
|
880 |
vph_p = cpu->cd.alpha.vph_table0_kernel[a]; |
x1 = (cached_pc >> (64-DYNTRANS_L1N)) & mask1; |
881 |
kernel = 1; |
x2 = (cached_pc >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2; |
882 |
} else |
x3 = (cached_pc >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) & mask3; |
883 |
vph_p = cpu->cd.alpha.vph_table0[a]; |
l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1]; |
884 |
if (vph_p != cpu->cd.alpha.vph_default_page) { |
l3 = l2->l3[x2]; |
885 |
ppp = vph_p->phys_page[b]; |
ppp = l3->phys_page[x3]; |
886 |
if (ppp != NULL) |
if (ppp != NULL) |
887 |
goto have_it; |
goto have_it; |
|
} |
|
|
#else |
|
|
fatal("X1: cached_pc=%016llx\n", (long long)cached_pc); |
|
|
/* Temporary, to avoid a compiler warning: */ |
|
|
ppp = NULL; |
|
|
fatal("Neither alpha nor 32-bit? 1\n"); |
|
|
exit(1); |
|
|
#endif |
|
888 |
#endif |
#endif |
889 |
|
|
890 |
DYNTRANS_PC_TO_POINTERS_GENERIC(cpu); |
DYNTRANS_PC_TO_POINTERS_GENERIC(cpu); |
891 |
return; |
return; |
892 |
|
|
893 |
/* Quick return path: */ |
/* Quick return path: */ |
|
#if defined(MODE32) || defined(DYNTRANS_ALPHA) |
|
894 |
have_it: |
have_it: |
895 |
cpu->cd.DYNTRANS_ARCH.cur_ic_page = &ppp->ics[0]; |
cpu->cd.DYNTRANS_ARCH.cur_ic_page = &ppp->ics[0]; |
896 |
cpu->cd.DYNTRANS_ARCH.next_ic = cpu->cd.DYNTRANS_ARCH.cur_ic_page + |
cpu->cd.DYNTRANS_ARCH.next_ic = cpu->cd.DYNTRANS_ARCH.cur_ic_page + |
897 |
DYNTRANS_PC_TO_IC_ENTRY(cached_pc); |
DYNTRANS_PC_TO_IC_ENTRY(cached_pc); |
898 |
|
|
899 |
/* printf("cached_pc=0x%016llx pagenr=%lli table_index=%lli, " |
/* printf("cached_pc=0x%016"PRIx64" pagenr=%lli table_index=%lli, " |
900 |
"physpage_ofs=0x%016llx\n", (long long)cached_pc, (long long)pagenr, |
"physpage_ofs=0x%016"PRIx64"\n", (uint64_t)cached_pc, (long long) |
901 |
(long long)table_index, (long long)physpage_ofs); */ |
pagenr, (long long)table_index, (uint64_t)physpage_ofs); */ |
|
#endif |
|
902 |
} |
} |
903 |
#endif /* DYNTRANS_PC_TO_POINTERS_FUNC */ |
#endif /* DYNTRANS_PC_TO_POINTERS_FUNC */ |
904 |
|
|
905 |
|
|
906 |
|
|
907 |
|
#ifdef DYNTRANS_INIT_64BIT_DUMMY_TABLES |
908 |
|
/* |
909 |
|
* XXX_init_64bit_dummy_tables(): |
910 |
|
* |
911 |
|
* Initializes 64-bit dummy tables and pointers. |
912 |
|
*/ |
913 |
|
void DYNTRANS_INIT_64BIT_DUMMY_TABLES(struct cpu *cpu) |
914 |
|
{ |
915 |
|
struct DYNTRANS_L2_64_TABLE *dummy_l2; |
916 |
|
struct DYNTRANS_L3_64_TABLE *dummy_l3; |
917 |
|
int x1, x2; |
918 |
|
|
919 |
|
if (cpu->is_32bit) |
920 |
|
return; |
921 |
|
|
922 |
|
dummy_l2 = zeroed_alloc(sizeof(struct DYNTRANS_L2_64_TABLE)); |
923 |
|
dummy_l3 = zeroed_alloc(sizeof(struct DYNTRANS_L3_64_TABLE)); |
924 |
|
|
925 |
|
cpu->cd.DYNTRANS_ARCH.l2_64_dummy = dummy_l2; |
926 |
|
cpu->cd.DYNTRANS_ARCH.l3_64_dummy = dummy_l3; |
927 |
|
|
928 |
|
for (x1 = 0; x1 < (1 << DYNTRANS_L1N); x1 ++) |
929 |
|
cpu->cd.DYNTRANS_ARCH.l1_64[x1] = dummy_l2; |
930 |
|
|
931 |
|
for (x2 = 0; x2 < (1 << DYNTRANS_L2N); x2 ++) |
932 |
|
dummy_l2->l3[x2] = dummy_l3; |
933 |
|
} |
934 |
|
#endif /* DYNTRANS_INIT_64BIT_DUMMY_TABLES */ |
935 |
|
|
936 |
|
|
937 |
|
|
938 |
#ifdef DYNTRANS_INVAL_ENTRY |
#ifdef DYNTRANS_INVAL_ENTRY |
939 |
/* |
/* |
940 |
* XXX_invalidate_tlb_entry(): |
* XXX_invalidate_tlb_entry(): |
965 |
(int)vaddr_page); */ |
(int)vaddr_page); */ |
966 |
cpu->cd.DYNTRANS_ARCH.host_store[index] = NULL; |
cpu->cd.DYNTRANS_ARCH.host_store[index] = NULL; |
967 |
} else { |
} else { |
968 |
|
int tlbi = cpu->cd.DYNTRANS_ARCH.vaddr_to_tlbindex[index]; |
969 |
cpu->cd.DYNTRANS_ARCH.host_load[index] = NULL; |
cpu->cd.DYNTRANS_ARCH.host_load[index] = NULL; |
970 |
cpu->cd.DYNTRANS_ARCH.host_store[index] = NULL; |
cpu->cd.DYNTRANS_ARCH.host_store[index] = NULL; |
971 |
cpu->cd.DYNTRANS_ARCH.phys_addr[index] = 0; |
cpu->cd.DYNTRANS_ARCH.phys_addr[index] = 0; |
972 |
cpu->cd.DYNTRANS_ARCH.phys_page[index] = NULL; |
cpu->cd.DYNTRANS_ARCH.phys_page[index] = NULL; |
973 |
|
if (tlbi > 0) |
974 |
|
cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[tlbi-1].valid = 0; |
975 |
cpu->cd.DYNTRANS_ARCH.vaddr_to_tlbindex[index] = 0; |
cpu->cd.DYNTRANS_ARCH.vaddr_to_tlbindex[index] = 0; |
976 |
} |
} |
977 |
#else |
#else |
978 |
/* 2-level: */ |
const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1; |
979 |
#ifdef DYNTRANS_ALPHA |
const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1; |
980 |
struct alpha_vph_page *vph_p; |
const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1; |
981 |
uint32_t a, b; |
uint32_t x1, x2, x3; |
982 |
int kernel = 0; |
struct DYNTRANS_L2_64_TABLE *l2; |
983 |
|
struct DYNTRANS_L3_64_TABLE *l3; |
984 |
a = (vaddr_page >> ALPHA_LEVEL0_SHIFT) & (ALPHA_LEVEL0 - 1); |
|
985 |
b = (vaddr_page >> ALPHA_LEVEL1_SHIFT) & (ALPHA_LEVEL1 - 1); |
x1 = (vaddr_page >> (64-DYNTRANS_L1N)) & mask1; |
986 |
if ((vaddr_page >> ALPHA_TOPSHIFT) == ALPHA_TOP_KERNEL) { |
x2 = (vaddr_page >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2; |
987 |
vph_p = cpu->cd.alpha.vph_table0_kernel[a]; |
x3 = (vaddr_page >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N))& mask3; |
|
kernel = 1; |
|
|
} else |
|
|
vph_p = cpu->cd.alpha.vph_table0[a]; |
|
988 |
|
|
989 |
if (vph_p == cpu->cd.alpha.vph_default_page) { |
l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1]; |
990 |
fatal("alpha_invalidate_tlb_entry(): huh? Problem 1.\n"); |
if (l2 == cpu->cd.DYNTRANS_ARCH.l2_64_dummy) |
991 |
exit(1); |
return; |
992 |
} |
|
993 |
|
l3 = l2->l3[x2]; |
994 |
|
if (l3 == cpu->cd.DYNTRANS_ARCH.l3_64_dummy) |
995 |
|
return; |
996 |
|
|
997 |
if (flags & JUST_MARK_AS_NON_WRITABLE) { |
if (flags & JUST_MARK_AS_NON_WRITABLE) { |
998 |
vph_p->host_store[b] = NULL; |
l3->host_store[x3] = NULL; |
999 |
return; |
return; |
1000 |
} |
} |
1001 |
vph_p->host_load[b] = NULL; |
l3->host_load[x3] = NULL; |
1002 |
vph_p->host_store[b] = NULL; |
l3->host_store[x3] = NULL; |
1003 |
vph_p->phys_addr[b] = 0; |
l3->phys_addr[x3] = 0; |
1004 |
vph_p->phys_page[b] = NULL; |
l3->phys_page[x3] = NULL; |
1005 |
vph_p->refcount --; |
l3->refcount --; |
1006 |
if (vph_p->refcount < 0) { |
if (l3->refcount < 0) { |
1007 |
fatal("alpha_invalidate_tlb_entry(): huh? Problem 2.\n"); |
fatal("xxx_invalidate_tlb_entry(): huh? Refcount bug.\n"); |
1008 |
exit(1); |
exit(1); |
1009 |
} |
} |
1010 |
if (vph_p->refcount == 0) { |
if (l3->refcount == 0) { |
1011 |
vph_p->next = cpu->cd.alpha.vph_next_free_page; |
l3->next = cpu->cd.DYNTRANS_ARCH.next_free_l3; |
1012 |
cpu->cd.alpha.vph_next_free_page = vph_p; |
cpu->cd.DYNTRANS_ARCH.next_free_l3 = l3; |
1013 |
if (kernel) |
l2->l3[x2] = cpu->cd.DYNTRANS_ARCH.l3_64_dummy; |
1014 |
cpu->cd.alpha.vph_table0_kernel[a] = |
|
1015 |
cpu->cd.alpha.vph_default_page; |
l2->refcount --; |
1016 |
else |
if (l2->refcount < 0) { |
1017 |
cpu->cd.alpha.vph_table0[a] = |
fatal("xxx_invalidate_tlb_entry(): Refcount bug L2.\n"); |
1018 |
cpu->cd.alpha.vph_default_page; |
exit(1); |
1019 |
} |
} |
1020 |
#else /* !DYNTRANS_ALPHA */ |
if (l2->refcount == 0) { |
1021 |
fatal("Not yet for non-1-level, non-Alpha\n"); |
l2->next = cpu->cd.DYNTRANS_ARCH.next_free_l2; |
1022 |
#endif /* !DYNTRANS_ALPHA */ |
cpu->cd.DYNTRANS_ARCH.next_free_l2 = l2; |
1023 |
|
cpu->cd.DYNTRANS_ARCH.l1_64[x1] = |
1024 |
|
cpu->cd.DYNTRANS_ARCH.l2_64_dummy; |
1025 |
|
} |
1026 |
|
} |
1027 |
#endif |
#endif |
1028 |
} |
} |
1029 |
#endif |
#endif |
1245 |
cpu->cd.DYNTRANS_ARCH.phystranslation[ |
cpu->cd.DYNTRANS_ARCH.phystranslation[ |
1246 |
index >> 5] &= ~ (1 << (index & 31)); |
index >> 5] &= ~ (1 << (index & 31)); |
1247 |
#else |
#else |
1248 |
/* 2-level: */ |
const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1; |
1249 |
#ifdef DYNTRANS_ALPHA |
const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1; |
1250 |
struct alpha_vph_page *vph_p; |
const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1; |
1251 |
uint32_t a, b; |
uint32_t x1, x2, x3; |
1252 |
int kernel = 0; |
struct DYNTRANS_L2_64_TABLE *l2; |
1253 |
|
struct DYNTRANS_L3_64_TABLE *l3; |
1254 |
a = (vaddr_page >> ALPHA_LEVEL0_SHIFT) |
|
1255 |
& (ALPHA_LEVEL0 - 1); |
x1 = (vaddr_page >> (64-DYNTRANS_L1N)) & mask1; |
1256 |
b = (vaddr_page >> ALPHA_LEVEL1_SHIFT) |
x2 = (vaddr_page >> (64-DYNTRANS_L1N - |
1257 |
& (ALPHA_LEVEL1 - 1); |
DYNTRANS_L2N)) & mask2; |
1258 |
if ((vaddr_page >> ALPHA_TOPSHIFT) == |
x3 = (vaddr_page >> (64-DYNTRANS_L1N - |
1259 |
ALPHA_TOP_KERNEL) { |
DYNTRANS_L2N - DYNTRANS_L3N)) & mask3; |
1260 |
vph_p = cpu->cd.alpha. |
l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1]; |
1261 |
vph_table0_kernel[a]; |
l3 = l2->l3[x2]; |
1262 |
kernel = 1; |
l3->phys_page[x3] = NULL; |
|
} else |
|
|
vph_p = cpu->cd.alpha.vph_table0[a]; |
|
|
vph_p->phys_page[b] = NULL; |
|
|
#else /* !DYNTRANS_ALPHA */ |
|
|
fatal("Not yet for non-1-level, non-Alpha\n"); |
|
|
#endif /* !DYNTRANS_ALPHA */ |
|
1263 |
#endif |
#endif |
1264 |
} |
} |
1265 |
} |
} |
1283 |
#endif |
#endif |
1284 |
int found, r, lowest_index, start, end, useraccess = 0; |
int found, r, lowest_index, start, end, useraccess = 0; |
1285 |
|
|
|
#ifdef DYNTRANS_ALPHA |
|
|
uint32_t a, b; |
|
|
struct alpha_vph_page *vph_p; |
|
|
int kernel = 0; |
|
|
/* fatal("update_translation_table(): v=0x%llx, h=%p w=%i" |
|
|
" p=0x%llx\n", (long long)vaddr_page, host_page, writeflag, |
|
|
(long long)paddr_page); */ |
|
|
#else |
|
1286 |
#ifdef MODE32 |
#ifdef MODE32 |
1287 |
uint32_t index; |
uint32_t index; |
1288 |
vaddr_page &= 0xffffffffULL; |
vaddr_page &= 0xffffffffULL; |
1291 |
" p=0x%x\n", (int)vaddr_page, host_page, writeflag, |
" p=0x%x\n", (int)vaddr_page, host_page, writeflag, |
1292 |
(int)paddr_page); */ |
(int)paddr_page); */ |
1293 |
#else /* !MODE32 */ |
#else /* !MODE32 */ |
1294 |
fatal("Neither 32-bit nor Alpha? 2\n"); |
const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1; |
1295 |
exit(1); |
const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1; |
1296 |
#endif |
const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1; |
1297 |
|
uint32_t x1, x2, x3; |
1298 |
|
struct DYNTRANS_L2_64_TABLE *l2; |
1299 |
|
struct DYNTRANS_L3_64_TABLE *l3; |
1300 |
|
/* fatal("update_translation_table(): v=0x%"PRIx64", h=%p w=%i" |
1301 |
|
" p=0x%"PRIx64"\n", (uint64_t)vaddr_page, host_page, writeflag, |
1302 |
|
(uint64_t)paddr_page); */ |
1303 |
#endif |
#endif |
1304 |
|
|
1305 |
if (writeflag & MEMORY_USER_ACCESS) { |
if (writeflag & MEMORY_USER_ACCESS) { |
1380 |
#endif |
#endif |
1381 |
|
|
1382 |
/* Add the new translation to the table: */ |
/* Add the new translation to the table: */ |
|
#ifdef DYNTRANS_ALPHA |
|
|
a = (vaddr_page >> ALPHA_LEVEL0_SHIFT) & (ALPHA_LEVEL0 - 1); |
|
|
b = (vaddr_page >> ALPHA_LEVEL1_SHIFT) & (ALPHA_LEVEL1 - 1); |
|
|
if ((vaddr_page >> ALPHA_TOPSHIFT) == ALPHA_TOP_KERNEL) { |
|
|
vph_p = cpu->cd.alpha.vph_table0_kernel[a]; |
|
|
kernel = 1; |
|
|
} else |
|
|
vph_p = cpu->cd.alpha.vph_table0[a]; |
|
|
if (vph_p == cpu->cd.alpha.vph_default_page) { |
|
|
if (cpu->cd.alpha.vph_next_free_page != NULL) { |
|
|
if (kernel) |
|
|
vph_p = cpu->cd.alpha.vph_table0_kernel |
|
|
[a] = cpu->cd.alpha. |
|
|
vph_next_free_page; |
|
|
else |
|
|
vph_p = cpu->cd.alpha.vph_table0[a] = |
|
|
cpu->cd.alpha.vph_next_free_page; |
|
|
cpu->cd.alpha.vph_next_free_page = vph_p->next; |
|
|
} else { |
|
|
if (kernel) |
|
|
vph_p = cpu->cd.alpha.vph_table0_kernel |
|
|
[a] = malloc(sizeof(struct |
|
|
alpha_vph_page)); |
|
|
else |
|
|
vph_p = cpu->cd.alpha.vph_table0[a] = |
|
|
malloc(sizeof(struct |
|
|
alpha_vph_page)); |
|
|
memset(vph_p, 0, sizeof(struct alpha_vph_page)); |
|
|
} |
|
|
} |
|
|
vph_p->refcount ++; |
|
|
vph_p->host_load[b] = host_page; |
|
|
vph_p->host_store[b] = writeflag? host_page : NULL; |
|
|
vph_p->phys_addr[b] = paddr_page; |
|
|
vph_p->phys_page[b] = NULL; |
|
|
#else |
|
1383 |
#ifdef MODE32 |
#ifdef MODE32 |
1384 |
index = DYNTRANS_ADDR_TO_PAGENR(vaddr_page); |
index = DYNTRANS_ADDR_TO_PAGENR(vaddr_page); |
1385 |
cpu->cd.DYNTRANS_ARCH.host_load[index] = host_page; |
cpu->cd.DYNTRANS_ARCH.host_load[index] = host_page; |
1393 |
cpu->cd.DYNTRANS_ARCH.is_userpage[index >> 5] |
cpu->cd.DYNTRANS_ARCH.is_userpage[index >> 5] |
1394 |
|= 1 << (index & 31); |
|= 1 << (index & 31); |
1395 |
#endif |
#endif |
1396 |
#endif /* 32 */ |
#else /* !MODE32 */ |
1397 |
#endif /* !ALPHA */ |
x1 = (vaddr_page >> (64-DYNTRANS_L1N)) & mask1; |
1398 |
|
x2 = (vaddr_page >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2; |
1399 |
|
x3 = (vaddr_page >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) |
1400 |
|
& mask3; |
1401 |
|
l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1]; |
1402 |
|
if (l2 == cpu->cd.DYNTRANS_ARCH.l2_64_dummy) { |
1403 |
|
if (cpu->cd.DYNTRANS_ARCH.next_free_l2 != NULL) { |
1404 |
|
l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1] = |
1405 |
|
cpu->cd.DYNTRANS_ARCH.next_free_l2; |
1406 |
|
cpu->cd.DYNTRANS_ARCH.next_free_l2 = l2->next; |
1407 |
|
} else { |
1408 |
|
int i; |
1409 |
|
l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1] = |
1410 |
|
malloc(sizeof(struct DYNTRANS_L2_64_TABLE)); |
1411 |
|
for (i=0; i<(1 << DYNTRANS_L2N); i++) |
1412 |
|
l2->l3[i] = cpu->cd.DYNTRANS_ARCH. |
1413 |
|
l3_64_dummy; |
1414 |
|
} |
1415 |
|
} |
1416 |
|
l3 = l2->l3[x2]; |
1417 |
|
if (l3 == cpu->cd.DYNTRANS_ARCH.l3_64_dummy) { |
1418 |
|
if (cpu->cd.DYNTRANS_ARCH.next_free_l3 != NULL) { |
1419 |
|
l3 = l2->l3[x2] = |
1420 |
|
cpu->cd.DYNTRANS_ARCH.next_free_l3; |
1421 |
|
cpu->cd.DYNTRANS_ARCH.next_free_l3 = l3->next; |
1422 |
|
} else { |
1423 |
|
l3 = l2->l3[x2] = zeroed_alloc(sizeof( |
1424 |
|
struct DYNTRANS_L3_64_TABLE)); |
1425 |
|
} |
1426 |
|
l2->refcount ++; |
1427 |
|
} |
1428 |
|
l3->host_load[x3] = host_page; |
1429 |
|
l3->host_store[x3] = writeflag? host_page : NULL; |
1430 |
|
l3->phys_addr[x3] = paddr_page; |
1431 |
|
l3->phys_page[x3] = NULL; |
1432 |
|
l3->vaddr_to_tlbindex[x3] = r + 1; |
1433 |
|
l3->refcount ++; |
1434 |
|
#endif /* !MODE32 */ |
1435 |
} else { |
} else { |
1436 |
/* |
/* |
1437 |
* The translation was already in the TLB. |
* The translation was already in the TLB. |
1447 |
cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].writeflag = 1; |
cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].writeflag = 1; |
1448 |
if (writeflag & MEM_DOWNGRADE) |
if (writeflag & MEM_DOWNGRADE) |
1449 |
cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].writeflag = 0; |
cpu->cd.DYNTRANS_ARCH.vph_tlb_entry[r].writeflag = 0; |
|
#ifdef DYNTRANS_ALPHA |
|
|
a = (vaddr_page >> ALPHA_LEVEL0_SHIFT) & (ALPHA_LEVEL0 - 1); |
|
|
b = (vaddr_page >> ALPHA_LEVEL1_SHIFT) & (ALPHA_LEVEL1 - 1); |
|
|
if ((vaddr_page >> ALPHA_TOPSHIFT) == ALPHA_TOP_KERNEL) { |
|
|
vph_p = cpu->cd.alpha.vph_table0_kernel[a]; |
|
|
kernel = 1; |
|
|
} else |
|
|
vph_p = cpu->cd.alpha.vph_table0[a]; |
|
|
vph_p->phys_page[b] = NULL; |
|
|
if (vph_p->phys_addr[b] == paddr_page) { |
|
|
if (writeflag & MEM_WRITE) |
|
|
vph_p->host_store[b] = host_page; |
|
|
if (writeflag & MEM_DOWNGRADE) |
|
|
vph_p->host_store[b] = NULL; |
|
|
} else { |
|
|
/* Change the entire physical/host mapping: */ |
|
|
vph_p->host_load[b] = host_page; |
|
|
vph_p->host_store[b] = writeflag? host_page : NULL; |
|
|
vph_p->phys_addr[b] = paddr_page; |
|
|
} |
|
|
#else |
|
1450 |
#ifdef MODE32 |
#ifdef MODE32 |
1451 |
index = DYNTRANS_ADDR_TO_PAGENR(vaddr_page); |
index = DYNTRANS_ADDR_TO_PAGENR(vaddr_page); |
1452 |
cpu->cd.DYNTRANS_ARCH.phys_page[index] = NULL; |
cpu->cd.DYNTRANS_ARCH.phys_page[index] = NULL; |
1469 |
writeflag? host_page : NULL; |
writeflag? host_page : NULL; |
1470 |
cpu->cd.DYNTRANS_ARCH.phys_addr[index] = paddr_page; |
cpu->cd.DYNTRANS_ARCH.phys_addr[index] = paddr_page; |
1471 |
} |
} |
1472 |
#endif /* 32 */ |
#else /* !MODE32 */ |
1473 |
#endif /* !ALPHA */ |
x1 = (vaddr_page >> (64-DYNTRANS_L1N)) & mask1; |
1474 |
|
x2 = (vaddr_page >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2; |
1475 |
|
x3 = (vaddr_page >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) |
1476 |
|
& mask3; |
1477 |
|
l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1]; |
1478 |
|
l3 = l2->l3[x2]; |
1479 |
|
if (l3->phys_addr[x3] == paddr_page) { |
1480 |
|
if (writeflag & MEM_WRITE) |
1481 |
|
l3->host_store[x3] = host_page; |
1482 |
|
if (writeflag & MEM_DOWNGRADE) |
1483 |
|
l3->host_store[x3] = NULL; |
1484 |
|
} else { |
1485 |
|
/* Change the entire physical/host mapping: */ |
1486 |
|
l3->host_load[x3] = host_page; |
1487 |
|
l3->host_store[x3] = writeflag? host_page : NULL; |
1488 |
|
l3->phys_addr[x3] = paddr_page; |
1489 |
|
} |
1490 |
|
#endif /* !MODE32 */ |
1491 |
} |
} |
1492 |
} |
} |
1493 |
#endif /* DYNTRANS_UPDATE_TRANSLATION_TABLE */ |
#endif /* DYNTRANS_UPDATE_TRANSLATION_TABLE */ |
1501 |
* Check for breakpoints. |
* Check for breakpoints. |
1502 |
*/ |
*/ |
1503 |
if (!single_step_breakpoint) { |
if (!single_step_breakpoint) { |
1504 |
#ifdef MODE32 |
MODE_uint_t curpc = cpu->pc; |
|
uint32_t curpc = cpu->pc; |
|
|
#else |
|
|
uint64_t curpc = cpu->pc; |
|
|
#endif |
|
1505 |
int i; |
int i; |
1506 |
for (i=0; i<cpu->machine->n_breakpoints; i++) |
for (i=0; i<cpu->machine->n_breakpoints; i++) |
1507 |
if (curpc == |
if (curpc == (MODE_uint_t) |
|
#ifdef MODE32 |
|
|
(uint32_t) |
|
|
#endif |
|
1508 |
cpu->machine->breakpoint_addr[i]) { |
cpu->machine->breakpoint_addr[i]) { |
1509 |
if (!cpu->machine->instruction_trace) { |
if (!cpu->machine->instruction_trace) { |
1510 |
int old_quiet_mode = quiet_mode; |
int old_quiet_mode = quiet_mode; |
1511 |
quiet_mode = 0; |
quiet_mode = 0; |
1512 |
DISASSEMBLE(cpu, ib, 1, 0, 0); |
DISASSEMBLE(cpu, ib, 1, 0); |
1513 |
quiet_mode = old_quiet_mode; |
quiet_mode = old_quiet_mode; |
1514 |
} |
} |
1515 |
fatal("BREAKPOINT: pc = 0x%llx\n(The " |
fatal("BREAKPOINT: pc = 0x%"PRIx64"\n(The " |
1516 |
"instruction has not yet executed.)\n", |
"instruction has not yet executed.)\n", |
1517 |
(long long)cpu->pc); |
(uint64_t)cpu->pc); |
1518 |
#ifdef DYNTRANS_DELAYSLOT |
#ifdef DYNTRANS_DELAYSLOT |
1519 |
if (cpu->cd.DYNTRANS_ARCH.delay_slot != |
if (cpu->delay_slot != NOT_DELAYED) |
|
NOT_DELAYED) |
|
1520 |
fatal("ERROR! Breakpoint in a delay" |
fatal("ERROR! Breakpoint in a delay" |
1521 |
" slot! Not yet supported.\n"); |
" slot! Not yet supported.\n"); |
1522 |
#endif |
#endif |
1539 |
* (Special case for 32-bit mode: set the corresponding bit in the |
* (Special case for 32-bit mode: set the corresponding bit in the |
1540 |
* phystranslation[] array.) |
* phystranslation[] array.) |
1541 |
*/ |
*/ |
1542 |
|
/* Make sure cur_physpage is in synch: */ |
1543 |
|
cpu->cd.DYNTRANS_ARCH.cur_physpage = (void *) |
1544 |
|
cpu->cd.DYNTRANS_ARCH.cur_ic_page; |
1545 |
#ifdef MODE32 |
#ifdef MODE32 |
1546 |
if (!(cpu->cd.DYNTRANS_ARCH.cur_physpage->flags & TRANSLATIONS)) { |
if (!(cpu->cd.DYNTRANS_ARCH.cur_physpage->flags & TRANSLATIONS)) { |
1547 |
uint32_t index = DYNTRANS_ADDR_TO_PAGENR((uint32_t)addr); |
uint32_t index = DYNTRANS_ADDR_TO_PAGENR((uint32_t)addr); |
1552 |
cpu->cd.DYNTRANS_ARCH.cur_physpage->flags |= TRANSLATIONS; |
cpu->cd.DYNTRANS_ARCH.cur_physpage->flags |= TRANSLATIONS; |
1553 |
|
|
1554 |
|
|
|
#ifdef DYNTRANS_BACKEND |
|
|
/* |
|
|
* "Empty"/simple native dyntrans backend stuff: |
|
|
* |
|
|
* 1) If no translation is currently being done, but the translated |
|
|
* instruction was simple enough, then let's start making a new |
|
|
* native translation block. |
|
|
* |
|
|
* 2) If a native translation block is currently being constructed, |
|
|
* but this instruction wasn't simple enough, then end the block |
|
|
* (without including this instruction). |
|
|
* |
|
|
* 3) If a native translation block is currently being constructed, |
|
|
* and this is a simple instruction, then add it. |
|
|
*/ |
|
|
if (simple && cpu->translation_context.p == NULL && |
|
|
dyntrans_backend_enable) { |
|
|
size_t s = 0; |
|
|
|
|
|
if (cpu->translation_context.translation_buffer == NULL) { |
|
|
cpu->translation_context.translation_buffer = |
|
|
zeroed_alloc(DTB_TRANSLATION_SIZE_MAX + |
|
|
DTB_TRANSLATION_SIZE_MARGIN); |
|
|
} |
|
|
|
|
|
cpu->translation_context.p = |
|
|
cpu->translation_context.translation_buffer; |
|
|
|
|
|
cpu->translation_context.ic_page = |
|
|
cpu->cd.DYNTRANS_ARCH.cur_ic_page; |
|
|
cpu->translation_context.start_instr_call_index = |
|
|
((size_t)ic - (size_t)cpu->cd.DYNTRANS_ARCH.cur_ic_page) |
|
|
/ (sizeof(*ic)); |
|
|
|
|
|
dtb_function_prologue(&cpu->translation_context, &s); |
|
|
cpu->translation_context.p += s; |
|
|
cpu->translation_context.n_simple = 0; |
|
|
} |
|
|
|
|
|
/* If this is not a continuation of a simple translation, then |
|
|
stop now! */ |
|
|
if (cpu->translation_context.ic_page != cpu->cd.DYNTRANS_ARCH. |
|
|
cur_ic_page || ic != &cpu->cd.DYNTRANS_ARCH.cur_ic_page[ |
|
|
cpu->translation_context.start_instr_call_index + |
|
|
cpu->translation_context.n_simple]) |
|
|
simple = 0; |
|
|
|
|
|
if (cpu->translation_context.p != NULL && !simple) { |
|
|
size_t s = 0, total; |
|
|
|
|
|
if (cpu->translation_context.n_simple > 1) { |
|
|
dtb_generate_ptr_inc(cpu, &cpu->translation_context, |
|
|
&s, &cpu->cd.DYNTRANS_ARCH.next_ic, |
|
|
(cpu->translation_context.n_simple - 1) * |
|
|
sizeof(*(cpu->cd.DYNTRANS_ARCH.next_ic))); |
|
|
cpu->translation_context.p += s; |
|
|
} |
|
|
|
|
|
dtb_function_epilogue(&cpu->translation_context, &s); |
|
|
cpu->translation_context.p += s; |
|
|
|
|
|
cpu_dtb_do_fixups(cpu); |
|
|
#if 0 |
|
|
{ |
|
|
int i; |
|
|
unsigned char *addr = cpu->translation_context.translation_buffer; |
|
|
printf("index = %i\n", cpu->translation_context.start_instr_call_index); |
|
|
quiet_mode = 0; |
|
|
for (i=0; i<4*32; i+=4) |
|
|
alpha_cpu_disassemble_instr(cpu, (unsigned char *)addr + i, |
|
|
0, i, 0); |
|
|
} |
|
|
#endif |
|
|
total = (size_t)cpu->translation_context.p - |
|
|
(size_t)cpu->translation_context.translation_buffer; |
|
|
|
|
|
/* Copy the translated block to the translation cache: */ |
|
|
/* Align first: */ |
|
|
cpu->translation_cache_cur_ofs --; |
|
|
cpu->translation_cache_cur_ofs |= 31; |
|
|
cpu->translation_cache_cur_ofs ++; |
|
|
|
|
|
memcpy(cpu->translation_cache + cpu->translation_cache_cur_ofs, |
|
|
cpu->translation_context.translation_buffer, total); |
|
|
|
|
|
/* Set the ic pointer: */ |
|
|
((struct DYNTRANS_IC *)cpu->translation_context.ic_page) |
|
|
[cpu->translation_context.start_instr_call_index].f = |
|
|
(void *) |
|
|
(cpu->translation_cache + cpu->translation_cache_cur_ofs); |
|
|
|
|
|
/* Align cur_ofs afterwards as well, just to be safe. */ |
|
|
cpu->translation_cache_cur_ofs += total; |
|
|
cpu->translation_cache_cur_ofs --; |
|
|
cpu->translation_cache_cur_ofs |= 31; |
|
|
cpu->translation_cache_cur_ofs ++; |
|
|
|
|
|
/* Set the "combined instruction" flag for this page: */ |
|
|
cpu->cd.DYNTRANS_ARCH.cur_physpage = (void *) |
|
|
cpu->cd.DYNTRANS_ARCH.cur_ic_page; |
|
|
cpu->cd.DYNTRANS_ARCH.cur_physpage->flags |= COMBINATIONS; |
|
|
|
|
|
dtb_host_cacheinvalidate(0,0); /* p , size ... ); */ |
|
|
|
|
|
cpu->translation_context.p = NULL; |
|
|
} |
|
|
if (cpu->translation_context.p != NULL) { |
|
|
size_t s = 0; |
|
|
dtb_generate_fcall(cpu, &cpu->translation_context, |
|
|
&s, (size_t)ic->f, (size_t)ic); |
|
|
cpu->translation_context.p += s; |
|
|
cpu->translation_context.n_simple ++; |
|
|
} |
|
|
#endif /* DYNTRANS_BACKEND */ |
|
|
|
|
|
|
|
1555 |
/* |
/* |
1556 |
* Now it is time to check for combinations of instructions that can |
* Now it is time to check for combinations of instructions that can |
1557 |
* be converted into a single function call. |
* be converted into a single function call. |
1558 |
* |
* |
1559 |
* Note: Single-stepping or instruction tracing doesn't work with |
* Note: Single-stepping or instruction tracing doesn't work with |
1560 |
* instruction combination. |
* instruction combination. For architectures with delay slots, |
1561 |
|
* we also ignore combinations if the delay slot is across a page |
1562 |
|
* boundary. |
1563 |
*/ |
*/ |
1564 |
if (!single_step && !cpu->machine->instruction_trace) { |
if (!single_step && !cpu->machine->instruction_trace |
1565 |
|
#ifdef DYNTRANS_DELAYSLOT |
1566 |
|
&& !in_crosspage_delayslot |
1567 |
|
#endif |
1568 |
|
) { |
1569 |
if (cpu->cd.DYNTRANS_ARCH.combination_check != NULL && |
if (cpu->cd.DYNTRANS_ARCH.combination_check != NULL && |
1570 |
cpu->machine->speed_tricks) |
cpu->machine->speed_tricks) |
1571 |
cpu->cd.DYNTRANS_ARCH.combination_check(cpu, ic, |
cpu->cd.DYNTRANS_ARCH.combination_check(cpu, ic, |
1572 |
addr & (DYNTRANS_PAGESIZE - 1)); |
addr & (DYNTRANS_PAGESIZE - 1)); |
1573 |
cpu->cd.DYNTRANS_ARCH.combination_check = NULL; |
} |
1574 |
|
|
1575 |
|
cpu->cd.DYNTRANS_ARCH.combination_check = NULL; |
1576 |
|
|
1577 |
|
/* An additional check, to catch some bugs: */ |
1578 |
|
if (ic->f == ( |
1579 |
|
#ifdef DYNTRANS_DUALMODE_32 |
1580 |
|
cpu->is_32bit? instr32(to_be_translated) : |
1581 |
|
#endif |
1582 |
|
instr(to_be_translated))) { |
1583 |
|
fatal("INTERNAL ERROR: ic->f not set!\n"); |
1584 |
|
goto bad; |
1585 |
|
} |
1586 |
|
if (ic->f == NULL) { |
1587 |
|
fatal("INTERNAL ERROR: ic->f == NULL!\n"); |
1588 |
|
goto bad; |
1589 |
} |
} |
1590 |
|
|
1591 |
/* ... and finally execute the translated instruction: */ |
/* ... and finally execute the translated instruction: */ |
1592 |
if (single_step_breakpoint) { |
if ((single_step_breakpoint && cpu->delay_slot == NOT_DELAYED) |
1593 |
|
#ifdef DYNTRANS_DELAYSLOT |
1594 |
|
|| in_crosspage_delayslot |
1595 |
|
#endif |
1596 |
|
) { |
1597 |
/* |
/* |
1598 |
* Special case when single-stepping: Execute the translated |
* Special case when single-stepping: Execute the translated |
1599 |
* instruction, but then replace it with a "to be translated" |
* instruction, but then replace it with a "to be translated" |
1600 |
* directly afterwards. |
* directly afterwards. |
1601 |
*/ |
*/ |
1602 |
single_step_breakpoint = 0; |
single_step_breakpoint = 0; |
1603 |
|
#ifdef DYNTRANS_VARIABLE_INSTRUCTION_LENGTH |
1604 |
|
cpu->cd.DYNTRANS_ARCH.next_ic = ic + ic->arg[0]; |
1605 |
|
#endif |
1606 |
ic->f(cpu, ic); |
ic->f(cpu, ic); |
1607 |
ic->f = |
ic->f = |
1608 |
#ifdef DYNTRANS_DUALMODE_32 |
#ifdef DYNTRANS_DUALMODE_32 |
1609 |
cpu->is_32bit? instr32(to_be_translated) : |
cpu->is_32bit? instr32(to_be_translated) : |
1610 |
#endif |
#endif |
1611 |
instr(to_be_translated); |
instr(to_be_translated); |
1612 |
} else |
#ifdef DYNTRANS_VARIABLE_INSTRUCTION_LENGTH |
1613 |
|
ic->arg[0] = 0; |
1614 |
|
#endif |
1615 |
|
} else { |
1616 |
|
#ifdef DYNTRANS_VARIABLE_INSTRUCTION_LENGTH |
1617 |
|
cpu->cd.DYNTRANS_ARCH.next_ic = ic + ic->arg[0]; |
1618 |
|
|
1619 |
|
/* Additional check, for variable length ISAs: */ |
1620 |
|
if (ic->arg[0] == 0) { |
1621 |
|
fatal("INTERNAL ERROR: instr len = 0!\n"); |
1622 |
|
goto bad; |
1623 |
|
} |
1624 |
|
#endif |
1625 |
|
|
1626 |
|
/* Finally finally :-), execute the instruction: */ |
1627 |
ic->f(cpu, ic); |
ic->f(cpu, ic); |
1628 |
|
} |
1629 |
|
|
1630 |
return; |
return; |
1631 |
|
|
1639 |
|
|
1640 |
if (cpu->machine->instruction_trace) |
if (cpu->machine->instruction_trace) |
1641 |
#ifdef MODE32 |
#ifdef MODE32 |
1642 |
fatal(" at 0x%x\n", (int)cpu->pc); |
fatal(" at 0x%"PRIx32"\n", (uint32_t)cpu->pc); |
1643 |
#else |
#else |
1644 |
fatal(" at 0x%llx\n", (long long)cpu->pc); |
fatal(" at 0x%"PRIx64"\n", (uint64_t)cpu->pc); |
1645 |
#endif |
#endif |
1646 |
else { |
else { |
1647 |
fatal(":\n"); |
fatal(":\n"); |
1648 |
DISASSEMBLE(cpu, ib, 1, 0, 0); |
DISASSEMBLE(cpu, ib, 1, 0); |
1649 |
} |
} |
1650 |
|
|
1651 |
cpu->running = 0; |
cpu->running = 0; |